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[openwrt/staging/lynxis/omap.git] / target / linux / ramips / patches-4.9 / 0004-MIPS-ralink-add-MT7621-pcie-driver.patch
1 From fec11d4e8dc5cc79bcd7c8fd55038ac21ac39965 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 05:22:39 +0000
4 Subject: [PATCH 04/53] MIPS: ralink: add MT7621 pcie driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/pci/Makefile | 1 +
9 arch/mips/pci/pci-mt7621.c | 813 ++++++++++++++++++++++++++++++++++++++++++++
10 2 files changed, 814 insertions(+)
11 create mode 100644 arch/mips/pci/pci-mt7621.c
12
13 Index: linux-4.9.14/arch/mips/pci/Makefile
14 ===================================================================
15 --- linux-4.9.14.orig/arch/mips/pci/Makefile
16 +++ linux-4.9.14/arch/mips/pci/Makefile
17 @@ -46,6 +46,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
18 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
19 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
20 obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
21 +obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
22 obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
23 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
24 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
25 Index: linux-4.9.14/arch/mips/pci/pci-mt7621.c
26 ===================================================================
27 --- /dev/null
28 +++ linux-4.9.14/arch/mips/pci/pci-mt7621.c
29 @@ -0,0 +1,836 @@
30 +/**************************************************************************
31 + *
32 + * BRIEF MODULE DESCRIPTION
33 + * PCI init for Ralink RT2880 solution
34 + *
35 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
36 + *
37 + * This program is free software; you can redistribute it and/or modify it
38 + * under the terms of the GNU General Public License as published by the
39 + * Free Software Foundation; either version 2 of the License, or (at your
40 + * option) any later version.
41 + *
42 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
43 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
44 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
45 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
46 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
47 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
48 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
49 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
50 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
51 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 + *
53 + * You should have received a copy of the GNU General Public License along
54 + * with this program; if not, write to the Free Software Foundation, Inc.,
55 + * 675 Mass Ave, Cambridge, MA 02139, USA.
56 + *
57 + *
58 + **************************************************************************
59 + * May 2007 Bruce Chang
60 + * Initial Release
61 + *
62 + * May 2009 Bruce Chang
63 + * support RT2880/RT3883 PCIe
64 + *
65 + * May 2011 Bruce Chang
66 + * support RT6855/MT7620 PCIe
67 + *
68 + **************************************************************************
69 + */
70 +
71 +#include <linux/types.h>
72 +#include <linux/pci.h>
73 +#include <linux/kernel.h>
74 +#include <linux/slab.h>
75 +#include <linux/version.h>
76 +#include <asm/pci.h>
77 +#include <asm/io.h>
78 +#include <asm/mips-cm.h>
79 +#include <linux/init.h>
80 +#include <linux/module.h>
81 +#include <linux/delay.h>
82 +#include <linux/of.h>
83 +#include <linux/of_pci.h>
84 +#include <linux/of_irq.h>
85 +#include <linux/platform_device.h>
86 +
87 +#include <ralink_regs.h>
88 +
89 +extern void pcie_phy_init(void);
90 +extern void chk_phy_pll(void);
91 +
92 +/*
93 + * These functions and structures provide the BIOS scan and mapping of the PCI
94 + * devices.
95 + */
96 +
97 +#define CONFIG_PCIE_PORT0
98 +#define CONFIG_PCIE_PORT1
99 +#define CONFIG_PCIE_PORT2
100 +#define RALINK_PCIE0_CLK_EN (1<<24)
101 +#define RALINK_PCIE1_CLK_EN (1<<25)
102 +#define RALINK_PCIE2_CLK_EN (1<<26)
103 +
104 +#define RALINK_PCI_CONFIG_ADDR 0x20
105 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
106 +#define RALINK_INT_PCIE0 pcie_irq[0]
107 +#define RALINK_INT_PCIE1 pcie_irq[1]
108 +#define RALINK_INT_PCIE2 pcie_irq[2]
109 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
110 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
111 +#define RALINK_PCIE0_RST (1<<24)
112 +#define RALINK_PCIE1_RST (1<<25)
113 +#define RALINK_PCIE2_RST (1<<26)
114 +#define RALINK_SYSCTL_BASE 0xBE000000
115 +
116 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
117 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
118 +#define RALINK_PCI_BASE 0xBE140000
119 +
120 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
121 +#define RT6855_PCIE0_OFFSET 0x2000
122 +#define RT6855_PCIE1_OFFSET 0x3000
123 +#define RT6855_PCIE2_OFFSET 0x4000
124 +
125 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
126 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
127 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
128 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
129 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
130 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
131 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
132 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
133 +
134 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
135 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
136 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
137 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
138 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
139 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
140 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
141 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
142 +
143 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
144 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
145 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
146 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
147 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
148 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
149 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
150 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
151 +
152 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
153 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
154 +
155 +
156 +#define MV_WRITE(ofs, data) \
157 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
158 +#define MV_READ(ofs, data) \
159 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
160 +#define MV_READ_DATA(ofs) \
161 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
162 +
163 +#define MV_WRITE_16(ofs, data) \
164 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
165 +#define MV_READ_16(ofs, data) \
166 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
167 +
168 +#define MV_WRITE_8(ofs, data) \
169 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
170 +#define MV_READ_8(ofs, data) \
171 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
172 +
173 +
174 +
175 +#define RALINK_PCI_MM_MAP_BASE 0x60000000
176 +#define RALINK_PCI_IO_MAP_BASE 0x1e160000
177 +
178 +#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
179 +#define GPIO_PERST
180 +#define ASSERT_SYSRST_PCIE(val) do { \
181 + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
182 + RALINK_RSTCTRL |= val; \
183 + else \
184 + RALINK_RSTCTRL &= ~val; \
185 + } while(0)
186 +#define DEASSERT_SYSRST_PCIE(val) do { \
187 + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
188 + RALINK_RSTCTRL &= ~val; \
189 + else \
190 + RALINK_RSTCTRL |= val; \
191 + } while(0)
192 +#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
193 +#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
194 +#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
195 +#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
196 +#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
197 +#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
198 +#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
199 +#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
200 +//RALINK_SYSCFG1 bit
201 +#define RALINK_PCI_HOST_MODE_EN (1<<7)
202 +#define RALINK_PCIE_RC_MODE_EN (1<<8)
203 +//RALINK_RSTCTRL bit
204 +#define RALINK_PCIE_RST (1<<23)
205 +#define RALINK_PCI_RST (1<<24)
206 +//RALINK_CLKCFG1 bit
207 +#define RALINK_PCI_CLK_EN (1<<19)
208 +#define RALINK_PCIE_CLK_EN (1<<21)
209 +//RALINK_GPIOMODE bit
210 +#define PCI_SLOTx2 (1<<11)
211 +#define PCI_SLOTx1 (2<<11)
212 +//MTK PCIE PLL bit
213 +#define PDRV_SW_SET (1<<31)
214 +#define LC_CKDRVPD_ (1<<19)
215 +
216 +#define MEMORY_BASE 0x0
217 +static int pcie_link_status = 0;
218 +
219 +#define PCI_ACCESS_READ_1 0
220 +#define PCI_ACCESS_READ_2 1
221 +#define PCI_ACCESS_READ_4 2
222 +#define PCI_ACCESS_WRITE_1 3
223 +#define PCI_ACCESS_WRITE_2 4
224 +#define PCI_ACCESS_WRITE_4 5
225 +
226 +static int pcie_irq[3];
227 +
228 +static int config_access(unsigned char access_type, struct pci_bus *bus,
229 + unsigned int devfn, unsigned int where, u32 * data)
230 +{
231 + unsigned int slot = PCI_SLOT(devfn);
232 + u8 func = PCI_FUNC(devfn);
233 + uint32_t address_reg, data_reg;
234 + unsigned int address;
235 +
236 + address_reg = RALINK_PCI_CONFIG_ADDR;
237 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
238 +
239 + address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
240 + MV_WRITE(address_reg, address);
241 +
242 + switch(access_type) {
243 + case PCI_ACCESS_WRITE_1:
244 + MV_WRITE_8(data_reg+(where&0x3), *data);
245 + break;
246 + case PCI_ACCESS_WRITE_2:
247 + MV_WRITE_16(data_reg+(where&0x3), *data);
248 + break;
249 + case PCI_ACCESS_WRITE_4:
250 + MV_WRITE(data_reg, *data);
251 + break;
252 + case PCI_ACCESS_READ_1:
253 + MV_READ_8( data_reg+(where&0x3), data);
254 + break;
255 + case PCI_ACCESS_READ_2:
256 + MV_READ_16(data_reg+(where&0x3), data);
257 + break;
258 + case PCI_ACCESS_READ_4:
259 + MV_READ(data_reg, data);
260 + break;
261 + default:
262 + printk("no specify access type\n");
263 + break;
264 + }
265 + return 0;
266 +}
267 +
268 +static int
269 +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
270 +{
271 + return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
272 +}
273 +
274 +static int
275 +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
276 +{
277 + return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
278 +}
279 +
280 +static int
281 +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
282 +{
283 + return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
284 +}
285 +
286 +static int
287 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
288 +{
289 + if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
290 + return -1;
291 +
292 + return PCIBIOS_SUCCESSFUL;
293 +}
294 +
295 +static int
296 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
297 +{
298 + if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
299 + return -1;
300 +
301 + return PCIBIOS_SUCCESSFUL;
302 +}
303 +
304 +static int
305 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
306 +{
307 + if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
308 + return -1;
309 +
310 + return PCIBIOS_SUCCESSFUL;
311 +}
312 +
313 +
314 +static int
315 +pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
316 +{
317 + switch (size) {
318 + case 1:
319 + return read_config_byte(bus, devfn, where, (u8 *) val);
320 + case 2:
321 + return read_config_word(bus, devfn, where, (u16 *) val);
322 + default:
323 + return read_config_dword(bus, devfn, where, val);
324 + }
325 +}
326 +
327 +static int
328 +pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
329 +{
330 + switch (size) {
331 + case 1:
332 + return write_config_byte(bus, devfn, where, (u8) val);
333 + case 2:
334 + return write_config_word(bus, devfn, where, (u16) val);
335 + default:
336 + return write_config_dword(bus, devfn, where, val);
337 + }
338 +}
339 +
340 +struct pci_ops mt7621_pci_ops= {
341 + .read = pci_config_read,
342 + .write = pci_config_write,
343 +};
344 +
345 +static struct resource mt7621_res_pci_mem1 = {
346 + .name = "PCI MEM1",
347 + .start = RALINK_PCI_MM_MAP_BASE,
348 + .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
349 + .flags = IORESOURCE_MEM,
350 +};
351 +static struct resource mt7621_res_pci_io1 = {
352 + .name = "PCI I/O1",
353 + .start = RALINK_PCI_IO_MAP_BASE,
354 + .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
355 + .flags = IORESOURCE_IO,
356 +};
357 +
358 +static struct pci_controller mt7621_controller = {
359 + .pci_ops = &mt7621_pci_ops,
360 + .mem_resource = &mt7621_res_pci_mem1,
361 + .io_resource = &mt7621_res_pci_io1,
362 + .mem_offset = 0x00000000UL,
363 + .io_offset = 0x00000000UL,
364 + .io_map_base = 0xa0000000,
365 +};
366 +
367 +static void
368 +read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
369 +{
370 + unsigned int address_reg, data_reg, address;
371 +
372 + address_reg = RALINK_PCI_CONFIG_ADDR;
373 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
374 + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
375 + MV_WRITE(address_reg, address);
376 + MV_READ(data_reg, val);
377 + return;
378 +}
379 +
380 +static void
381 +write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
382 +{
383 + unsigned int address_reg, data_reg, address;
384 +
385 + address_reg = RALINK_PCI_CONFIG_ADDR;
386 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
387 + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
388 + MV_WRITE(address_reg, address);
389 + MV_WRITE(data_reg, val);
390 + return;
391 +}
392 +
393 +
394 +int __init
395 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
396 +{
397 + u16 cmd;
398 + u32 val;
399 + int irq = 0;
400 +
401 + if ((dev->bus->number == 0) && (slot == 0)) {
402 + write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
403 + read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
404 + printk("BAR0 at slot 0 = %x\n", val);
405 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
406 + } else if((dev->bus->number == 0) && (slot == 0x1)) {
407 + write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
408 + read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
409 + printk("BAR0 at slot 1 = %x\n", val);
410 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
411 + } else if((dev->bus->number == 0) && (slot == 0x2)) {
412 + write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
413 + read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
414 + printk("BAR0 at slot 2 = %x\n", val);
415 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
416 + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
417 + switch (pcie_link_status) {
418 + case 2:
419 + case 6:
420 + irq = RALINK_INT_PCIE1;
421 + break;
422 + case 4:
423 + irq = RALINK_INT_PCIE2;
424 + break;
425 + default:
426 + irq = RALINK_INT_PCIE0;
427 + }
428 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
429 + } else if ((dev->bus->number == 2) && (slot == 0x0)) {
430 + switch (pcie_link_status) {
431 + case 5:
432 + case 6:
433 + irq = RALINK_INT_PCIE2;
434 + break;
435 + default:
436 + irq = RALINK_INT_PCIE1;
437 + }
438 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
439 + } else if ((dev->bus->number == 2) && (slot == 0x1)) {
440 + switch (pcie_link_status) {
441 + case 5:
442 + case 6:
443 + irq = RALINK_INT_PCIE2;
444 + break;
445 + default:
446 + irq = RALINK_INT_PCIE1;
447 + }
448 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
449 + } else if ((dev->bus->number ==3) && (slot == 0x0)) {
450 + irq = RALINK_INT_PCIE2;
451 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
452 + } else if ((dev->bus->number ==3) && (slot == 0x1)) {
453 + irq = RALINK_INT_PCIE2;
454 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
455 + } else if ((dev->bus->number ==3) && (slot == 0x2)) {
456 + irq = RALINK_INT_PCIE2;
457 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
458 + } else {
459 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
460 + return 0;
461 + }
462 +
463 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
464 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
465 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
466 + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
467 + pci_write_config_word(dev, PCI_COMMAND, cmd);
468 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
469 + return irq;
470 +}
471 +
472 +void
473 +set_pcie_phy(u32 *addr, int start_b, int bits, int val)
474 +{
475 +// printk("0x%p:", addr);
476 +// printk(" %x", *addr);
477 + *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
478 + *(unsigned int *)(addr) |= val << start_b;
479 +// printk(" -> %x\n", *addr);
480 +}
481 +
482 +void
483 +bypass_pipe_rst(void)
484 +{
485 +#if defined (CONFIG_PCIE_PORT0)
486 + /* PCIe Port 0 */
487 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
488 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
489 +#endif
490 +#if defined (CONFIG_PCIE_PORT1)
491 + /* PCIe Port 1 */
492 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
493 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
494 +#endif
495 +#if defined (CONFIG_PCIE_PORT2)
496 + /* PCIe Port 2 */
497 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
498 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
499 +#endif
500 +}
501 +
502 +void
503 +set_phy_for_ssc(void)
504 +{
505 + unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
506 +
507 + reg = (reg >> 6) & 0x7;
508 +#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
509 + /* Set PCIe Port0 & Port1 PHY to disable SSC */
510 + /* Debug Xtal Type */
511 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
512 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
513 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
514 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
515 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
516 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
517 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
518 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
519 + printk("***** Xtal 40MHz *****\n");
520 + } else { // 25MHz | 20MHz Xtal
521 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
522 + if (reg >= 6) {
523 + printk("***** Xtal 25MHz *****\n");
524 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
525 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
526 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
527 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
528 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
529 + } else {
530 + printk("***** Xtal 20MHz *****\n");
531 + }
532 + }
533 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
534 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
535 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
536 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
537 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
538 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
539 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
540 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
541 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
542 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
543 + }
544 + /* Enable PHY and disable force mode */
545 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
546 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
547 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
548 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
549 +#endif
550 +#if defined (CONFIG_PCIE_PORT2)
551 + /* Set PCIe Port2 PHY to disable SSC */
552 + /* Debug Xtal Type */
553 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
554 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
555 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
556 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
557 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
558 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
559 + } else { // 25MHz | 20MHz Xtal
560 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
561 + if (reg >= 6) { // 25MHz Xtal
562 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
563 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
564 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
565 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
566 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
567 + }
568 + }
569 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
570 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
571 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
572 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
573 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
574 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
575 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
576 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
577 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
578 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
579 + }
580 + /* Enable PHY and disable force mode */
581 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
582 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
583 +#endif
584 +}
585 +
586 +void setup_cm_memory_region(struct resource *mem_resource)
587 +{
588 + resource_size_t mask;
589 + if (mips_cm_numiocu()) {
590 + /* FIXME: hardware doesn't accept mask values with 1s after
591 + 0s (e.g. 0xffef), so it would be great to warn if that's
592 + about to happen */
593 + mask = ~(mem_resource->end - mem_resource->start);
594 +
595 + write_gcr_reg1_base(mem_resource->start);
596 + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
597 + printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
598 + read_gcr_reg1_base(),
599 + read_gcr_reg1_mask());
600 + }
601 +}
602 +
603 +static int mt7621_pci_probe(struct platform_device *pdev)
604 +{
605 + unsigned long val = 0;
606 + int i;
607 +
608 + for (i = 0; i < 3; i++)
609 + pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
610 +
611 + iomem_resource.start = 0;
612 + iomem_resource.end= ~0;
613 + ioport_resource.start= 0;
614 + ioport_resource.end = ~0;
615 +
616 +#if defined (CONFIG_PCIE_PORT0)
617 + val = RALINK_PCIE0_RST;
618 +#endif
619 +#if defined (CONFIG_PCIE_PORT1)
620 + val |= RALINK_PCIE1_RST;
621 +#endif
622 +#if defined (CONFIG_PCIE_PORT2)
623 + val |= RALINK_PCIE2_RST;
624 +#endif
625 + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
626 + printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
627 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
628 + *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
629 + *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
630 + mdelay(100);
631 + *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
632 + mdelay(100);
633 + *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
634 +
635 + mdelay(100);
636 +#else
637 + *(unsigned int *)(0xbe000060) &= ~0x00000c00;
638 +#endif
639 +#if defined (CONFIG_PCIE_PORT0)
640 + val = RALINK_PCIE0_RST;
641 +#endif
642 +#if defined (CONFIG_PCIE_PORT1)
643 + val |= RALINK_PCIE1_RST;
644 +#endif
645 +#if defined (CONFIG_PCIE_PORT2)
646 + val |= RALINK_PCIE2_RST;
647 +#endif
648 + DEASSERT_SYSRST_PCIE(val);
649 + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
650 +
651 + if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
652 + bypass_pipe_rst();
653 + set_phy_for_ssc();
654 + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
655 +
656 +#if defined (CONFIG_PCIE_PORT0)
657 + read_config(0, 0, 0, 0x70c, &val);
658 + printk("Port 0 N_FTS = %x\n", (unsigned int)val);
659 +#endif
660 +#if defined (CONFIG_PCIE_PORT1)
661 + read_config(0, 1, 0, 0x70c, &val);
662 + printk("Port 1 N_FTS = %x\n", (unsigned int)val);
663 +#endif
664 +#if defined (CONFIG_PCIE_PORT2)
665 + read_config(0, 2, 0, 0x70c, &val);
666 + printk("Port 2 N_FTS = %x\n", (unsigned int)val);
667 +#endif
668 +
669 + RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
670 + RALINK_SYSCFG1 &= ~(0x30);
671 + RALINK_SYSCFG1 |= (2<<4);
672 + RALINK_PCIE_CLK_GEN &= 0x7fffffff;
673 + RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
674 + RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
675 + RALINK_PCIE_CLK_GEN |= 0x80000000;
676 + mdelay(50);
677 + RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
678 +
679 +
680 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
681 + *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
682 + mdelay(100);
683 +#else
684 + RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
685 +#endif
686 + mdelay(500);
687 +
688 +
689 + mdelay(500);
690 +#if defined (CONFIG_PCIE_PORT0)
691 + if(( RALINK_PCI0_STATUS & 0x1) == 0)
692 + {
693 + printk("PCIE0 no card, disable it(RST&CLK)\n");
694 + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
695 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
696 + pcie_link_status &= ~(1<<0);
697 + } else {
698 + pcie_link_status |= 1<<0;
699 + RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
700 + }
701 +#endif
702 +#if defined (CONFIG_PCIE_PORT1)
703 + if(( RALINK_PCI1_STATUS & 0x1) == 0)
704 + {
705 + printk("PCIE1 no card, disable it(RST&CLK)\n");
706 + ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
707 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
708 + pcie_link_status &= ~(1<<1);
709 + } else {
710 + pcie_link_status |= 1<<1;
711 + RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
712 + }
713 +#endif
714 +#if defined (CONFIG_PCIE_PORT2)
715 + if (( RALINK_PCI2_STATUS & 0x1) == 0) {
716 + printk("PCIE2 no card, disable it(RST&CLK)\n");
717 + ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
718 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
719 + pcie_link_status &= ~(1<<2);
720 + } else {
721 + pcie_link_status |= 1<<2;
722 + RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
723 + }
724 +#endif
725 + if (pcie_link_status == 0)
726 + return 0;
727 +
728 +/*
729 +pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
730 +3'b000 x x x
731 +3'b001 x x 0
732 +3'b010 x 0 x
733 +3'b011 x 1 0
734 +3'b100 0 x x
735 +3'b101 1 x 0
736 +3'b110 1 0 x
737 +3'b111 2 1 0
738 +*/
739 + switch(pcie_link_status) {
740 + case 2:
741 + RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
742 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
743 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
744 + break;
745 + case 4:
746 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
747 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
748 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
749 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
750 + break;
751 + case 5:
752 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
753 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
754 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
755 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
756 + break;
757 + case 6:
758 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
759 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
760 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
761 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
762 + break;
763 + }
764 + printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
765 + //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
766 +
767 +/*
768 + ioport_resource.start = mt7621_res_pci_io1.start;
769 + ioport_resource.end = mt7621_res_pci_io1.end;
770 +*/
771 +
772 + RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
773 + RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
774 +
775 +#if defined (CONFIG_PCIE_PORT0)
776 + //PCIe0
777 + if((pcie_link_status & 0x1) != 0) {
778 + RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
779 + RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
780 + RALINK_PCI0_CLASS = 0x06040001;
781 + printk("PCIE0 enabled\n");
782 + }
783 +#endif
784 +#if defined (CONFIG_PCIE_PORT1)
785 + //PCIe1
786 + if ((pcie_link_status & 0x2) != 0) {
787 + RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
788 + RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
789 + RALINK_PCI1_CLASS = 0x06040001;
790 + printk("PCIE1 enabled\n");
791 + }
792 +#endif
793 +#if defined (CONFIG_PCIE_PORT2)
794 + //PCIe2
795 + if ((pcie_link_status & 0x4) != 0) {
796 + RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
797 + RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
798 + RALINK_PCI2_CLASS = 0x06040001;
799 + printk("PCIE2 enabled\n");
800 + }
801 +#endif
802 +
803 +
804 + switch(pcie_link_status) {
805 + case 7:
806 + read_config(0, 2, 0, 0x4, &val);
807 + write_config(0, 2, 0, 0x4, val|0x4);
808 + // write_config(0, 1, 0, 0x4, val|0x7);
809 + read_config(0, 2, 0, 0x70c, &val);
810 + val &= ~(0xff)<<8;
811 + val |= 0x50<<8;
812 + write_config(0, 2, 0, 0x70c, val);
813 + case 3:
814 + case 5:
815 + case 6:
816 + read_config(0, 1, 0, 0x4, &val);
817 + write_config(0, 1, 0, 0x4, val|0x4);
818 + // write_config(0, 1, 0, 0x4, val|0x7);
819 + read_config(0, 1, 0, 0x70c, &val);
820 + val &= ~(0xff)<<8;
821 + val |= 0x50<<8;
822 + write_config(0, 1, 0, 0x70c, val);
823 + default:
824 + read_config(0, 0, 0, 0x4, &val);
825 + write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
826 + // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
827 + read_config(0, 0, 0, 0x70c, &val);
828 + val &= ~(0xff)<<8;
829 + val |= 0x50<<8;
830 + write_config(0, 0, 0, 0x70c, val);
831 + }
832 +
833 + pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
834 + setup_cm_memory_region(mt7621_controller.mem_resource);
835 + register_pci_controller(&mt7621_controller);
836 + return 0;
837 +
838 +}
839 +
840 +int pcibios_plat_dev_init(struct pci_dev *dev)
841 +{
842 + return 0;
843 +}
844 +
845 +static const struct of_device_id mt7621_pci_ids[] = {
846 + { .compatible = "mediatek,mt7621-pci" },
847 + {},
848 +};
849 +MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
850 +
851 +static struct platform_driver mt7621_pci_driver = {
852 + .probe = mt7621_pci_probe,
853 + .driver = {
854 + .name = "mt7621-pci",
855 + .owner = THIS_MODULE,
856 + .of_match_table = of_match_ptr(mt7621_pci_ids),
857 + },
858 +};
859 +
860 +static int __init mt7621_pci_init(void)
861 +{
862 + return platform_driver_register(&mt7621_pci_driver);
863 +}
864 +
865 +arch_initcall(mt7621_pci_init);
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