target/linux/sunxi/patches-4.9/0010-arm64-dts-add-Allwinner-A64-SoC-.dtsi.patch

   1 From 6bc37fac30cf01c39feb17834090089304bd1d31 Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@arm.com>
   3 Date: Mon, 18 Jan 2016 10:24:31 +0000
   4 Subject: arm64: dts: add Allwinner A64 SoC .dtsi
   5
   6 The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
   7 and the typical tablet / TV box peripherals.
   8 The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
   9 the peripherals and the memory map.
  10 Although the cores are proper 64-bit ones, the whole SoC is actually
  11 limited to 4GB (including all the supported DRAM), so we use 32-bit
  12 address and size cells. This has the nice feature of us being able to
  13 reuse the DT for 32-bit kernels as well.
  14 This .dtsi lists the hardware that we support so far.
  15
  16 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  17 Acked-by: Rob Herring <robh@kernel.org>
  18 Acked-by: Chen-Yu Tsai <wens@csie.org>
  19 [Maxime: Convert to CCU binding, drop the MMC support for now]
  20 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  21 ---
  22  Documentation/devicetree/bindings/arm/sunxi.txt |   1 +
  23  MAINTAINERS                                     |   1 +
  24  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi   | 263 ++++++++++++++++++++++++
  25  3 files changed, 265 insertions(+)
  26  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  27
  28 --- a/Documentation/devicetree/bindings/arm/sunxi.txt
  29 +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
  30 @@ -14,4 +14,5 @@ using one of the following compatible st
  31    allwinner,sun8i-a83t
  32    allwinner,sun8i-h3
  33    allwinner,sun9i-a80
  34 +  allwinner,sun50i-a64
  35    nextthing,gr8
  36 --- a/MAINTAINERS
  37 +++ b/MAINTAINERS
  38 @@ -1026,6 +1026,7 @@ L:        linux-arm-kernel@lists.infradead.org
  39  S:     Maintained
  40  N:     sun[x456789]i
  41  F:     arch/arm/boot/dts/ntc-gr8*
  42 +F:     arch/arm64/boot/dts/allwinner/
  43
  44  ARM/Allwinner SoC Clock Support
  45  M:     Emilio López <emilio@elopez.com.ar>
  46 --- /dev/null
  47 +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  48 @@ -0,0 +1,263 @@
  49 +/*
  50 + * Copyright (C) 2016 ARM Ltd.
  51 + * based on the Allwinner H3 dtsi:
  52 + *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  53 + *
  54 + * This file is dual-licensed: you can use it either under the terms
  55 + * of the GPL or the X11 license, at your option. Note that this dual
  56 + * licensing only applies to this file, and not this project as a
  57 + * whole.
  58 + *
  59 + *  a) This file is free software; you can redistribute it and/or
  60 + *     modify it under the terms of the GNU General Public License as
  61 + *     published by the Free Software Foundation; either version 2 of the
  62 + *     License, or (at your option) any later version.
  63 + *
  64 + *     This file is distributed in the hope that it will be useful,
  65 + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  66 + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  67 + *     GNU General Public License for more details.
  68 + *
  69 + * Or, alternatively,
  70 + *
  71 + *  b) Permission is hereby granted, free of charge, to any person
  72 + *     obtaining a copy of this software and associated documentation
  73 + *     files (the "Software"), to deal in the Software without
  74 + *     restriction, including without limitation the rights to use,
  75 + *     copy, modify, merge, publish, distribute, sublicense, and/or
  76 + *     sell copies of the Software, and to permit persons to whom the
  77 + *     Software is furnished to do so, subject to the following
  78 + *     conditions:
  79 + *
  80 + *     The above copyright notice and this permission notice shall be
  81 + *     included in all copies or substantial portions of the Software.
  82 + *
  83 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  84 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  85 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  86 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  87 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  88 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  89 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  90 + *     OTHER DEALINGS IN THE SOFTWARE.
  91 + */
  92 +
  93 +#include <dt-bindings/clock/sun50i-a64-ccu.h>
  94 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  95 +#include <dt-bindings/pinctrl/sun4i-a10.h>
  96 +#include <dt-bindings/reset/sun50i-a64-ccu.h>
  97 +
  98 +/ {
  99 +       interrupt-parent = <&gic>;
 100 +       #address-cells = <1>;
 101 +       #size-cells = <1>;
 102 +
 103 +       cpus {
 104 +               #address-cells = <1>;
 105 +               #size-cells = <0>;
 106 +
 107 +               cpu0: cpu@0 {
 108 +                       compatible = "arm,cortex-a53", "arm,armv8";
 109 +                       device_type = "cpu";
 110 +                       reg = <0>;
 111 +                       enable-method = "psci";
 112 +               };
 113 +
 114 +               cpu1: cpu@1 {
 115 +                       compatible = "arm,cortex-a53", "arm,armv8";
 116 +                       device_type = "cpu";
 117 +                       reg = <1>;
 118 +                       enable-method = "psci";
 119 +               };
 120 +
 121 +               cpu2: cpu@2 {
 122 +                       compatible = "arm,cortex-a53", "arm,armv8";
 123 +                       device_type = "cpu";
 124 +                       reg = <2>;
 125 +                       enable-method = "psci";
 126 +               };
 127 +
 128 +               cpu3: cpu@3 {
 129 +                       compatible = "arm,cortex-a53", "arm,armv8";
 130 +                       device_type = "cpu";
 131 +                       reg = <3>;
 132 +                       enable-method = "psci";
 133 +               };
 134 +       };
 135 +
 136 +       osc24M: osc24M_clk {
 137 +               #clock-cells = <0>;
 138 +               compatible = "fixed-clock";
 139 +               clock-frequency = <24000000>;
 140 +               clock-output-names = "osc24M";
 141 +       };
 142 +
 143 +       osc32k: osc32k_clk {
 144 +               #clock-cells = <0>;
 145 +               compatible = "fixed-clock";
 146 +               clock-frequency = <32768>;
 147 +               clock-output-names = "osc32k";
 148 +       };
 149 +
 150 +       psci {
 151 +               compatible = "arm,psci-0.2";
 152 +               method = "smc";
 153 +       };
 154 +
 155 +       timer {
 156 +               compatible = "arm,armv8-timer";
 157 +               interrupts = <GIC_PPI 13
 158 +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 159 +                            <GIC_PPI 14
 160 +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 161 +                            <GIC_PPI 11
 162 +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 163 +                            <GIC_PPI 10
 164 +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 165 +       };
 166 +
 167 +       soc {
 168 +               compatible = "simple-bus";
 169 +               #address-cells = <1>;
 170 +               #size-cells = <1>;
 171 +               ranges;
 172 +
 173 +               ccu: clock@01c20000 {
 174 +                       compatible = "allwinner,sun50i-a64-ccu";
 175 +                       reg = <0x01c20000 0x400>;
 176 +                       clocks = <&osc24M>, <&osc32k>;
 177 +                       clock-names = "hosc", "losc";
 178 +                       #clock-cells = <1>;
 179 +                       #reset-cells = <1>;
 180 +               };
 181 +
 182 +               pio: pinctrl@1c20800 {
 183 +                       compatible = "allwinner,sun50i-a64-pinctrl";
 184 +                       reg = <0x01c20800 0x400>;
 185 +                       interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 186 +                                    <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 187 +                                    <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 188 +                       clocks = <&ccu CLK_BUS_PIO>;
 189 +                       gpio-controller;
 190 +                       #gpio-cells = <3>;
 191 +                       interrupt-controller;
 192 +                       #interrupt-cells = <3>;
 193 +
 194 +                       i2c1_pins: i2c1_pins {
 195 +                               pins = "PH2", "PH3";
 196 +                               function = "i2c1";
 197 +                       };
 198 +
 199 +                       uart0_pins_a: uart0@0 {
 200 +                               pins = "PB8", "PB9";
 201 +                               function = "uart0";
 202 +                       };
 203 +               };
 204 +
 205 +               uart0: serial@1c28000 {
 206 +                       compatible = "snps,dw-apb-uart";
 207 +                       reg = <0x01c28000 0x400>;
 208 +                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 209 +                       reg-shift = <2>;
 210 +                       reg-io-width = <4>;
 211 +                       clocks = <&ccu CLK_BUS_UART0>;
 212 +                       resets = <&ccu RST_BUS_UART0>;
 213 +                       status = "disabled";
 214 +               };
 215 +
 216 +               uart1: serial@1c28400 {
 217 +                       compatible = "snps,dw-apb-uart";
 218 +                       reg = <0x01c28400 0x400>;
 219 +                       interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 220 +                       reg-shift = <2>;
 221 +                       reg-io-width = <4>;
 222 +                       clocks = <&ccu CLK_BUS_UART1>;
 223 +                       resets = <&ccu RST_BUS_UART1>;
 224 +                       status = "disabled";
 225 +               };
 226 +
 227 +               uart2: serial@1c28800 {
 228 +                       compatible = "snps,dw-apb-uart";
 229 +                       reg = <0x01c28800 0x400>;
 230 +                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 231 +                       reg-shift = <2>;
 232 +                       reg-io-width = <4>;
 233 +                       clocks = <&ccu CLK_BUS_UART2>;
 234 +                       resets = <&ccu RST_BUS_UART2>;
 235 +                       status = "disabled";
 236 +               };
 237 +
 238 +               uart3: serial@1c28c00 {
 239 +                       compatible = "snps,dw-apb-uart";
 240 +                       reg = <0x01c28c00 0x400>;
 241 +                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 242 +                       reg-shift = <2>;
 243 +                       reg-io-width = <4>;
 244 +                       clocks = <&ccu CLK_BUS_UART3>;
 245 +                       resets = <&ccu RST_BUS_UART3>;
 246 +                       status = "disabled";
 247 +               };
 248 +
 249 +               uart4: serial@1c29000 {
 250 +                       compatible = "snps,dw-apb-uart";
 251 +                       reg = <0x01c29000 0x400>;
 252 +                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 253 +                       reg-shift = <2>;
 254 +                       reg-io-width = <4>;
 255 +                       clocks = <&ccu CLK_BUS_UART4>;
 256 +                       resets = <&ccu RST_BUS_UART4>;
 257 +                       status = "disabled";
 258 +               };
 259 +
 260 +               i2c0: i2c@1c2ac00 {
 261 +                       compatible = "allwinner,sun6i-a31-i2c";
 262 +                       reg = <0x01c2ac00 0x400>;
 263 +                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 264 +                       clocks = <&ccu CLK_BUS_I2C0>;
 265 +                       resets = <&ccu RST_BUS_I2C0>;
 266 +                       status = "disabled";
 267 +                       #address-cells = <1>;
 268 +                       #size-cells = <0>;
 269 +               };
 270 +
 271 +               i2c1: i2c@1c2b000 {
 272 +                       compatible = "allwinner,sun6i-a31-i2c";
 273 +                       reg = <0x01c2b000 0x400>;
 274 +                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 275 +                       clocks = <&ccu CLK_BUS_I2C1>;
 276 +                       resets = <&ccu RST_BUS_I2C1>;
 277 +                       status = "disabled";
 278 +                       #address-cells = <1>;
 279 +                       #size-cells = <0>;
 280 +               };
 281 +
 282 +               i2c2: i2c@1c2b400 {
 283 +                       compatible = "allwinner,sun6i-a31-i2c";
 284 +                       reg = <0x01c2b400 0x400>;
 285 +                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 286 +                       clocks = <&ccu CLK_BUS_I2C2>;
 287 +                       resets = <&ccu RST_BUS_I2C2>;
 288 +                       status = "disabled";
 289 +                       #address-cells = <1>;
 290 +                       #size-cells = <0>;
 291 +               };
 292 +
 293 +               gic: interrupt-controller@1c81000 {
 294 +                       compatible = "arm,gic-400";
 295 +                       reg = <0x01c81000 0x1000>,
 296 +                             <0x01c82000 0x2000>,
 297 +                             <0x01c84000 0x2000>,
 298 +                             <0x01c86000 0x2000>;
 299 +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 300 +                       interrupt-controller;
 301 +                       #interrupt-cells = <3>;
 302 +               };
 303 +
 304 +               rtc: rtc@1f00000 {
 305 +                       compatible = "allwinner,sun6i-a31-rtc";
 306 +                       reg = <0x01f00000 0x54>;
 307 +                       interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 308 +                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 309 +               };
 310 +       };
 311 +};