target/linux/mediatek/patches-4.14/0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch

   1 From e0e3768b73daae674c69db1f71718894274b7bfc Mon Sep 17 00:00:00 2001
   2 From: Ryder Lee <ryder.lee@mediatek.com>
   3 Date: Thu, 4 Jan 2018 15:44:07 +0800
   4 Subject: [PATCH 184/224] ASoC: mediatek: add some core clocks for MT2701 AFE
   5
   6 Add three core clocks for MT2701 AFE.
   7
   8 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
   9 Signed-off-by: Mark Brown <broonie@kernel.org>
  10 ---
  11  sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 30 ++++++++++++++++++++++-
  12  sound/soc/mediatek/mt2701/mt2701-afe-common.h     |  3 +++
  13  2 files changed, 32 insertions(+), 1 deletion(-)
  14
  15 --- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  16 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  17 @@ -18,8 +18,11 @@
  18  #include "mt2701-afe-clock-ctrl.h"
  19
  20  static const char *const base_clks[] = {
  21 +       [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
  22         [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
  23         [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
  24 +       [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
  25 +       [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
  26         [MT2701_AUDSYS_AFE] = "audio_afe_pd",
  27         [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
  28         [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
  29 @@ -169,10 +172,26 @@ static int mt2701_afe_enable_audsys(stru
  30         struct mt2701_afe_private *afe_priv = afe->platform_priv;
  31         int ret;
  32
  33 -       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  34 +       /* Enable infra clock gate */
  35 +       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  36         if (ret)
  37                 return ret;
  38
  39 +       /* Enable top a1sys clock gate */
  40 +       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  41 +       if (ret)
  42 +               goto err_a1sys;
  43 +
  44 +       /* Enable top a2sys clock gate */
  45 +       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  46 +       if (ret)
  47 +               goto err_a2sys;
  48 +
  49 +       /* Internal clock gates */
  50 +       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  51 +       if (ret)
  52 +               goto err_afe;
  53 +
  54         ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  55         if (ret)
  56                 goto err_audio_a1sys;
  57 @@ -193,6 +212,12 @@ err_audio_a2sys:
  58         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  59  err_audio_a1sys:
  60         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  61 +err_afe:
  62 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  63 +err_a2sys:
  64 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  65 +err_a1sys:
  66 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  67
  68         return ret;
  69  }
  70 @@ -205,6 +230,9 @@ static void mt2701_afe_disable_audsys(st
  71         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
  72         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  73         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  74 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  75 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  76 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  77  }
  78
  79  int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
  80 --- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  81 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  82 @@ -61,8 +61,11 @@ enum {
  83  };
  84
  85  enum audio_base_clock {
  86 +       MT2701_INFRA_SYS_AUDIO,
  87         MT2701_TOP_AUD_MCLK_SRC0,
  88         MT2701_TOP_AUD_MCLK_SRC1,
  89 +       MT2701_TOP_AUD_A1SYS,
  90 +       MT2701_TOP_AUD_A2SYS,
  91         MT2701_AUDSYS_AFE,
  92         MT2701_AUDSYS_AFE_CONN,
  93         MT2701_AUDSYS_A1SYS,