projects / openwrt / staging / lynxis.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: bump 4.14 to 4.14.44
[openwrt/staging/lynxis.git] / target / linux / mediatek / patches-4.14 / 0150-clk-mediatek-add-clock-support-for-MT7622-SoC.patch
1 From b24e830d69f1fa637284c093410645a059b60028 Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Thu, 5 Oct 2017 11:50:24 +0800
4 Subject: [PATCH 150/224] clk: mediatek: add clock support for MT7622 SoC
5
6 Add all supported clocks exported from every susbystem found on MT7622 SoC
7 such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys,
8 ethsys and audsys.
9
10 Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
13 ---
14 drivers/clk/mediatek/Kconfig | 30 ++
15 drivers/clk/mediatek/Makefile | 4 +
16 drivers/clk/mediatek/clk-mt7622-aud.c | 195 +++++++++
17 drivers/clk/mediatek/clk-mt7622-eth.c | 156 +++++++
18 drivers/clk/mediatek/clk-mt7622-hif.c | 169 ++++++++
19 drivers/clk/mediatek/clk-mt7622.c | 780 ++++++++++++++++++++++++++++++++++
20 6 files changed, 1334 insertions(+)
21 create mode 100644 drivers/clk/mediatek/clk-mt7622-aud.c
22 create mode 100644 drivers/clk/mediatek/clk-mt7622-eth.c
23 create mode 100644 drivers/clk/mediatek/clk-mt7622-hif.c
24 create mode 100644 drivers/clk/mediatek/clk-mt7622.c
25
26 --- a/drivers/clk/mediatek/Kconfig
27 +++ b/drivers/clk/mediatek/Kconfig
28 @@ -132,6 +132,36 @@ config COMMON_CLK_MT6797_VENCSYS
29 ---help---
30 This driver supports Mediatek MT6797 vencsys clocks.
31
32 +config COMMON_CLK_MT7622
33 + bool "Clock driver for MediaTek MT7622"
34 + depends on ARCH_MEDIATEK || COMPILE_TEST
35 + select COMMON_CLK_MEDIATEK
36 + default ARCH_MEDIATEK
37 + ---help---
38 + This driver supports MediaTek MT7622 basic clocks and clocks
39 + required for various periperals found on MediaTek.
40 +
41 +config COMMON_CLK_MT7622_ETHSYS
42 + bool "Clock driver for MediaTek MT7622 ETHSYS"
43 + depends on COMMON_CLK_MT7622
44 + ---help---
45 + This driver add support for clocks for Ethernet and SGMII
46 + required on MediaTek MT7622 SoC.
47 +
48 +config COMMON_CLK_MT7622_HIFSYS
49 + bool "Clock driver for MediaTek MT7622 HIFSYS"
50 + depends on COMMON_CLK_MT7622
51 + ---help---
52 + This driver supports MediaTek MT7622 HIFSYS clocks providing
53 + to PCI-E and USB.
54 +
55 +config COMMON_CLK_MT7622_AUDSYS
56 + bool "Clock driver for MediaTek MT7622 AUDSYS"
57 + depends on COMMON_CLK_MT7622
58 + ---help---
59 + This driver supports MediaTek MT7622 AUDSYS clocks providing
60 + to audio consumers such as I2S and TDM.
61 +
62 config COMMON_CLK_MT8135
63 bool "Clock driver for Mediatek MT8135"
64 depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
65 --- a/drivers/clk/mediatek/Makefile
66 +++ b/drivers/clk/mediatek/Makefile
67 @@ -21,5 +21,9 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) +
68 obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
69 obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
70 obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
71 +obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
72 +obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
73 +obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
74 +obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
75 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
76 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
77 --- /dev/null
78 +++ b/drivers/clk/mediatek/clk-mt7622-aud.c
79 @@ -0,0 +1,195 @@
80 +/*
81 + * Copyright (c) 2017 MediaTek Inc.
82 + * Author: Chen Zhong <chen.zhong@mediatek.com>
83 + * Sean Wang <sean.wang@mediatek.com>
84 + *
85 + * This program is free software; you can redistribute it and/or modify
86 + * it under the terms of the GNU General Public License version 2 as
87 + * published by the Free Software Foundation.
88 + *
89 + * This program is distributed in the hope that it will be useful,
90 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
91 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
92 + * GNU General Public License for more details.
93 + */
94 +
95 +#include <linux/clk-provider.h>
96 +#include <linux/of.h>
97 +#include <linux/of_address.h>
98 +#include <linux/of_device.h>
99 +#include <linux/platform_device.h>
100 +
101 +#include "clk-mtk.h"
102 +#include "clk-gate.h"
103 +
104 +#include <dt-bindings/clock/mt7622-clk.h>
105 +
106 +#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
107 + .id = _id, \
108 + .name = _name, \
109 + .parent_name = _parent, \
110 + .regs = &audio0_cg_regs, \
111 + .shift = _shift, \
112 + .ops = &mtk_clk_gate_ops_no_setclr, \
113 + }
114 +
115 +#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
116 + .id = _id, \
117 + .name = _name, \
118 + .parent_name = _parent, \
119 + .regs = &audio1_cg_regs, \
120 + .shift = _shift, \
121 + .ops = &mtk_clk_gate_ops_no_setclr, \
122 + }
123 +
124 +#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
125 + .id = _id, \
126 + .name = _name, \
127 + .parent_name = _parent, \
128 + .regs = &audio2_cg_regs, \
129 + .shift = _shift, \
130 + .ops = &mtk_clk_gate_ops_no_setclr, \
131 + }
132 +
133 +#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
134 + .id = _id, \
135 + .name = _name, \
136 + .parent_name = _parent, \
137 + .regs = &audio3_cg_regs, \
138 + .shift = _shift, \
139 + .ops = &mtk_clk_gate_ops_no_setclr, \
140 + }
141 +
142 +static const struct mtk_gate_regs audio0_cg_regs = {
143 + .set_ofs = 0x0,
144 + .clr_ofs = 0x0,
145 + .sta_ofs = 0x0,
146 +};
147 +
148 +static const struct mtk_gate_regs audio1_cg_regs = {
149 + .set_ofs = 0x10,
150 + .clr_ofs = 0x10,
151 + .sta_ofs = 0x10,
152 +};
153 +
154 +static const struct mtk_gate_regs audio2_cg_regs = {
155 + .set_ofs = 0x14,
156 + .clr_ofs = 0x14,
157 + .sta_ofs = 0x14,
158 +};
159 +
160 +static const struct mtk_gate_regs audio3_cg_regs = {
161 + .set_ofs = 0x634,
162 + .clr_ofs = 0x634,
163 + .sta_ofs = 0x634,
164 +};
165 +
166 +static const struct mtk_gate audio_clks[] = {
167 + /* AUDIO0 */
168 + GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
169 + GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
170 + GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
171 + GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
172 + /* AUDIO1 */
173 + GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
174 + GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
175 + GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
176 + GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
177 + GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
178 + GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
179 + GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
180 + GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
181 + GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
182 + GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
183 + GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
184 + GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
185 + GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
186 + GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
187 + GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
188 + /* AUDIO2 */
189 + GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
190 + GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
191 + GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
192 + GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
193 + GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
194 + GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
195 + GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
196 + GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
197 + GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
198 + GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
199 + GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
200 + GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
201 + GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
202 + GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
203 + GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
204 + GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
205 + GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
206 + GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
207 + /* AUDIO3 */
208 + GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
209 + GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
210 + GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
211 + GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
212 + GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
213 + GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
214 + GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
215 + GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
216 + GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
217 +};
218 +
219 +static int clk_mt7622_audiosys_init(struct platform_device *pdev)
220 +{
221 + struct clk_onecell_data *clk_data;
222 + struct device_node *node = pdev->dev.of_node;
223 + int r;
224 +
225 + clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
226 +
227 + mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
228 + clk_data);
229 +
230 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
231 + if (r)
232 + dev_err(&pdev->dev,
233 + "could not register clock provider: %s: %d\n",
234 + pdev->name, r);
235 +
236 + return r;
237 +}
238 +
239 +static const struct of_device_id of_match_clk_mt7622_aud[] = {
240 + {
241 + .compatible = "mediatek,mt7622-audsys",
242 + .data = clk_mt7622_audiosys_init,
243 + }, {
244 + /* sentinel */
245 + }
246 +};
247 +
248 +static int clk_mt7622_aud_probe(struct platform_device *pdev)
249 +{
250 + int (*clk_init)(struct platform_device *);
251 + int r;
252 +
253 + clk_init = of_device_get_match_data(&pdev->dev);
254 + if (!clk_init)
255 + return -EINVAL;
256 +
257 + r = clk_init(pdev);
258 + if (r)
259 + dev_err(&pdev->dev,
260 + "could not register clock provider: %s: %d\n",
261 + pdev->name, r);
262 +
263 + return r;
264 +}
265 +
266 +static struct platform_driver clk_mt7622_aud_drv = {
267 + .probe = clk_mt7622_aud_probe,
268 + .driver = {
269 + .name = "clk-mt7622-aud",
270 + .of_match_table = of_match_clk_mt7622_aud,
271 + },
272 +};
273 +
274 +builtin_platform_driver(clk_mt7622_aud_drv);
275 --- /dev/null
276 +++ b/drivers/clk/mediatek/clk-mt7622-eth.c
277 @@ -0,0 +1,156 @@
278 +/*
279 + * Copyright (c) 2017 MediaTek Inc.
280 + * Author: Chen Zhong <chen.zhong@mediatek.com>
281 + * Sean Wang <sean.wang@mediatek.com>
282 + *
283 + * This program is free software; you can redistribute it and/or modify
284 + * it under the terms of the GNU General Public License version 2 as
285 + * published by the Free Software Foundation.
286 + *
287 + * This program is distributed in the hope that it will be useful,
288 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
289 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
290 + * GNU General Public License for more details.
291 + */
292 +
293 +#include <linux/clk-provider.h>
294 +#include <linux/of.h>
295 +#include <linux/of_address.h>
296 +#include <linux/of_device.h>
297 +#include <linux/platform_device.h>
298 +
299 +#include "clk-mtk.h"
300 +#include "clk-gate.h"
301 +
302 +#include <dt-bindings/clock/mt7622-clk.h>
303 +
304 +#define GATE_ETH(_id, _name, _parent, _shift) { \
305 + .id = _id, \
306 + .name = _name, \
307 + .parent_name = _parent, \
308 + .regs = &eth_cg_regs, \
309 + .shift = _shift, \
310 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
311 + }
312 +
313 +static const struct mtk_gate_regs eth_cg_regs = {
314 + .set_ofs = 0x30,
315 + .clr_ofs = 0x30,
316 + .sta_ofs = 0x30,
317 +};
318 +
319 +static const struct mtk_gate eth_clks[] = {
320 + GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
321 + GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
322 + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
323 + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
324 + GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
325 +};
326 +
327 +static const struct mtk_gate_regs sgmii_cg_regs = {
328 + .set_ofs = 0xE4,
329 + .clr_ofs = 0xE4,
330 + .sta_ofs = 0xE4,
331 +};
332 +
333 +#define GATE_SGMII(_id, _name, _parent, _shift) { \
334 + .id = _id, \
335 + .name = _name, \
336 + .parent_name = _parent, \
337 + .regs = &sgmii_cg_regs, \
338 + .shift = _shift, \
339 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
340 + }
341 +
342 +static const struct mtk_gate sgmii_clks[] = {
343 + GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
344 + "ssusb_tx250m", 2),
345 + GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
346 + "ssusb_eq_rx250m", 3),
347 + GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
348 + "ssusb_cdr_ref", 4),
349 + GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
350 + "ssusb_cdr_fb", 5),
351 +};
352 +
353 +static int clk_mt7622_ethsys_init(struct platform_device *pdev)
354 +{
355 + struct clk_onecell_data *clk_data;
356 + struct device_node *node = pdev->dev.of_node;
357 + int r;
358 +
359 + clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
360 +
361 + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
362 + clk_data);
363 +
364 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
365 + if (r)
366 + dev_err(&pdev->dev,
367 + "could not register clock provider: %s: %d\n",
368 + pdev->name, r);
369 +
370 + mtk_register_reset_controller(node, 1, 0x34);
371 +
372 + return r;
373 +}
374 +
375 +static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
376 +{
377 + struct clk_onecell_data *clk_data;
378 + struct device_node *node = pdev->dev.of_node;
379 + int r;
380 +
381 + clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
382 +
383 + mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
384 + clk_data);
385 +
386 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
387 + if (r)
388 + dev_err(&pdev->dev,
389 + "could not register clock provider: %s: %d\n",
390 + pdev->name, r);
391 +
392 + return r;
393 +}
394 +
395 +static const struct of_device_id of_match_clk_mt7622_eth[] = {
396 + {
397 + .compatible = "mediatek,mt7622-ethsys",
398 + .data = clk_mt7622_ethsys_init,
399 + }, {
400 + .compatible = "mediatek,mt7622-sgmiisys",
401 + .data = clk_mt7622_sgmiisys_init,
402 + }, {
403 + /* sentinel */
404 + }
405 +};
406 +
407 +static int clk_mt7622_eth_probe(struct platform_device *pdev)
408 +{
409 + int (*clk_init)(struct platform_device *);
410 + int r;
411 +
412 + clk_init = of_device_get_match_data(&pdev->dev);
413 + if (!clk_init)
414 + return -EINVAL;
415 +
416 + r = clk_init(pdev);
417 + if (r)
418 + dev_err(&pdev->dev,
419 + "could not register clock provider: %s: %d\n",
420 + pdev->name, r);
421 +
422 + return r;
423 +}
424 +
425 +static struct platform_driver clk_mt7622_eth_drv = {
426 + .probe = clk_mt7622_eth_probe,
427 + .driver = {
428 + .name = "clk-mt7622-eth",
429 + .of_match_table = of_match_clk_mt7622_eth,
430 + },
431 +};
432 +
433 +builtin_platform_driver(clk_mt7622_eth_drv);
434 --- /dev/null
435 +++ b/drivers/clk/mediatek/clk-mt7622-hif.c
436 @@ -0,0 +1,169 @@
437 +/*
438 + * Copyright (c) 2017 MediaTek Inc.
439 + * Author: Chen Zhong <chen.zhong@mediatek.com>
440 + * Sean Wang <sean.wang@mediatek.com>
441 + *
442 + * This program is free software; you can redistribute it and/or modify
443 + * it under the terms of the GNU General Public License version 2 as
444 + * published by the Free Software Foundation.
445 + *
446 + * This program is distributed in the hope that it will be useful,
447 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
448 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
449 + * GNU General Public License for more details.
450 + */
451 +
452 +#include <linux/clk-provider.h>
453 +#include <linux/of.h>
454 +#include <linux/of_address.h>
455 +#include <linux/of_device.h>
456 +#include <linux/platform_device.h>
457 +
458 +#include "clk-mtk.h"
459 +#include "clk-gate.h"
460 +
461 +#include <dt-bindings/clock/mt7622-clk.h>
462 +
463 +#define GATE_PCIE(_id, _name, _parent, _shift) { \
464 + .id = _id, \
465 + .name = _name, \
466 + .parent_name = _parent, \
467 + .regs = &pcie_cg_regs, \
468 + .shift = _shift, \
469 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
470 + }
471 +
472 +#define GATE_SSUSB(_id, _name, _parent, _shift) { \
473 + .id = _id, \
474 + .name = _name, \
475 + .parent_name = _parent, \
476 + .regs = &ssusb_cg_regs, \
477 + .shift = _shift, \
478 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
479 + }
480 +
481 +static const struct mtk_gate_regs pcie_cg_regs = {
482 + .set_ofs = 0x30,
483 + .clr_ofs = 0x30,
484 + .sta_ofs = 0x30,
485 +};
486 +
487 +static const struct mtk_gate_regs ssusb_cg_regs = {
488 + .set_ofs = 0x30,
489 + .clr_ofs = 0x30,
490 + .sta_ofs = 0x30,
491 +};
492 +
493 +static const struct mtk_gate ssusb_clks[] = {
494 + GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
495 + "to_u2_phy_1p", 0),
496 + GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
497 + GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
498 + GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
499 + GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
500 + GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
501 +};
502 +
503 +static const struct mtk_gate pcie_clks[] = {
504 + GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
505 + GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
506 + GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
507 + GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
508 + GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
509 + GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
510 + GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
511 + GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
512 + GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
513 + GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
514 + GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
515 + GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
516 + GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
517 + GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
518 + GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
519 + GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
520 + GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
521 +};
522 +
523 +static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
524 +{
525 + struct clk_onecell_data *clk_data;
526 + struct device_node *node = pdev->dev.of_node;
527 + int r;
528 +
529 + clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
530 +
531 + mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
532 + clk_data);
533 +
534 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
535 + if (r)
536 + dev_err(&pdev->dev,
537 + "could not register clock provider: %s: %d\n",
538 + pdev->name, r);
539 +
540 + mtk_register_reset_controller(node, 1, 0x34);
541 +
542 + return r;
543 +}
544 +
545 +static int clk_mt7622_pciesys_init(struct platform_device *pdev)
546 +{
547 + struct clk_onecell_data *clk_data;
548 + struct device_node *node = pdev->dev.of_node;
549 + int r;
550 +
551 + clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
552 +
553 + mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
554 + clk_data);
555 +
556 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
557 + if (r)
558 + dev_err(&pdev->dev,
559 + "could not register clock provider: %s: %d\n",
560 + pdev->name, r);
561 +
562 + mtk_register_reset_controller(node, 1, 0x34);
563 +
564 + return r;
565 +}
566 +
567 +static const struct of_device_id of_match_clk_mt7622_hif[] = {
568 + {
569 + .compatible = "mediatek,mt7622-pciesys",
570 + .data = clk_mt7622_pciesys_init,
571 + }, {
572 + .compatible = "mediatek,mt7622-ssusbsys",
573 + .data = clk_mt7622_ssusbsys_init,
574 + }, {
575 + /* sentinel */
576 + }
577 +};
578 +
579 +static int clk_mt7622_hif_probe(struct platform_device *pdev)
580 +{
581 + int (*clk_init)(struct platform_device *);
582 + int r;
583 +
584 + clk_init = of_device_get_match_data(&pdev->dev);
585 + if (!clk_init)
586 + return -EINVAL;
587 +
588 + r = clk_init(pdev);
589 + if (r)
590 + dev_err(&pdev->dev,
591 + "could not register clock provider: %s: %d\n",
592 + pdev->name, r);
593 +
594 + return r;
595 +}
596 +
597 +static struct platform_driver clk_mt7622_hif_drv = {
598 + .probe = clk_mt7622_hif_probe,
599 + .driver = {
600 + .name = "clk-mt7622-hif",
601 + .of_match_table = of_match_clk_mt7622_hif,
602 + },
603 +};
604 +
605 +builtin_platform_driver(clk_mt7622_hif_drv);
606 --- /dev/null
607 +++ b/drivers/clk/mediatek/clk-mt7622.c
608 @@ -0,0 +1,780 @@
609 +/*
610 + * Copyright (c) 2017 MediaTek Inc.
611 + * Author: Chen Zhong <chen.zhong@mediatek.com>
612 + * Sean Wang <sean.wang@mediatek.com>
613 + *
614 + * This program is free software; you can redistribute it and/or modify
615 + * it under the terms of the GNU General Public License version 2 as
616 + * published by the Free Software Foundation.
617 + *
618 + * This program is distributed in the hope that it will be useful,
619 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
620 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
621 + * GNU General Public License for more details.
622 + */
623 +
624 +#include <linux/clk-provider.h>
625 +#include <linux/of.h>
626 +#include <linux/of_address.h>
627 +#include <linux/of_device.h>
628 +#include <linux/platform_device.h>
629 +
630 +#include "clk-mtk.h"
631 +#include "clk-gate.h"
632 +#include "clk-cpumux.h"
633 +
634 +#include <dt-bindings/clock/mt7622-clk.h>
635 +#include <linux/clk.h> /* for consumer */
636 +
637 +#define MT7622_PLL_FMAX (2500UL * MHZ)
638 +#define CON0_MT7622_RST_BAR BIT(27)
639 +
640 +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
641 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
642 + _pcw_shift, _div_table, _parent_name) { \
643 + .id = _id, \
644 + .name = _name, \
645 + .reg = _reg, \
646 + .pwr_reg = _pwr_reg, \
647 + .en_mask = _en_mask, \
648 + .flags = _flags, \
649 + .rst_bar_mask = CON0_MT7622_RST_BAR, \
650 + .fmax = MT7622_PLL_FMAX, \
651 + .pcwbits = _pcwbits, \
652 + .pd_reg = _pd_reg, \
653 + .pd_shift = _pd_shift, \
654 + .tuner_reg = _tuner_reg, \
655 + .pcw_reg = _pcw_reg, \
656 + .pcw_shift = _pcw_shift, \
657 + .div_table = _div_table, \
658 + .parent_name = _parent_name, \
659 + }
660 +
661 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
662 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
663 + _pcw_shift) \
664 + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
665 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
666 + NULL, "clkxtal")
667 +
668 +#define GATE_APMIXED(_id, _name, _parent, _shift) { \
669 + .id = _id, \
670 + .name = _name, \
671 + .parent_name = _parent, \
672 + .regs = &apmixed_cg_regs, \
673 + .shift = _shift, \
674 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
675 + }
676 +
677 +#define GATE_INFRA(_id, _name, _parent, _shift) { \
678 + .id = _id, \
679 + .name = _name, \
680 + .parent_name = _parent, \
681 + .regs = &infra_cg_regs, \
682 + .shift = _shift, \
683 + .ops = &mtk_clk_gate_ops_setclr, \
684 + }
685 +
686 +#define GATE_TOP0(_id, _name, _parent, _shift) { \
687 + .id = _id, \
688 + .name = _name, \
689 + .parent_name = _parent, \
690 + .regs = &top0_cg_regs, \
691 + .shift = _shift, \
692 + .ops = &mtk_clk_gate_ops_no_setclr, \
693 + }
694 +
695 +#define GATE_TOP1(_id, _name, _parent, _shift) { \
696 + .id = _id, \
697 + .name = _name, \
698 + .parent_name = _parent, \
699 + .regs = &top1_cg_regs, \
700 + .shift = _shift, \
701 + .ops = &mtk_clk_gate_ops_no_setclr, \
702 + }
703 +
704 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
705 + .id = _id, \
706 + .name = _name, \
707 + .parent_name = _parent, \
708 + .regs = &peri0_cg_regs, \
709 + .shift = _shift, \
710 + .ops = &mtk_clk_gate_ops_setclr, \
711 + }
712 +
713 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
714 + .id = _id, \
715 + .name = _name, \
716 + .parent_name = _parent, \
717 + .regs = &peri1_cg_regs, \
718 + .shift = _shift, \
719 + .ops = &mtk_clk_gate_ops_setclr, \
720 + }
721 +
722 +static DEFINE_SPINLOCK(mt7622_clk_lock);
723 +
724 +static const char * const infra_mux1_parents[] = {
725 + "clkxtal",
726 + "armpll",
727 + "main_core_en",
728 + "armpll"
729 +};
730 +
731 +static const char * const axi_parents[] = {
732 + "clkxtal",
733 + "syspll1_d2",
734 + "syspll_d5",
735 + "syspll1_d4",
736 + "univpll_d5",
737 + "univpll2_d2",
738 + "univpll_d7"
739 +};
740 +
741 +static const char * const mem_parents[] = {
742 + "clkxtal",
743 + "dmpll_ck"
744 +};
745 +
746 +static const char * const ddrphycfg_parents[] = {
747 + "clkxtal",
748 + "syspll1_d8"
749 +};
750 +
751 +static const char * const eth_parents[] = {
752 + "clkxtal",
753 + "syspll1_d2",
754 + "univpll1_d2",
755 + "syspll1_d4",
756 + "univpll_d5",
757 + "clk_null",
758 + "univpll_d7"
759 +};
760 +
761 +static const char * const pwm_parents[] = {
762 + "clkxtal",
763 + "univpll2_d4"
764 +};
765 +
766 +static const char * const f10m_ref_parents[] = {
767 + "clkxtal",
768 + "syspll4_d16"
769 +};
770 +
771 +static const char * const nfi_infra_parents[] = {
772 + "clkxtal",
773 + "clkxtal",
774 + "clkxtal",
775 + "clkxtal",
776 + "clkxtal",
777 + "clkxtal",
778 + "clkxtal",
779 + "clkxtal",
780 + "univpll2_d8",
781 + "syspll1_d8",
782 + "univpll1_d8",
783 + "syspll4_d2",
784 + "univpll2_d4",
785 + "univpll3_d2",
786 + "syspll1_d4"
787 +};
788 +
789 +static const char * const flash_parents[] = {
790 + "clkxtal",
791 + "univpll_d80_d4",
792 + "syspll2_d8",
793 + "syspll3_d4",
794 + "univpll3_d4",
795 + "univpll1_d8",
796 + "syspll2_d4",
797 + "univpll2_d4"
798 +};
799 +
800 +static const char * const uart_parents[] = {
801 + "clkxtal",
802 + "univpll2_d8"
803 +};
804 +
805 +static const char * const spi0_parents[] = {
806 + "clkxtal",
807 + "syspll3_d2",
808 + "clkxtal",
809 + "syspll2_d4",
810 + "syspll4_d2",
811 + "univpll2_d4",
812 + "univpll1_d8",
813 + "clkxtal"
814 +};
815 +
816 +static const char * const spi1_parents[] = {
817 + "clkxtal",
818 + "syspll3_d2",
819 + "clkxtal",
820 + "syspll4_d4",
821 + "syspll4_d2",
822 + "univpll2_d4",
823 + "univpll1_d8",
824 + "clkxtal"
825 +};
826 +
827 +static const char * const msdc30_0_parents[] = {
828 + "clkxtal",
829 + "univpll2_d16",
830 + "univ48m"
831 +};
832 +
833 +static const char * const a1sys_hp_parents[] = {
834 + "clkxtal",
835 + "aud1pll_ck",
836 + "aud2pll_ck",
837 + "clkxtal"
838 +};
839 +
840 +static const char * const intdir_parents[] = {
841 + "clkxtal",
842 + "syspll_d2",
843 + "univpll_d2",
844 + "sgmiipll_ck"
845 +};
846 +
847 +static const char * const aud_intbus_parents[] = {
848 + "clkxtal",
849 + "syspll1_d4",
850 + "syspll4_d2",
851 + "syspll3_d2"
852 +};
853 +
854 +static const char * const pmicspi_parents[] = {
855 + "clkxtal",
856 + "clk_null",
857 + "clk_null",
858 + "clk_null",
859 + "clk_null",
860 + "univpll2_d16"
861 +};
862 +
863 +static const char * const atb_parents[] = {
864 + "clkxtal",
865 + "syspll1_d2",
866 + "syspll_d5"
867 +};
868 +
869 +static const char * const audio_parents[] = {
870 + "clkxtal",
871 + "syspll3_d4",
872 + "syspll4_d4",
873 + "univpll1_d16"
874 +};
875 +
876 +static const char * const usb20_parents[] = {
877 + "clkxtal",
878 + "univpll3_d4",
879 + "syspll1_d8",
880 + "clkxtal"
881 +};
882 +
883 +static const char * const aud1_parents[] = {
884 + "clkxtal",
885 + "aud1pll_ck"
886 +};
887 +
888 +static const char * const aud2_parents[] = {
889 + "clkxtal",
890 + "aud2pll_ck"
891 +};
892 +
893 +static const char * const asm_l_parents[] = {
894 + "clkxtal",
895 + "syspll_d5",
896 + "univpll2_d2",
897 + "univpll2_d4"
898 +};
899 +
900 +static const char * const apll1_ck_parents[] = {
901 + "aud1_sel",
902 + "aud2_sel"
903 +};
904 +
905 +static const char * const peribus_ck_parents[] = {
906 + "syspll1_d8",
907 + "syspll1_d4"
908 +};
909 +
910 +static const struct mtk_gate_regs apmixed_cg_regs = {
911 + .set_ofs = 0x8,
912 + .clr_ofs = 0x8,
913 + .sta_ofs = 0x8,
914 +};
915 +
916 +static const struct mtk_gate_regs infra_cg_regs = {
917 + .set_ofs = 0x40,
918 + .clr_ofs = 0x44,
919 + .sta_ofs = 0x48,
920 +};
921 +
922 +static const struct mtk_gate_regs top0_cg_regs = {
923 + .set_ofs = 0x120,
924 + .clr_ofs = 0x120,
925 + .sta_ofs = 0x120,
926 +};
927 +
928 +static const struct mtk_gate_regs top1_cg_regs = {
929 + .set_ofs = 0x128,
930 + .clr_ofs = 0x128,
931 + .sta_ofs = 0x128,
932 +};
933 +
934 +static const struct mtk_gate_regs peri0_cg_regs = {
935 + .set_ofs = 0x8,
936 + .clr_ofs = 0x10,
937 + .sta_ofs = 0x18,
938 +};
939 +
940 +static const struct mtk_gate_regs peri1_cg_regs = {
941 + .set_ofs = 0xC,
942 + .clr_ofs = 0x14,
943 + .sta_ofs = 0x1C,
944 +};
945 +
946 +static const struct mtk_pll_data plls[] = {
947 + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
948 + PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
949 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
950 + HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
951 + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
952 + HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
953 + PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
954 + 0, 21, 0x0300, 1, 0, 0x0304, 0),
955 + PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
956 + 0, 21, 0x0314, 1, 0, 0x0318, 0),
957 + PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
958 + 0, 31, 0x0324, 1, 0, 0x0328, 0),
959 + PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
960 + 0, 31, 0x0334, 1, 0, 0x0338, 0),
961 + PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
962 + 0, 21, 0x0344, 1, 0, 0x0348, 0),
963 + PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
964 + 0, 21, 0x0358, 1, 0, 0x035C, 0),
965 +};
966 +
967 +static const struct mtk_gate apmixed_clks[] = {
968 + GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
969 +};
970 +
971 +static const struct mtk_gate infra_clks[] = {
972 + GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
973 + GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
974 + GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
975 + GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
976 + GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
977 + GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
978 +};
979 +
980 +static const struct mtk_fixed_clk top_fixed_clks[] = {
981 + FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
982 + 31250000),
983 + FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
984 + 31250000),
985 + FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
986 + 125000000),
987 + FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
988 + 125000000),
989 + FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
990 + 250000000),
991 + FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
992 + 250000000),
993 + FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
994 + 33333333),
995 + FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
996 + 50000000),
997 + FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
998 + 50000000),
999 + FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
1000 + 50000000),
1001 +};
1002 +
1003 +static const struct mtk_fixed_factor top_divs[] = {
1004 + FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
1005 + FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
1006 + FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
1007 + FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
1008 + FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
1009 + FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
1010 + FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
1011 + FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
1012 + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
1013 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
1014 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
1015 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
1016 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
1017 + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
1018 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
1019 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
1020 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
1021 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
1022 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
1023 + FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
1024 + FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
1025 + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
1026 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
1027 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
1028 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
1029 + FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
1030 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
1031 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
1032 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
1033 + FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
1034 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
1035 + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
1036 + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
1037 + FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
1038 + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
1039 + FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
1040 + FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
1041 + FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
1042 + FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
1043 + FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
1044 + FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
1045 + FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
1046 + FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
1047 + FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
1048 + FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
1049 + FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
1050 +};
1051 +
1052 +static const struct mtk_gate top_clks[] = {
1053 + /* TOP0 */
1054 + GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
1055 + GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
1056 + GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
1057 + 2),
1058 + GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
1059 + 3),
1060 + GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
1061 + 4),
1062 + GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
1063 + 5),
1064 +
1065 + /* TOP1 */
1066 + GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
1067 + GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
1068 +};
1069 +
1070 +static const struct mtk_clk_divider top_adj_divs[] = {
1071 + DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
1072 + 0x120, 24, 3),
1073 + DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
1074 + 0x120, 28, 3),
1075 + DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
1076 + 0x124, 0, 7),
1077 + DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
1078 + 0x124, 8, 7),
1079 + DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
1080 + 0x124, 16, 7),
1081 + DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
1082 + 0x124, 24, 7),
1083 + DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
1084 + 0x128, 8, 7),
1085 + DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
1086 + 0x128, 24, 7),
1087 +};
1088 +
1089 +static const struct mtk_gate peri_clks[] = {
1090 + /* PERI0 */
1091 + GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
1092 + GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
1093 + GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
1094 + GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
1095 + GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
1096 + GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
1097 + GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
1098 + GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
1099 + GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
1100 + GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
1101 + GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
1102 + GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
1103 + GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
1104 + GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
1105 + GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
1106 + GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
1107 + GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
1108 + GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
1109 + GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
1110 + GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
1111 + GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
1112 + GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
1113 + GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
1114 + GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
1115 + GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
1116 + GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
1117 + GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
1118 +
1119 + /* PERI1 */
1120 + GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
1121 + GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
1122 +};
1123 +
1124 +static struct mtk_composite infra_muxes[] __initdata = {
1125 + MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
1126 + 0x000, 2, 2),
1127 +};
1128 +
1129 +static struct mtk_composite top_muxes[] = {
1130 + /* CLK_CFG_0 */
1131 + MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
1132 + 0x040, 0, 3, 7),
1133 + MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
1134 + 0x040, 8, 1, 15),
1135 + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
1136 + 0x040, 16, 1, 23),
1137 + MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
1138 + 0x040, 24, 3, 31),
1139 +
1140 + /* CLK_CFG_1 */
1141 + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
1142 + 0x050, 0, 2, 7),
1143 + MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
1144 + 0x050, 8, 1, 15),
1145 + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
1146 + 0x050, 16, 4, 23),
1147 + MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
1148 + 0x050, 24, 3, 31),
1149 +
1150 + /* CLK_CFG_2 */
1151 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
1152 + 0x060, 0, 1, 7),
1153 + MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
1154 + 0x060, 8, 3, 15),
1155 + MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
1156 + 0x060, 16, 3, 23),
1157 + MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
1158 + 0x060, 24, 3, 31),
1159 +
1160 + /* CLK_CFG_3 */
1161 + MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
1162 + 0x070, 0, 3, 7),
1163 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
1164 + 0x070, 8, 3, 15),
1165 + MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
1166 + 0x070, 16, 2, 23),
1167 + MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
1168 + 0x070, 24, 2, 31),
1169 +
1170 + /* CLK_CFG_4 */
1171 + MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
1172 + 0x080, 0, 2, 7),
1173 + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
1174 + 0x080, 8, 2, 15),
1175 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
1176 + 0x080, 16, 3, 23),
1177 + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
1178 + 0x080, 24, 2, 31),
1179 +
1180 + /* CLK_CFG_5 */
1181 + MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
1182 + 0x090, 0, 2, 7),
1183 + MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
1184 + 0x090, 8, 3, 15),
1185 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
1186 + 0x090, 16, 2, 23),
1187 + MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
1188 + 0x090, 24, 2, 31),
1189 +
1190 + /* CLK_CFG_6 */
1191 + MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
1192 + 0x0A0, 0, 1, 7),
1193 + MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
1194 + 0x0A0, 8, 1, 15),
1195 + MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
1196 + 0x0A0, 16, 1, 23),
1197 + MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
1198 + 0x0A0, 24, 1, 31),
1199 +
1200 + /* CLK_CFG_7 */
1201 + MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
1202 + 0x0B0, 0, 2, 7),
1203 + MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
1204 + 0x0B0, 8, 2, 15),
1205 + MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
1206 + 0x0B0, 16, 2, 23),
1207 +
1208 + /* CLK_AUDDIV_0 */
1209 + MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
1210 + 0x120, 6, 1),
1211 + MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
1212 + 0x120, 7, 1),
1213 + MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
1214 + 0x120, 8, 1),
1215 + MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
1216 + 0x120, 9, 1),
1217 + MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
1218 + 0x120, 10, 1),
1219 + MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
1220 + 0x120, 11, 1),
1221 +};
1222 +
1223 +static struct mtk_composite peri_muxes[] = {
1224 + /* PERI_GLOBALCON_CKSEL */
1225 + MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
1226 +};
1227 +
1228 +static int mtk_topckgen_init(struct platform_device *pdev)
1229 +{
1230 + struct clk_onecell_data *clk_data;
1231 + void __iomem *base;
1232 + struct device_node *node = pdev->dev.of_node;
1233 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1234 +
1235 + base = devm_ioremap_resource(&pdev->dev, res);
1236 + if (IS_ERR(base))
1237 + return PTR_ERR(base);
1238 +
1239 + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1240 +
1241 + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1242 + clk_data);
1243 +
1244 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
1245 + clk_data);
1246 +
1247 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
1248 + base, &mt7622_clk_lock, clk_data);
1249 +
1250 + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
1251 + base, &mt7622_clk_lock, clk_data);
1252 +
1253 + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1254 + clk_data);
1255 +
1256 + clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
1257 + clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
1258 + clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
1259 +
1260 + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1261 +}
1262 +
1263 +static int __init mtk_infrasys_init(struct platform_device *pdev)
1264 +{
1265 + struct device_node *node = pdev->dev.of_node;
1266 + struct clk_onecell_data *clk_data;
1267 + int r;
1268 +
1269 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1270 +
1271 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1272 + clk_data);
1273 +
1274 + mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
1275 + clk_data);
1276 +
1277 + r = of_clk_add_provider(node, of_clk_src_onecell_get,
1278 + clk_data);
1279 + if (r)
1280 + return r;
1281 +
1282 + mtk_register_reset_controller(node, 1, 0x30);
1283 +
1284 + return 0;
1285 +}
1286 +
1287 +static int mtk_apmixedsys_init(struct platform_device *pdev)
1288 +{
1289 + struct clk_onecell_data *clk_data;
1290 + struct device_node *node = pdev->dev.of_node;
1291 +
1292 + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1293 + if (!clk_data)
1294 + return -ENOMEM;
1295 +
1296 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
1297 + clk_data);
1298 +
1299 + mtk_clk_register_gates(node, apmixed_clks,
1300 + ARRAY_SIZE(apmixed_clks), clk_data);
1301 +
1302 + clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
1303 + clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
1304 +
1305 + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1306 +}
1307 +
1308 +static int mtk_pericfg_init(struct platform_device *pdev)
1309 +{
1310 + struct clk_onecell_data *clk_data;
1311 + void __iomem *base;
1312 + int r;
1313 + struct device_node *node = pdev->dev.of_node;
1314 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1315 +
1316 + base = devm_ioremap_resource(&pdev->dev, res);
1317 + if (IS_ERR(base))
1318 + return PTR_ERR(base);
1319 +
1320 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1321 +
1322 + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1323 + clk_data);
1324 +
1325 + mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
1326 + &mt7622_clk_lock, clk_data);
1327 +
1328 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1329 + if (r)
1330 + return r;
1331 +
1332 + clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
1333 +
1334 + mtk_register_reset_controller(node, 2, 0x0);
1335 +
1336 + return 0;
1337 +}
1338 +
1339 +static const struct of_device_id of_match_clk_mt7622[] = {
1340 + {
1341 + .compatible = "mediatek,mt7622-apmixedsys",
1342 + .data = mtk_apmixedsys_init,
1343 + }, {
1344 + .compatible = "mediatek,mt7622-infracfg",
1345 + .data = mtk_infrasys_init,
1346 + }, {
1347 + .compatible = "mediatek,mt7622-topckgen",
1348 + .data = mtk_topckgen_init,
1349 + }, {
1350 + .compatible = "mediatek,mt7622-pericfg",
1351 + .data = mtk_pericfg_init,
1352 + }, {
1353 + /* sentinel */
1354 + }
1355 +};
1356 +
1357 +static int clk_mt7622_probe(struct platform_device *pdev)
1358 +{
1359 + int (*clk_init)(struct platform_device *);
1360 + int r;
1361 +
1362 + clk_init = of_device_get_match_data(&pdev->dev);
1363 + if (!clk_init)
1364 + return -EINVAL;
1365 +
1366 + r = clk_init(pdev);
1367 + if (r)
1368 + dev_err(&pdev->dev,
1369 + "could not register clock provider: %s: %d\n",
1370 + pdev->name, r);
1371 +
1372 + return r;
1373 +}
1374 +
1375 +static struct platform_driver clk_mt7622_drv = {
1376 + .probe = clk_mt7622_probe,
1377 + .driver = {
1378 + .name = "clk-mt7622",
1379 + .of_match_table = of_match_clk_mt7622,
1380 + },
1381 +};
1382 +
1383 +static int clk_mt7622_init(void)
1384 +{
1385 + return platform_driver_register(&clk_mt7622_drv);
1386 +}
1387 +
1388 +arch_initcall(clk_mt7622_init);
lynxis staging tree