1 From ea009d063f7a3d70831788046c7285a4af4ab82d Mon Sep 17 00:00:00 2001
2 From: Chen Zhong <chen.zhong@mediatek.com>
3 Date: Thu, 5 Oct 2017 11:50:25 +0800
4 Subject: [PATCH 149/224] clk: mediatek: add clocks dt-bindings required header
7 Add the required header for the entire clocks dt-bindings exported
8 from topckgen, apmixedsys, infracfg, pericfg, ethsys, pciesys, ssusbsys
9 and audsys which could be found on MT7622 SoC.
11 Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
12 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
15 include/dt-bindings/clock/mt7622-clk.h | 289 +++++++++++++++++++++++++++++++++
16 1 file changed, 289 insertions(+)
17 create mode 100644 include/dt-bindings/clock/mt7622-clk.h
19 diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
21 index 000000000000..3e514ed51d15
23 +++ b/include/dt-bindings/clock/mt7622-clk.h
26 + * Copyright (c) 2017 MediaTek Inc.
27 + * Author: Chen Zhong <chen.zhong@mediatek.com>
29 + * This program is free software; you can redistribute it and/or modify
30 + * it under the terms of the GNU General Public License version 2 as
31 + * published by the Free Software Foundation.
33 + * This program is distributed in the hope that it will be useful,
34 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 + * GNU General Public License for more details.
39 +#ifndef _DT_BINDINGS_CLK_MT7622_H
40 +#define _DT_BINDINGS_CLK_MT7622_H
44 +#define CLK_TOP_TO_U2_PHY 0
45 +#define CLK_TOP_TO_U2_PHY_1P 1
46 +#define CLK_TOP_PCIE0_PIPE_EN 2
47 +#define CLK_TOP_PCIE1_PIPE_EN 3
48 +#define CLK_TOP_SSUSB_TX250M 4
49 +#define CLK_TOP_SSUSB_EQ_RX250M 5
50 +#define CLK_TOP_SSUSB_CDR_REF 6
51 +#define CLK_TOP_SSUSB_CDR_FB 7
52 +#define CLK_TOP_SATA_ASIC 8
53 +#define CLK_TOP_SATA_RBC 9
54 +#define CLK_TOP_TO_USB3_SYS 10
55 +#define CLK_TOP_P1_1MHZ 11
56 +#define CLK_TOP_4MHZ 12
57 +#define CLK_TOP_P0_1MHZ 13
58 +#define CLK_TOP_TXCLK_SRC_PRE 14
59 +#define CLK_TOP_RTC 15
60 +#define CLK_TOP_MEMPLL 16
61 +#define CLK_TOP_DMPLL 17
62 +#define CLK_TOP_SYSPLL_D2 18
63 +#define CLK_TOP_SYSPLL1_D2 19
64 +#define CLK_TOP_SYSPLL1_D4 20
65 +#define CLK_TOP_SYSPLL1_D8 21
66 +#define CLK_TOP_SYSPLL2_D4 22
67 +#define CLK_TOP_SYSPLL2_D8 23
68 +#define CLK_TOP_SYSPLL_D5 24
69 +#define CLK_TOP_SYSPLL3_D2 25
70 +#define CLK_TOP_SYSPLL3_D4 26
71 +#define CLK_TOP_SYSPLL4_D2 27
72 +#define CLK_TOP_SYSPLL4_D4 28
73 +#define CLK_TOP_SYSPLL4_D16 29
74 +#define CLK_TOP_UNIVPLL 30
75 +#define CLK_TOP_UNIVPLL_D2 31
76 +#define CLK_TOP_UNIVPLL1_D2 32
77 +#define CLK_TOP_UNIVPLL1_D4 33
78 +#define CLK_TOP_UNIVPLL1_D8 34
79 +#define CLK_TOP_UNIVPLL1_D16 35
80 +#define CLK_TOP_UNIVPLL2_D2 36
81 +#define CLK_TOP_UNIVPLL2_D4 37
82 +#define CLK_TOP_UNIVPLL2_D8 38
83 +#define CLK_TOP_UNIVPLL2_D16 39
84 +#define CLK_TOP_UNIVPLL_D5 40
85 +#define CLK_TOP_UNIVPLL3_D2 41
86 +#define CLK_TOP_UNIVPLL3_D4 42
87 +#define CLK_TOP_UNIVPLL3_D16 43
88 +#define CLK_TOP_UNIVPLL_D7 44
89 +#define CLK_TOP_UNIVPLL_D80_D4 45
90 +#define CLK_TOP_UNIV48M 46
91 +#define CLK_TOP_SGMIIPLL 47
92 +#define CLK_TOP_SGMIIPLL_D2 48
93 +#define CLK_TOP_AUD1PLL 49
94 +#define CLK_TOP_AUD2PLL 50
95 +#define CLK_TOP_AUD_I2S2_MCK 51
96 +#define CLK_TOP_TO_USB3_REF 52
97 +#define CLK_TOP_PCIE1_MAC_EN 53
98 +#define CLK_TOP_PCIE0_MAC_EN 54
99 +#define CLK_TOP_ETH_500M 55
100 +#define CLK_TOP_AXI_SEL 56
101 +#define CLK_TOP_MEM_SEL 57
102 +#define CLK_TOP_DDRPHYCFG_SEL 58
103 +#define CLK_TOP_ETH_SEL 59
104 +#define CLK_TOP_PWM_SEL 60
105 +#define CLK_TOP_F10M_REF_SEL 61
106 +#define CLK_TOP_NFI_INFRA_SEL 62
107 +#define CLK_TOP_FLASH_SEL 63
108 +#define CLK_TOP_UART_SEL 64
109 +#define CLK_TOP_SPI0_SEL 65
110 +#define CLK_TOP_SPI1_SEL 66
111 +#define CLK_TOP_MSDC50_0_SEL 67
112 +#define CLK_TOP_MSDC30_0_SEL 68
113 +#define CLK_TOP_MSDC30_1_SEL 69
114 +#define CLK_TOP_A1SYS_HP_SEL 70
115 +#define CLK_TOP_A2SYS_HP_SEL 71
116 +#define CLK_TOP_INTDIR_SEL 72
117 +#define CLK_TOP_AUD_INTBUS_SEL 73
118 +#define CLK_TOP_PMICSPI_SEL 74
119 +#define CLK_TOP_SCP_SEL 75
120 +#define CLK_TOP_ATB_SEL 76
121 +#define CLK_TOP_HIF_SEL 77
122 +#define CLK_TOP_AUDIO_SEL 78
123 +#define CLK_TOP_U2_SEL 79
124 +#define CLK_TOP_AUD1_SEL 80
125 +#define CLK_TOP_AUD2_SEL 81
126 +#define CLK_TOP_IRRX_SEL 82
127 +#define CLK_TOP_IRTX_SEL 83
128 +#define CLK_TOP_ASM_L_SEL 84
129 +#define CLK_TOP_ASM_M_SEL 85
130 +#define CLK_TOP_ASM_H_SEL 86
131 +#define CLK_TOP_APLL1_SEL 87
132 +#define CLK_TOP_APLL2_SEL 88
133 +#define CLK_TOP_I2S0_MCK_SEL 89
134 +#define CLK_TOP_I2S1_MCK_SEL 90
135 +#define CLK_TOP_I2S2_MCK_SEL 91
136 +#define CLK_TOP_I2S3_MCK_SEL 92
137 +#define CLK_TOP_APLL1_DIV 93
138 +#define CLK_TOP_APLL2_DIV 94
139 +#define CLK_TOP_I2S0_MCK_DIV 95
140 +#define CLK_TOP_I2S1_MCK_DIV 96
141 +#define CLK_TOP_I2S2_MCK_DIV 97
142 +#define CLK_TOP_I2S3_MCK_DIV 98
143 +#define CLK_TOP_A1SYS_HP_DIV 99
144 +#define CLK_TOP_A2SYS_HP_DIV 100
145 +#define CLK_TOP_APLL1_DIV_PD 101
146 +#define CLK_TOP_APLL2_DIV_PD 102
147 +#define CLK_TOP_I2S0_MCK_DIV_PD 103
148 +#define CLK_TOP_I2S1_MCK_DIV_PD 104
149 +#define CLK_TOP_I2S2_MCK_DIV_PD 105
150 +#define CLK_TOP_I2S3_MCK_DIV_PD 106
151 +#define CLK_TOP_A1SYS_HP_DIV_PD 107
152 +#define CLK_TOP_A2SYS_HP_DIV_PD 108
153 +#define CLK_TOP_NR_CLK 109
157 +#define CLK_INFRA_MUX1_SEL 0
158 +#define CLK_INFRA_DBGCLK_PD 1
159 +#define CLK_INFRA_AUDIO_PD 2
160 +#define CLK_INFRA_IRRX_PD 3
161 +#define CLK_INFRA_APXGPT_PD 4
162 +#define CLK_INFRA_PMIC_PD 5
163 +#define CLK_INFRA_TRNG 6
164 +#define CLK_INFRA_NR_CLK 7
168 +#define CLK_PERIBUS_SEL 0
169 +#define CLK_PERI_THERM_PD 1
170 +#define CLK_PERI_PWM1_PD 2
171 +#define CLK_PERI_PWM2_PD 3
172 +#define CLK_PERI_PWM3_PD 4
173 +#define CLK_PERI_PWM4_PD 5
174 +#define CLK_PERI_PWM5_PD 6
175 +#define CLK_PERI_PWM6_PD 7
176 +#define CLK_PERI_PWM7_PD 8
177 +#define CLK_PERI_PWM_PD 9
178 +#define CLK_PERI_AP_DMA_PD 10
179 +#define CLK_PERI_MSDC30_0_PD 11
180 +#define CLK_PERI_MSDC30_1_PD 12
181 +#define CLK_PERI_UART0_PD 13
182 +#define CLK_PERI_UART1_PD 14
183 +#define CLK_PERI_UART2_PD 15
184 +#define CLK_PERI_UART3_PD 16
185 +#define CLK_PERI_UART4_PD 17
186 +#define CLK_PERI_BTIF_PD 18
187 +#define CLK_PERI_I2C0_PD 19
188 +#define CLK_PERI_I2C1_PD 20
189 +#define CLK_PERI_I2C2_PD 21
190 +#define CLK_PERI_SPI1_PD 22
191 +#define CLK_PERI_AUXADC_PD 23
192 +#define CLK_PERI_SPI0_PD 24
193 +#define CLK_PERI_SNFI_PD 25
194 +#define CLK_PERI_NFI_PD 26
195 +#define CLK_PERI_NFIECC_PD 27
196 +#define CLK_PERI_FLASH_PD 28
197 +#define CLK_PERI_IRTX_PD 29
198 +#define CLK_PERI_NR_CLK 30
202 +#define CLK_APMIXED_ARMPLL 0
203 +#define CLK_APMIXED_MAINPLL 1
204 +#define CLK_APMIXED_UNIV2PLL 2
205 +#define CLK_APMIXED_ETH1PLL 3
206 +#define CLK_APMIXED_ETH2PLL 4
207 +#define CLK_APMIXED_AUD1PLL 5
208 +#define CLK_APMIXED_AUD2PLL 6
209 +#define CLK_APMIXED_TRGPLL 7
210 +#define CLK_APMIXED_SGMIPLL 8
211 +#define CLK_APMIXED_MAIN_CORE_EN 9
212 +#define CLK_APMIXED_NR_CLK 10
216 +#define CLK_AUDIO_AFE 0
217 +#define CLK_AUDIO_HDMI 1
218 +#define CLK_AUDIO_SPDF 2
219 +#define CLK_AUDIO_APLL 3
220 +#define CLK_AUDIO_I2SIN1 4
221 +#define CLK_AUDIO_I2SIN2 5
222 +#define CLK_AUDIO_I2SIN3 6
223 +#define CLK_AUDIO_I2SIN4 7
224 +#define CLK_AUDIO_I2SO1 8
225 +#define CLK_AUDIO_I2SO2 9
226 +#define CLK_AUDIO_I2SO3 10
227 +#define CLK_AUDIO_I2SO4 11
228 +#define CLK_AUDIO_ASRCI1 12
229 +#define CLK_AUDIO_ASRCI2 13
230 +#define CLK_AUDIO_ASRCO1 14
231 +#define CLK_AUDIO_ASRCO2 15
232 +#define CLK_AUDIO_INTDIR 16
233 +#define CLK_AUDIO_A1SYS 17
234 +#define CLK_AUDIO_A2SYS 18
235 +#define CLK_AUDIO_UL1 19
236 +#define CLK_AUDIO_UL2 20
237 +#define CLK_AUDIO_UL3 21
238 +#define CLK_AUDIO_UL4 22
239 +#define CLK_AUDIO_UL5 23
240 +#define CLK_AUDIO_UL6 24
241 +#define CLK_AUDIO_DL1 25
242 +#define CLK_AUDIO_DL2 26
243 +#define CLK_AUDIO_DL3 27
244 +#define CLK_AUDIO_DL4 28
245 +#define CLK_AUDIO_DL5 29
246 +#define CLK_AUDIO_DL6 30
247 +#define CLK_AUDIO_DLMCH 31
248 +#define CLK_AUDIO_ARB1 32
249 +#define CLK_AUDIO_AWB 33
250 +#define CLK_AUDIO_AWB2 34
251 +#define CLK_AUDIO_DAI 35
252 +#define CLK_AUDIO_MOD 36
253 +#define CLK_AUDIO_ASRCI3 37
254 +#define CLK_AUDIO_ASRCI4 38
255 +#define CLK_AUDIO_ASRCO3 39
256 +#define CLK_AUDIO_ASRCO4 40
257 +#define CLK_AUDIO_MEM_ASRC1 41
258 +#define CLK_AUDIO_MEM_ASRC2 42
259 +#define CLK_AUDIO_MEM_ASRC3 43
260 +#define CLK_AUDIO_MEM_ASRC4 44
261 +#define CLK_AUDIO_MEM_ASRC5 45
262 +#define CLK_AUDIO_NR_CLK 46
266 +#define CLK_SSUSB_U2_PHY_1P_EN 0
267 +#define CLK_SSUSB_U2_PHY_EN 1
268 +#define CLK_SSUSB_REF_EN 2
269 +#define CLK_SSUSB_SYS_EN 3
270 +#define CLK_SSUSB_MCU_EN 4
271 +#define CLK_SSUSB_DMA_EN 5
272 +#define CLK_SSUSB_NR_CLK 6
276 +#define CLK_PCIE_P1_AUX_EN 0
277 +#define CLK_PCIE_P1_OBFF_EN 1
278 +#define CLK_PCIE_P1_AHB_EN 2
279 +#define CLK_PCIE_P1_AXI_EN 3
280 +#define CLK_PCIE_P1_MAC_EN 4
281 +#define CLK_PCIE_P1_PIPE_EN 5
282 +#define CLK_PCIE_P0_AUX_EN 6
283 +#define CLK_PCIE_P0_OBFF_EN 7
284 +#define CLK_PCIE_P0_AHB_EN 8
285 +#define CLK_PCIE_P0_AXI_EN 9
286 +#define CLK_PCIE_P0_MAC_EN 10
287 +#define CLK_PCIE_P0_PIPE_EN 11
288 +#define CLK_SATA_AHB_EN 12
289 +#define CLK_SATA_AXI_EN 13
290 +#define CLK_SATA_ASIC_EN 14
291 +#define CLK_SATA_RBC_EN 15
292 +#define CLK_SATA_PM_EN 16
293 +#define CLK_PCIE_NR_CLK 17
297 +#define CLK_ETH_HSDMA_EN 0
298 +#define CLK_ETH_ESW_EN 1
299 +#define CLK_ETH_GP2_EN 2
300 +#define CLK_ETH_GP1_EN 3
301 +#define CLK_ETH_GP0_EN 4
302 +#define CLK_ETH_NR_CLK 5
306 +#define CLK_SGMII_TX250M_EN 0
307 +#define CLK_SGMII_RX250M_EN 1
308 +#define CLK_SGMII_CDR_REF 2
309 +#define CLK_SGMII_CDR_FB 3
310 +#define CLK_SGMII_NR_CLK 4
312 +#endif /* _DT_BINDINGS_CLK_MT7622_H */
projects / openwrt / staging / lynxis.git / blob