mediatek: add v4.19 support
[openwrt/staging/lynxis.git] / target / linux / mediatek / files-4.19 / drivers / net / phy / mtk / mt753x / mt753x_mdio.c
1 /*
2 * Driver for MediaTek MT753x gigabit switch
3 *
4 * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
5 *
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/reset.h>
17 #include <linux/hrtimer.h>
18 #include <linux/mii.h>
19 #include <linux/of_mdio.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_net.h>
23 #include <linux/of_irq.h>
24 #include <linux/phy.h>
25
26 #include "mt753x.h"
27 #include "mt753x_swconfig.h"
28 #include "mt753x_regs.h"
29 #include "mt753x_nl.h"
30 #include "mt7530.h"
31 #include "mt7531.h"
32
33 static u32 mt753x_id;
34 struct list_head mt753x_devs;
35 static DEFINE_MUTEX(mt753x_devs_lock);
36
37 static struct mt753x_sw_id *mt753x_sw_ids[] = {
38 &mt7530_id,
39 &mt7531_id,
40 };
41
42 u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg)
43 {
44 u32 high, low;
45
46 mutex_lock(&gsw->host_bus->mdio_lock);
47
48 gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
49 (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);
50
51 low = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr,
52 (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S);
53
54 high = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, 0x10);
55
56 mutex_unlock(&gsw->host_bus->mdio_lock);
57
58 return (high << 16) | (low & 0xffff);
59 }
60
61 void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val)
62 {
63 mutex_lock(&gsw->host_bus->mdio_lock);
64
65 gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
66 (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);
67
68 gsw->host_bus->write(gsw->host_bus, gsw->smi_addr,
69 (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S, val & 0xffff);
70
71 gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x10, val >> 16);
72
73 mutex_unlock(&gsw->host_bus->mdio_lock);
74 }
75
76 /* Indirect MDIO clause 22/45 access */
77 static int mt753x_mii_rw(struct gsw_mt753x *gsw, int phy, int reg, u16 data,
78 u32 cmd, u32 st)
79 {
80 ktime_t timeout;
81 u32 val, timeout_us;
82 int ret = 0;
83
84 timeout_us = 100000;
85 timeout = ktime_add_us(ktime_get(), timeout_us);
86 while (1) {
87 val = mt753x_reg_read(gsw, PHY_IAC);
88
89 if ((val & PHY_ACS_ST) == 0)
90 break;
91
92 if (ktime_compare(ktime_get(), timeout) > 0)
93 return -ETIMEDOUT;
94 }
95
96 val = (st << MDIO_ST_S) |
97 ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
98 ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
99 ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
100
101 if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
102 val |= data & MDIO_RW_DATA_M;
103
104 mt753x_reg_write(gsw, PHY_IAC, val | PHY_ACS_ST);
105
106 timeout_us = 100000;
107 timeout = ktime_add_us(ktime_get(), timeout_us);
108 while (1) {
109 val = mt753x_reg_read(gsw, PHY_IAC);
110
111 if ((val & PHY_ACS_ST) == 0)
112 break;
113
114 if (ktime_compare(ktime_get(), timeout) > 0)
115 return -ETIMEDOUT;
116 }
117
118 if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
119 val = mt753x_reg_read(gsw, PHY_IAC);
120 ret = val & MDIO_RW_DATA_M;
121 }
122
123 return ret;
124 }
125
126 int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg)
127 {
128 int val;
129
130 if (phy < MT753X_NUM_PHYS)
131 phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
132
133 mutex_lock(&gsw->mii_lock);
134 val = mt753x_mii_rw(gsw, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
135 mutex_unlock(&gsw->mii_lock);
136
137 return val;
138 }
139
140 void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val)
141 {
142 if (phy < MT753X_NUM_PHYS)
143 phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
144
145 mutex_lock(&gsw->mii_lock);
146 mt753x_mii_rw(gsw, phy, reg, val, MDIO_CMD_WRITE, MDIO_ST_C22);
147 mutex_unlock(&gsw->mii_lock);
148 }
149
150 int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)
151 {
152 int val;
153
154 if (addr < MT753X_NUM_PHYS)
155 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
156
157 mutex_lock(&gsw->mii_lock);
158 mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
159 val = mt753x_mii_rw(gsw, addr, devad, 0, MDIO_CMD_READ_C45,
160 MDIO_ST_C45);
161 mutex_unlock(&gsw->mii_lock);
162
163 return val;
164 }
165
166 void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
167 u16 val)
168 {
169 if (addr < MT753X_NUM_PHYS)
170 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
171
172 mutex_lock(&gsw->mii_lock);
173 mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
174 mt753x_mii_rw(gsw, addr, devad, val, MDIO_CMD_WRITE, MDIO_ST_C45);
175 mutex_unlock(&gsw->mii_lock);
176 }
177
178 int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)
179 {
180 u16 val;
181
182 if (addr < MT753X_NUM_PHYS)
183 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
184
185 mutex_lock(&gsw->mii_lock);
186
187 mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
188 (MMD_ADDR << MMD_CMD_S) |
189 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
190 MDIO_CMD_WRITE, MDIO_ST_C22);
191
192 mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,
193 MDIO_CMD_WRITE, MDIO_ST_C22);
194
195 mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
196 (MMD_DATA << MMD_CMD_S) |
197 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
198 MDIO_CMD_WRITE, MDIO_ST_C22);
199
200 val = mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, 0,
201 MDIO_CMD_READ, MDIO_ST_C22);
202
203 mutex_unlock(&gsw->mii_lock);
204
205 return val;
206 }
207
208 void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
209 u16 val)
210 {
211 if (addr < MT753X_NUM_PHYS)
212 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
213
214 mutex_lock(&gsw->mii_lock);
215
216 mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
217 (MMD_ADDR << MMD_CMD_S) |
218 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
219 MDIO_CMD_WRITE, MDIO_ST_C22);
220
221 mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,
222 MDIO_CMD_WRITE, MDIO_ST_C22);
223
224 mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
225 (MMD_DATA << MMD_CMD_S) |
226 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
227 MDIO_CMD_WRITE, MDIO_ST_C22);
228
229 mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, val,
230 MDIO_CMD_WRITE, MDIO_ST_C22);
231
232 mutex_unlock(&gsw->mii_lock);
233 }
234
235 static void mt753x_load_port_cfg(struct gsw_mt753x *gsw)
236 {
237 struct device_node *port_np;
238 struct device_node *fixed_link_node;
239 struct mt753x_port_cfg *port_cfg;
240 u32 port;
241
242 for_each_child_of_node(gsw->dev->of_node, port_np) {
243 if (!of_device_is_compatible(port_np, "mediatek,mt753x-port"))
244 continue;
245
246 if (!of_device_is_available(port_np))
247 continue;
248
249 if (of_property_read_u32(port_np, "reg", &port))
250 continue;
251
252 switch (port) {
253 case 5:
254 port_cfg = &gsw->port5_cfg;
255 break;
256 case 6:
257 port_cfg = &gsw->port6_cfg;
258 break;
259 default:
260 continue;
261 }
262
263 if (port_cfg->enabled) {
264 dev_info(gsw->dev, "duplicated node for port%d\n",
265 port_cfg->phy_mode);
266 continue;
267 }
268
269 port_cfg->np = port_np;
270
271 port_cfg->phy_mode = of_get_phy_mode(port_np);
272 if (port_cfg->phy_mode < 0) {
273 dev_info(gsw->dev, "incorrect phy-mode %d\n", port);
274 continue;
275 }
276
277 fixed_link_node = of_get_child_by_name(port_np, "fixed-link");
278 if (fixed_link_node) {
279 u32 speed;
280
281 port_cfg->force_link = 1;
282 port_cfg->duplex = of_property_read_bool(
283 fixed_link_node,
284 "full-duplex");
285
286 if (of_property_read_u32(fixed_link_node, "speed",
287 &speed)) {
288 speed = 0;
289 continue;
290 }
291
292 of_node_put(fixed_link_node);
293
294 switch (speed) {
295 case 10:
296 port_cfg->speed = MAC_SPD_10;
297 break;
298 case 100:
299 port_cfg->speed = MAC_SPD_100;
300 break;
301 case 1000:
302 port_cfg->speed = MAC_SPD_1000;
303 break;
304 case 2500:
305 port_cfg->speed = MAC_SPD_2500;
306 break;
307 default:
308 dev_info(gsw->dev, "incorrect speed %d\n",
309 speed);
310 continue;
311 }
312 }
313
314 port_cfg->enabled = 1;
315 }
316 }
317
318 static void mt753x_add_gsw(struct gsw_mt753x *gsw)
319 {
320 mutex_lock(&mt753x_devs_lock);
321 gsw->id = mt753x_id++;
322 INIT_LIST_HEAD(&gsw->list);
323 list_add_tail(&gsw->list, &mt753x_devs);
324 mutex_unlock(&mt753x_devs_lock);
325 }
326
327 static void mt753x_remove_gsw(struct gsw_mt753x *gsw)
328 {
329 mutex_lock(&mt753x_devs_lock);
330 list_del(&gsw->list);
331 mutex_unlock(&mt753x_devs_lock);
332 }
333
334 struct gsw_mt753x *mt753x_get_gsw(u32 id)
335 {
336 struct gsw_mt753x *dev;
337
338 mutex_lock(&mt753x_devs_lock);
339
340 list_for_each_entry(dev, &mt753x_devs, list) {
341 if (dev->id == id)
342 return dev;
343 }
344
345 mutex_unlock(&mt753x_devs_lock);
346
347 return NULL;
348 }
349
350 struct gsw_mt753x *mt753x_get_first_gsw(void)
351 {
352 struct gsw_mt753x *dev;
353
354 mutex_lock(&mt753x_devs_lock);
355
356 list_for_each_entry(dev, &mt753x_devs, list)
357 return dev;
358
359 mutex_unlock(&mt753x_devs_lock);
360
361 return NULL;
362 }
363
364 void mt753x_put_gsw(void)
365 {
366 mutex_unlock(&mt753x_devs_lock);
367 }
368
369 void mt753x_lock_gsw(void)
370 {
371 mutex_lock(&mt753x_devs_lock);
372 }
373
374 static int mt753x_hw_reset(struct gsw_mt753x *gsw)
375 {
376 struct device_node *np = gsw->dev->of_node;
377 struct reset_control *rstc;
378 int mcm;
379 int ret = -EINVAL;
380
381 mcm = of_property_read_bool(np, "mediatek,mcm");
382 if (mcm) {
383 rstc = devm_reset_control_get(gsw->dev, "mcm");
384 ret = IS_ERR(rstc);
385 if (IS_ERR(rstc)) {
386 dev_err(gsw->dev, "Missing reset ctrl of switch\n");
387 return ret;
388 }
389
390 reset_control_assert(rstc);
391 msleep(30);
392 reset_control_deassert(rstc);
393
394 gsw->reset_pin = -1;
395 return 0;
396 }
397
398 gsw->reset_pin = of_get_named_gpio(np, "reset-gpios", 0);
399 if (gsw->reset_pin < 0) {
400 dev_err(gsw->dev, "Missing reset pin of switch\n");
401 return ret;
402 }
403
404 ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mt753x-reset");
405 if (ret) {
406 dev_info(gsw->dev, "Failed to request gpio %d\n",
407 gsw->reset_pin);
408 return ret;
409 }
410
411 gpio_direction_output(gsw->reset_pin, 0);
412 msleep(30);
413 gpio_set_value(gsw->reset_pin, 1);
414 msleep(500);
415
416 return 0;
417 }
418
419 static int mt753x_mdio_read(struct mii_bus *bus, int addr, int reg)
420 {
421 struct gsw_mt753x *gsw = bus->priv;
422
423 return gsw->mii_read(gsw, addr, reg);
424 }
425
426 static int mt753x_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val)
427 {
428 struct gsw_mt753x *gsw = bus->priv;
429
430 gsw->mii_write(gsw, addr, reg, val);
431
432 return 0;
433 }
434
435 static const struct net_device_ops mt753x_dummy_netdev_ops = {
436 };
437
438 static void mt753x_phy_link_handler(struct net_device *dev)
439 {
440 struct mt753x_phy *phy = container_of(dev, struct mt753x_phy, netdev);
441 struct phy_device *phydev = phy->phydev;
442 struct gsw_mt753x *gsw = phy->gsw;
443 u32 port = phy - gsw->phys;
444
445 if (phydev->link) {
446 dev_info(gsw->dev,
447 "Port %d Link is Up - %s/%s - flow control %s\n",
448 port, phy_speed_to_str(phydev->speed),
449 (phydev->duplex == DUPLEX_FULL) ? "Full" : "Half",
450 phydev->pause ? "rx/tx" : "off");
451 } else {
452 dev_info(gsw->dev, "Port %d Link is Down\n", port);
453 }
454 }
455
456 static void mt753x_connect_internal_phys(struct gsw_mt753x *gsw,
457 struct device_node *mii_np)
458 {
459 struct device_node *phy_np;
460 struct mt753x_phy *phy;
461 int phy_mode;
462 u32 phyad;
463
464 if (!mii_np)
465 return;
466
467 for_each_child_of_node(mii_np, phy_np) {
468 if (of_property_read_u32(phy_np, "reg", &phyad))
469 continue;
470
471 if (phyad >= MT753X_NUM_PHYS)
472 continue;
473
474 phy_mode = of_get_phy_mode(phy_np);
475 if (phy_mode < 0) {
476 dev_info(gsw->dev, "incorrect phy-mode %d for PHY %d\n",
477 phy_mode, phyad);
478 continue;
479 }
480
481 phy = &gsw->phys[phyad];
482 phy->gsw = gsw;
483
484 init_dummy_netdev(&phy->netdev);
485 phy->netdev.netdev_ops = &mt753x_dummy_netdev_ops;
486
487 phy->phydev = of_phy_connect(&phy->netdev, phy_np,
488 mt753x_phy_link_handler, 0, phy_mode);
489 if (!phy->phydev) {
490 dev_info(gsw->dev, "could not connect to PHY %d\n",
491 phyad);
492 continue;
493 }
494
495 phy_start(phy->phydev);
496 }
497 }
498
499 static void mt753x_disconnect_internal_phys(struct gsw_mt753x *gsw)
500 {
501 int i;
502
503 for (i = 0; i < ARRAY_SIZE(gsw->phys); i++) {
504 if (gsw->phys[i].phydev) {
505 phy_stop(gsw->phys[i].phydev);
506 phy_disconnect(gsw->phys[i].phydev);
507 gsw->phys[i].phydev = NULL;
508 }
509 }
510 }
511
512 static int mt753x_mdio_register(struct gsw_mt753x *gsw)
513 {
514 struct device_node *mii_np;
515 int i, ret;
516
517 mii_np = of_get_child_by_name(gsw->dev->of_node, "mdio-bus");
518 if (mii_np && !of_device_is_available(mii_np)) {
519 ret = -ENODEV;
520 goto err_put_node;
521 }
522
523 gsw->gphy_bus = devm_mdiobus_alloc(gsw->dev);
524 if (!gsw->gphy_bus) {
525 ret = -ENOMEM;
526 goto err_put_node;
527 }
528
529 gsw->gphy_bus->name = "mt753x_mdio";
530 gsw->gphy_bus->read = mt753x_mdio_read;
531 gsw->gphy_bus->write = mt753x_mdio_write;
532 gsw->gphy_bus->priv = gsw;
533 gsw->gphy_bus->parent = gsw->dev;
534 gsw->gphy_bus->phy_mask = BIT(MT753X_NUM_PHYS) - 1;
535
536 for (i = 0; i < PHY_MAX_ADDR; i++)
537 gsw->gphy_bus->irq[i] = PHY_POLL;
538
539 if (mii_np)
540 snprintf(gsw->gphy_bus->id, MII_BUS_ID_SIZE, "%s@%s",
541 mii_np->name, gsw->dev->of_node->name);
542 else
543 snprintf(gsw->gphy_bus->id, MII_BUS_ID_SIZE, "mdio@%s",
544 gsw->dev->of_node->name);
545
546 ret = of_mdiobus_register(gsw->gphy_bus, mii_np);
547
548 if (ret) {
549 devm_mdiobus_free(gsw->dev, gsw->gphy_bus);
550 gsw->gphy_bus = NULL;
551 } else {
552 if (gsw->phy_status_poll)
553 mt753x_connect_internal_phys(gsw, mii_np);
554 }
555
556 err_put_node:
557 if (mii_np)
558 of_node_put(mii_np);
559
560 return ret;
561 }
562
563 static irqreturn_t mt753x_irq_handler(int irq, void *dev)
564 {
565 struct gsw_mt753x *gsw = dev;
566
567 disable_irq_nosync(gsw->irq);
568
569 schedule_work(&gsw->irq_worker);
570
571 return IRQ_HANDLED;
572 }
573
574 static int mt753x_probe(struct platform_device *pdev)
575 {
576 struct gsw_mt753x *gsw;
577 struct mt753x_sw_id *sw;
578 struct device_node *np = pdev->dev.of_node;
579 struct device_node *mdio;
580 struct mii_bus *mdio_bus;
581 int ret = -EINVAL;
582 struct chip_rev rev;
583 int i;
584
585 mdio = of_parse_phandle(np, "mediatek,mdio", 0);
586 if (!mdio)
587 return -EINVAL;
588
589 mdio_bus = of_mdio_find_bus(mdio);
590 if (!mdio_bus)
591 return -EPROBE_DEFER;
592
593 gsw = devm_kzalloc(&pdev->dev, sizeof(struct gsw_mt753x), GFP_KERNEL);
594 if (!gsw)
595 return -ENOMEM;
596
597 gsw->host_bus = mdio_bus;
598 gsw->dev = &pdev->dev;
599 mutex_init(&gsw->mii_lock);
600
601 /* Switch hard reset */
602 mt753x_hw_reset(gsw);
603
604 /* Fetch the SMI address dirst */
605 if (of_property_read_u32(np, "mediatek,smi-addr", &gsw->smi_addr))
606 gsw->smi_addr = MT753X_DFL_SMI_ADDR;
607
608 /* Load MAC port configurations */
609 mt753x_load_port_cfg(gsw);
610
611 /* Check for valid switch and then initialize */
612 for (i = 0; i < ARRAY_SIZE(mt753x_sw_ids); i++) {
613 if (!mt753x_sw_ids[i]->detect(gsw, &rev)) {
614 sw = mt753x_sw_ids[i];
615
616 gsw->name = rev.name;
617 gsw->model = sw->model;
618
619 dev_info(gsw->dev, "Switch is MediaTek %s rev %d",
620 gsw->name, rev.rev);
621
622 /* Initialize the switch */
623 ret = sw->init(gsw);
624 if (ret)
625 goto fail;
626
627 break;
628 }
629 }
630
631 if (i >= ARRAY_SIZE(mt753x_sw_ids)) {
632 dev_err(gsw->dev, "No mt753x switch found\n");
633 goto fail;
634 }
635
636 gsw->irq = platform_get_irq(pdev, 0);
637 if (gsw->irq >= 0) {
638 ret = devm_request_irq(gsw->dev, gsw->irq, mt753x_irq_handler,
639 0, dev_name(gsw->dev), gsw);
640 if (ret) {
641 dev_err(gsw->dev, "Failed to request irq %d\n",
642 gsw->irq);
643 goto fail;
644 }
645
646 INIT_WORK(&gsw->irq_worker, mt753x_irq_worker);
647 }
648
649 platform_set_drvdata(pdev, gsw);
650
651 gsw->phy_status_poll = of_property_read_bool(gsw->dev->of_node,
652 "mediatek,phy-poll");
653
654 mt753x_add_gsw(gsw);
655
656 mt753x_mdio_register(gsw);
657
658 #ifdef CONFIG_SWCONFIG
659 mt753x_swconfig_init(gsw);
660 #endif
661
662 if (sw->post_init)
663 sw->post_init(gsw);
664
665 if (gsw->irq >= 0)
666 mt753x_irq_enable(gsw);
667
668 return 0;
669
670 fail:
671 devm_kfree(&pdev->dev, gsw);
672
673 return ret;
674 }
675
676 static int mt753x_remove(struct platform_device *pdev)
677 {
678 struct gsw_mt753x *gsw = platform_get_drvdata(pdev);
679
680 if (gsw->irq >= 0)
681 cancel_work_sync(&gsw->irq_worker);
682
683 if (gsw->reset_pin >= 0)
684 devm_gpio_free(&pdev->dev, gsw->reset_pin);
685
686 #ifdef CONFIG_SWCONFIG
687 mt753x_swconfig_destroy(gsw);
688 #endif
689
690 mt753x_disconnect_internal_phys(gsw);
691
692 mdiobus_unregister(gsw->gphy_bus);
693
694 mt753x_remove_gsw(gsw);
695
696 platform_set_drvdata(pdev, NULL);
697
698 return 0;
699 }
700
701 static const struct of_device_id mt753x_ids[] = {
702 { .compatible = "mediatek,mt753x" },
703 { },
704 };
705
706 MODULE_DEVICE_TABLE(of, mt753x_ids);
707
708 static struct platform_driver mt753x_driver = {
709 .probe = mt753x_probe,
710 .remove = mt753x_remove,
711 .driver = {
712 .name = "mt753x",
713 .of_match_table = mt753x_ids,
714 },
715 };
716
717 static int __init mt753x_init(void)
718 {
719 int ret;
720
721 INIT_LIST_HEAD(&mt753x_devs);
722 ret = platform_driver_register(&mt753x_driver);
723
724 mt753x_nl_init();
725
726 return ret;
727 }
728 module_init(mt753x_init);
729
730 static void __exit mt753x_exit(void)
731 {
732 mt753x_nl_exit();
733
734 platform_driver_unregister(&mt753x_driver);
735 }
736 module_exit(mt753x_exit);
737
738 MODULE_LICENSE("GPL");
739 MODULE_AUTHOR("Weijie Gao <weijie.gao@mediatek.com>");
740 MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch");