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mediatek: add v4.19 support
[openwrt/staging/lynxis.git] / target / linux / mediatek / files-4.19 / drivers / net / phy / mtk / mt753x / mt7530.c
1 /*
2 * Driver for MediaTek MT7530 gigabit switch
3 *
4 * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
5 *
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13
14 #include "mt753x.h"
15 #include "mt753x_regs.h"
16
17 /* MT7530 registers */
18
19 /* Unique fields of PMCR for MT7530 */
20 #define FORCE_MODE BIT(15)
21
22 /* Unique fields of GMACCR for MT7530 */
23 #define VLAN_SUPT_NO_S 14
24 #define VLAN_SUPT_NO_M 0x1c000
25 #define LATE_COL_DROP BIT(13)
26
27 /* Unique fields of (M)HWSTRAP for MT7530 */
28 #define BOND_OPTION BIT(24)
29 #define P5_PHY0_SEL BIT(20)
30 #define CHG_TRAP BIT(16)
31 #define LOOPDET_DIS BIT(14)
32 #define P5_INTF_SEL_GMAC5 BIT(13)
33 #define SMI_ADDR_S 11
34 #define SMI_ADDR_M 0x1800
35 #define XTAL_FSEL_S 9
36 #define XTAL_FSEL_M 0x600
37 #define P6_INTF_DIS BIT(8)
38 #define P5_INTF_MODE_RGMII BIT(7)
39 #define P5_INTF_DIS_S BIT(6)
40 #define C_MDIO_BPS_S BIT(5)
41 #define EEPROM_EN_S BIT(4)
42
43 /* PHY EEE Register bitmap of define */
44 #define PHY_DEV07 0x07
45 #define PHY_DEV07_REG_03C 0x3c
46
47 /* PHY Extend Register 0x14 bitmap of define */
48 #define PHY_EXT_REG_14 0x14
49
50 /* Fields of PHY_EXT_REG_14 */
51 #define PHY_EN_DOWN_SHFIT BIT(4)
52
53 /* PHY Token Ring Register 0x10 bitmap of define */
54 #define PHY_TR_REG_10 0x10
55
56 /* PHY Token Ring Register 0x12 bitmap of define */
57 #define PHY_TR_REG_12 0x12
58
59 /* PHY LPI PCS/DSP Control Register bitmap of define */
60 #define PHY_LPI_REG_11 0x11
61
62 /* PHY DEV 0x1e Register bitmap of define */
63 #define PHY_DEV1E 0x1e
64 #define PHY_DEV1E_REG_123 0x123
65 #define PHY_DEV1E_REG_A6 0xa6
66
67 /* Values of XTAL_FSEL */
68 #define XTAL_20MHZ 1
69 #define XTAL_40MHZ 2
70 #define XTAL_25MHZ 3
71
72 #define P6ECR 0x7830
73 #define P6_INTF_MODE_TRGMII BIT(0)
74
75 #define TRGMII_TXCTRL 0x7a40
76 #define TRAIN_TXEN BIT(31)
77 #define TXC_INV BIT(30)
78 #define TX_DOEO BIT(29)
79 #define TX_RST BIT(28)
80
81 #define TRGMII_TD0_CTRL 0x7a50
82 #define TRGMII_TD1_CTRL 0x7a58
83 #define TRGMII_TD2_CTRL 0x7a60
84 #define TRGMII_TD3_CTRL 0x7a68
85 #define TRGMII_TXCTL_CTRL 0x7a70
86 #define TRGMII_TCK_CTRL 0x7a78
87 #define TRGMII_TD_CTRL(n) (0x7a50 + (n) * 8)
88 #define NUM_TRGMII_CTRL 6
89 #define TX_DMPEDRV BIT(31)
90 #define TX_DM_SR BIT(15)
91 #define TX_DMERODT BIT(14)
92 #define TX_DMOECTL BIT(13)
93 #define TX_TAP_S 8
94 #define TX_TAP_M 0xf00
95 #define TX_TRAIN_WD_S 0
96 #define TX_TRAIN_WD_M 0xff
97
98 #define TRGMII_TD0_ODT 0x7a54
99 #define TRGMII_TD1_ODT 0x7a5c
100 #define TRGMII_TD2_ODT 0x7a64
101 #define TRGMII_TD3_ODT 0x7a6c
102 #define TRGMII_TXCTL_ODT 0x7574
103 #define TRGMII_TCK_ODT 0x757c
104 #define TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
105 #define NUM_TRGMII_ODT 6
106 #define TX_DM_DRVN_PRE_S 30
107 #define TX_DM_DRVN_PRE_M 0xc0000000
108 #define TX_DM_DRVP_PRE_S 28
109 #define TX_DM_DRVP_PRE_M 0x30000000
110 #define TX_DM_TDSEL_S 24
111 #define TX_DM_TDSEL_M 0xf000000
112 #define TX_ODTEN BIT(23)
113 #define TX_DME_PRE BIT(20)
114 #define TX_DM_DRVNT0 BIT(19)
115 #define TX_DM_DRVPT0 BIT(18)
116 #define TX_DM_DRVNTE BIT(17)
117 #define TX_DM_DRVPTE BIT(16)
118 #define TX_DM_ODTN_S 12
119 #define TX_DM_ODTN_M 0x7000
120 #define TX_DM_ODTP_S 8
121 #define TX_DM_ODTP_M 0x700
122 #define TX_DM_DRVN_S 4
123 #define TX_DM_DRVN_M 0xf0
124 #define TX_DM_DRVP_S 0
125 #define TX_DM_DRVP_M 0x0f
126
127 #define P5RGMIIRXCR 0x7b00
128 #define CSR_RGMII_RCTL_CFG_S 24
129 #define CSR_RGMII_RCTL_CFG_M 0x7000000
130 #define CSR_RGMII_RXD_CFG_S 16
131 #define CSR_RGMII_RXD_CFG_M 0x70000
132 #define CSR_RGMII_EDGE_ALIGN BIT(8)
133 #define CSR_RGMII_RXC_90DEG_CFG_S 4
134 #define CSR_RGMII_RXC_90DEG_CFG_M 0xf0
135 #define CSR_RGMII_RXC_0DEG_CFG_S 0
136 #define CSR_RGMII_RXC_0DEG_CFG_M 0x0f
137
138 #define P5RGMIITXCR 0x7b04
139 #define CSR_RGMII_TXEN_CFG_S 16
140 #define CSR_RGMII_TXEN_CFG_M 0x70000
141 #define CSR_RGMII_TXD_CFG_S 8
142 #define CSR_RGMII_TXD_CFG_M 0x700
143 #define CSR_RGMII_TXC_CFG_S 0
144 #define CSR_RGMII_TXC_CFG_M 0x1f
145
146 #define CHIP_REV 0x7ffc
147 #define CHIP_NAME_S 16
148 #define CHIP_NAME_M 0xffff0000
149 #define CHIP_REV_S 0
150 #define CHIP_REV_M 0x0f
151
152 /* MMD registers */
153 #define CORE_PLL_GROUP2 0x401
154 #define RG_SYSPLL_EN_NORMAL BIT(15)
155 #define RG_SYSPLL_VODEN BIT(14)
156 #define RG_SYSPLL_POSDIV_S 5
157 #define RG_SYSPLL_POSDIV_M 0x60
158
159 #define CORE_PLL_GROUP4 0x403
160 #define RG_SYSPLL_DDSFBK_EN BIT(12)
161 #define RG_SYSPLL_BIAS_EN BIT(11)
162 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
163
164 #define CORE_PLL_GROUP5 0x404
165 #define RG_LCDDS_PCW_NCPO1_S 0
166 #define RG_LCDDS_PCW_NCPO1_M 0xffff
167
168 #define CORE_PLL_GROUP6 0x405
169 #define RG_LCDDS_PCW_NCPO0_S 0
170 #define RG_LCDDS_PCW_NCPO0_M 0xffff
171
172 #define CORE_PLL_GROUP7 0x406
173 #define RG_LCDDS_PWDB BIT(15)
174 #define RG_LCDDS_ISO_EN BIT(13)
175 #define RG_LCCDS_C_S 4
176 #define RG_LCCDS_C_M 0x70
177 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
178
179 #define CORE_PLL_GROUP10 0x409
180 #define RG_LCDDS_SSC_DELTA_S 0
181 #define RG_LCDDS_SSC_DELTA_M 0xfff
182
183 #define CORE_PLL_GROUP11 0x40a
184 #define RG_LCDDS_SSC_DELTA1_S 0
185 #define RG_LCDDS_SSC_DELTA1_M 0xfff
186
187 #define CORE_GSWPLL_GCR_1 0x040d
188 #define GSWPLL_PREDIV_S 14
189 #define GSWPLL_PREDIV_M 0xc000
190 #define GSWPLL_POSTDIV_200M_S 12
191 #define GSWPLL_POSTDIV_200M_M 0x3000
192 #define GSWPLL_EN_PRE BIT(11)
193 #define GSWPLL_FBKSEL BIT(10)
194 #define GSWPLL_BP BIT(9)
195 #define GSWPLL_BR BIT(8)
196 #define GSWPLL_FBKDIV_200M_S 0
197 #define GSWPLL_FBKDIV_200M_M 0xff
198
199 #define CORE_GSWPLL_GCR_2 0x040e
200 #define GSWPLL_POSTDIV_500M_S 8
201 #define GSWPLL_POSTDIV_500M_M 0x300
202 #define GSWPLL_FBKDIV_500M_S 0
203 #define GSWPLL_FBKDIV_500M_M 0xff
204
205 #define TRGMII_GSW_CLK_CG 0x0410
206 #define TRGMIICK_EN BIT(1)
207 #define GSWCK_EN BIT(0)
208
209 static int mt7530_mii_read(struct gsw_mt753x *gsw, int phy, int reg)
210 {
211 if (phy < MT753X_NUM_PHYS)
212 phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
213
214 return mdiobus_read(gsw->host_bus, phy, reg);
215 }
216
217 static void mt7530_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val)
218 {
219 if (phy < MT753X_NUM_PHYS)
220 phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
221
222 mdiobus_write(gsw->host_bus, phy, reg, val);
223 }
224
225 static int mt7530_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)
226 {
227 u16 val;
228
229 if (addr < MT753X_NUM_PHYS)
230 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
231
232 mutex_lock(&gsw->host_bus->mdio_lock);
233
234 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,
235 (MMD_ADDR << MMD_CMD_S) |
236 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
237
238 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, reg);
239
240 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,
241 (MMD_DATA << MMD_CMD_S) |
242 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
243
244 val = gsw->host_bus->read(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG);
245
246 mutex_unlock(&gsw->host_bus->mdio_lock);
247
248 return val;
249 }
250
251 static void mt7530_mmd_write(struct gsw_mt753x *gsw, int addr, int devad,
252 u16 reg, u16 val)
253 {
254 if (addr < MT753X_NUM_PHYS)
255 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
256
257 mutex_lock(&gsw->host_bus->mdio_lock);
258
259 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,
260 (MMD_ADDR << MMD_CMD_S) |
261 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
262
263 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, reg);
264
265 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,
266 (MMD_DATA << MMD_CMD_S) |
267 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
268
269 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, val);
270
271 mutex_unlock(&gsw->host_bus->mdio_lock);
272 }
273
274 static void mt7530_core_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val)
275 {
276 gsw->mmd_write(gsw, 0, 0x1f, reg, val);
277 }
278
279 static int mt7530_mac_port_setup(struct gsw_mt753x *gsw)
280 {
281 u32 hwstrap, p6ecr = 0, p5mcr, p6mcr, phyad;
282
283 hwstrap = mt753x_reg_read(gsw, HWSTRAP);
284 hwstrap &= ~(P6_INTF_DIS | P5_INTF_MODE_RGMII | P5_INTF_DIS_S);
285 hwstrap |= CHG_TRAP | P5_INTF_SEL_GMAC5;
286
287 if (gsw->direct_phy_access)
288 hwstrap &= ~C_MDIO_BPS_S;
289 else
290 hwstrap |= C_MDIO_BPS_S;
291
292 if (!gsw->port5_cfg.enabled) {
293 p5mcr = FORCE_MODE;
294 hwstrap |= P5_INTF_DIS_S;
295 } else {
296 p5mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
297 MAC_MODE | MAC_TX_EN | MAC_RX_EN |
298 BKOFF_EN | BACKPR_EN;
299
300 if (gsw->port5_cfg.force_link) {
301 p5mcr |= FORCE_MODE | FORCE_LINK | FORCE_RX_FC |
302 FORCE_TX_FC;
303 p5mcr |= gsw->port5_cfg.speed << FORCE_SPD_S;
304
305 if (gsw->port5_cfg.duplex)
306 p5mcr |= FORCE_DPX;
307 }
308
309 switch (gsw->port5_cfg.phy_mode) {
310 case PHY_INTERFACE_MODE_MII:
311 case PHY_INTERFACE_MODE_GMII:
312 break;
313 case PHY_INTERFACE_MODE_RGMII:
314 hwstrap |= P5_INTF_MODE_RGMII;
315 break;
316 default:
317 dev_info(gsw->dev, "%s is not supported by port5\n",
318 phy_modes(gsw->port5_cfg.phy_mode));
319 p5mcr = FORCE_MODE;
320 hwstrap |= P5_INTF_DIS_S;
321 }
322
323 /* Port5 to PHY direct mode */
324 if (of_property_read_u32(gsw->port5_cfg.np, "phy-address",
325 &phyad))
326 goto parse_p6;
327
328 if (phyad != 0 && phyad != 4) {
329 dev_info(gsw->dev,
330 "Only PHY 0/4 can be connected to Port 5\n");
331 goto parse_p6;
332 }
333
334 hwstrap &= ~P5_INTF_SEL_GMAC5;
335 if (phyad == 0)
336 hwstrap |= P5_PHY0_SEL;
337 else
338 hwstrap &= ~P5_PHY0_SEL;
339 }
340
341 parse_p6:
342 if (!gsw->port6_cfg.enabled) {
343 p6mcr = FORCE_MODE;
344 hwstrap |= P6_INTF_DIS;
345 } else {
346 p6mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
347 MAC_MODE | MAC_TX_EN | MAC_RX_EN |
348 BKOFF_EN | BACKPR_EN;
349
350 if (gsw->port6_cfg.force_link) {
351 p6mcr |= FORCE_MODE | FORCE_LINK | FORCE_RX_FC |
352 FORCE_TX_FC;
353 p6mcr |= gsw->port6_cfg.speed << FORCE_SPD_S;
354
355 if (gsw->port6_cfg.duplex)
356 p6mcr |= FORCE_DPX;
357 }
358
359 switch (gsw->port6_cfg.phy_mode) {
360 case PHY_INTERFACE_MODE_RGMII:
361 break;
362 case PHY_INTERFACE_MODE_TRGMII:
363 /* set MT7530 central align */
364 p6ecr = BIT(1); /* TODO: confirm this */
365 break;
366 default:
367 dev_info(gsw->dev, "%s is not supported by port6\n",
368 phy_modes(gsw->port6_cfg.phy_mode));
369 p6mcr = FORCE_MODE;
370 hwstrap |= P6_INTF_DIS;
371 }
372 }
373
374 mt753x_reg_write(gsw, MHWSTRAP, hwstrap);
375 mt753x_reg_write(gsw, P6ECR, p6ecr);
376
377 mt753x_reg_write(gsw, PMCR(5), p5mcr);
378 mt753x_reg_write(gsw, PMCR(6), p6mcr);
379
380 return 0;
381 }
382
383 static void mt7530_core_pll_setup(struct gsw_mt753x *gsw)
384 {
385 u32 hwstrap, val, ncpo1, ssc_delta;
386 int i;
387
388 hwstrap = mt753x_reg_read(gsw, HWSTRAP);
389
390 switch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) {
391 case XTAL_40MHZ:
392 /* Disable MT7530 core clock */
393 mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, 0);
394
395 /* disable MT7530 PLL */
396 mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_1,
397 (2 << GSWPLL_POSTDIV_200M_S) |
398 (32 << GSWPLL_FBKDIV_200M_S));
399
400 /* For MT7530 core clock = 500Mhz */
401 mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_2,
402 (1 << GSWPLL_POSTDIV_500M_S) |
403 (25 << GSWPLL_FBKDIV_500M_S));
404
405 /* Enable MT7530 PLL */
406 mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_1,
407 (2 << GSWPLL_POSTDIV_200M_S) |
408 (32 << GSWPLL_FBKDIV_200M_S) |
409 GSWPLL_EN_PRE);
410
411 usleep_range(20, 40);
412
413 /* Enable MT7530 core clock */
414 mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, GSWCK_EN);
415 break;
416 default:
417 /* TODO: PLL settings for 20/25MHz */
418 break;
419 }
420
421 if (gsw->port6_cfg.enabled &&
422 gsw->port6_cfg.phy_mode == PHY_INTERFACE_MODE_TRGMII) {
423 ncpo1 = 0x1400;
424 ssc_delta = 0x57;
425 } else {
426 /* RGMII */
427 ncpo1 = 0x0c80;
428 ssc_delta = 0x87;
429 }
430
431 /* Setup the MT7530 TRGMII Tx Clock */
432 mt7530_core_reg_write(gsw, CORE_PLL_GROUP5, ncpo1);
433 mt7530_core_reg_write(gsw, CORE_PLL_GROUP6, 0);
434 mt7530_core_reg_write(gsw, CORE_PLL_GROUP10, ssc_delta);
435 mt7530_core_reg_write(gsw, CORE_PLL_GROUP11, ssc_delta);
436 mt7530_core_reg_write(gsw, CORE_PLL_GROUP4,
437 RG_SYSPLL_DDSFBK_EN |
438 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
439
440 mt7530_core_reg_write(gsw, CORE_PLL_GROUP2,
441 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
442 (1 << RG_SYSPLL_POSDIV_S));
443
444 mt7530_core_reg_write(gsw, CORE_PLL_GROUP7,
445 RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
446 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
447
448 /* Enable MT7530 TRGMII clock */
449 mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, GSWCK_EN | TRGMIICK_EN);
450
451 val = mt753x_reg_read(gsw, TRGMII_TXCTRL);
452 val &= ~TXC_INV;
453 mt753x_reg_write(gsw, TRGMII_TXCTRL, val);
454
455 /* lower Tx Driving */
456 for (i = 0 ; i < NUM_TRGMII_ODT; i++)
457 mt753x_reg_write(gsw, TRGMII_TD_ODT(i),
458 (8 << TX_DM_DRVP_S) | (8 << TX_DM_DRVN_S));
459
460 mt753x_reg_write(gsw, TRGMII_TCK_CTRL,
461 (8 << TX_TAP_S) | (0x55 << TX_TRAIN_WD_S));
462
463 /* delay setting for 10/1000M */
464 mt753x_reg_write(gsw, P5RGMIIRXCR,
465 CSR_RGMII_EDGE_ALIGN |
466 (2 << CSR_RGMII_RXC_0DEG_CFG_S));
467 mt753x_reg_write(gsw, P5RGMIITXCR, 0x14 << CSR_RGMII_TXC_CFG_S);
468 }
469
470 static int mt7530_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev)
471 {
472 u32 rev;
473
474 rev = mt753x_reg_read(gsw, CHIP_REV);
475
476 if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7530) {
477 if (crev) {
478 crev->rev = rev & CHIP_REV_M;
479 crev->name = "MT7530";
480 }
481
482 return 0;
483 }
484
485 return -ENODEV;
486 }
487
488 static void mt7530_phy_setting(struct gsw_mt753x *gsw)
489 {
490 int i;
491 u32 val;
492
493 for (i = 0; i < MT753X_NUM_PHYS; i++) {
494 /* Disable EEE */
495 gsw->mmd_write(gsw, i, PHY_DEV07, PHY_DEV07_REG_03C, 0);
496
497 /* Enable HW auto downshift */
498 gsw->mii_write(gsw, i, 0x1f, 0x1);
499 val = gsw->mii_read(gsw, i, PHY_EXT_REG_14);
500 val |= PHY_EN_DOWN_SHFIT;
501 gsw->mii_write(gsw, i, PHY_EXT_REG_14, val);
502
503 /* Increase SlvDPSready time */
504 gsw->mii_write(gsw, i, 0x1f, 0x52b5);
505 gsw->mii_write(gsw, i, PHY_TR_REG_10, 0xafae);
506 gsw->mii_write(gsw, i, PHY_TR_REG_12, 0x2f);
507 gsw->mii_write(gsw, i, PHY_TR_REG_10, 0x8fae);
508
509 /* Increase post_update_timer */
510 gsw->mii_write(gsw, i, 0x1f, 0x3);
511 gsw->mii_write(gsw, i, PHY_LPI_REG_11, 0x4b);
512 gsw->mii_write(gsw, i, 0x1f, 0);
513
514 /* Adjust 100_mse_threshold */
515 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff);
516
517 /* Disable mcc */
518 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300);
519 }
520 }
521
522 static int mt7530_sw_init(struct gsw_mt753x *gsw)
523 {
524 int i;
525 u32 val;
526
527 gsw->direct_phy_access = of_property_read_bool(gsw->dev->of_node,
528 "mt7530,direct-phy-access");
529
530 /* Force MT7530 to use (in)direct PHY access */
531 val = mt753x_reg_read(gsw, HWSTRAP);
532 val |= CHG_TRAP;
533 if (gsw->direct_phy_access)
534 val &= ~C_MDIO_BPS_S;
535 else
536 val |= C_MDIO_BPS_S;
537 mt753x_reg_write(gsw, MHWSTRAP, val);
538
539 /* Read PHY address base from HWSTRAP */
540 gsw->phy_base = (((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3) + 8;
541 gsw->phy_base &= MT753X_SMI_ADDR_MASK;
542
543 if (gsw->direct_phy_access) {
544 gsw->mii_read = mt7530_mii_read;
545 gsw->mii_write = mt7530_mii_write;
546 gsw->mmd_read = mt7530_mmd_read;
547 gsw->mmd_write = mt7530_mmd_write;
548 } else {
549 gsw->mii_read = mt753x_mii_read;
550 gsw->mii_write = mt753x_mii_write;
551 gsw->mmd_read = mt753x_mmd_ind_read;
552 gsw->mmd_write = mt753x_mmd_ind_write;
553 }
554
555 for (i = 0; i < MT753X_NUM_PHYS; i++) {
556 val = gsw->mii_read(gsw, i, MII_BMCR);
557 val |= BMCR_PDOWN;
558 gsw->mii_write(gsw, i, MII_BMCR, val);
559 }
560
561 /* Force MAC link down before reset */
562 mt753x_reg_write(gsw, PMCR(5), FORCE_MODE);
563 mt753x_reg_write(gsw, PMCR(6), FORCE_MODE);
564
565 /* Switch soft reset */
566 /* BUG: sw reset causes gsw int flooding */
567 mt753x_reg_write(gsw, SYS_CTRL, SW_PHY_RST | SW_SYS_RST | SW_REG_RST);
568 usleep_range(10, 20);
569
570 /* global mac control settings configuration */
571 mt753x_reg_write(gsw, GMACCR,
572 LATE_COL_DROP | (15 << MTCC_LMT_S) |
573 (2 << MAX_RX_JUMBO_S) | RX_PKT_LEN_MAX_JUMBO);
574
575 mt7530_core_pll_setup(gsw);
576 mt7530_mac_port_setup(gsw);
577
578 return 0;
579 }
580
581 static int mt7530_sw_post_init(struct gsw_mt753x *gsw)
582 {
583 int i;
584 u32 val;
585
586 mt7530_phy_setting(gsw);
587
588 for (i = 0; i < MT753X_NUM_PHYS; i++) {
589 val = gsw->mii_read(gsw, i, MII_BMCR);
590 val &= ~BMCR_PDOWN;
591 gsw->mii_write(gsw, i, MII_BMCR, val);
592 }
593
594 return 0;
595 }
596
597 struct mt753x_sw_id mt7530_id = {
598 .model = MT7530,
599 .detect = mt7530_sw_detect,
600 .init = mt7530_sw_init,
601 .post_init = mt7530_sw_post_init
602 };
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