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[openwrt/staging/lynxis.git] / target / linux / layerscape / patches-4.4 / 3227-ls2088a-dts-add-ls2088a-dts.patch
1 From 45ba5bb2bdc9462fe5998aeb75e2c7e33b56c9fb Mon Sep 17 00:00:00 2001
2 From: Zhao Qiang <qiang.zhao@nxp.com>
3 Date: Mon, 7 Nov 2016 10:23:52 +0800
4 Subject: [PATCH 227/238] ls2088a/dts: add ls2088a dts
5
6 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
7 ---
8 arch/arm64/boot/dts/freescale/Makefile | 2 +
9 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 241 ++++++
10 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 207 +++++
11 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 854 +++++++++++++++++++++
12 4 files changed, 1304 insertions(+)
13 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
14 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
15 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
16
17 --- a/arch/arm64/boot/dts/freescale/Makefile
18 +++ b/arch/arm64/boot/dts/freescale/Makefile
19 @@ -6,6 +6,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
20 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
21 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
22 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
23 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
24 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
25
26 always := $(dtb-y)
27 subdir-y := $(dts-dirs)
28 --- /dev/null
29 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
30 @@ -0,0 +1,241 @@
31 +/*
32 + * Device Tree file for Freescale LS2080a QDS Board
33 + *
34 + * Copyright (C) 2016, Freescale Semiconductor
35 + *
36 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
37 + *
38 + * This file is licensed under the terms of the GNU General Public
39 + * License version 2. This program is licensed "as is" without any
40 + * warranty of any kind, whether express or implied.
41 + */
42 +
43 +/dts-v1/;
44 +
45 +#include "fsl-ls2088a.dtsi"
46 +
47 +/ {
48 + model = "Freescale Layerscape 2088a QDS Board";
49 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
50 +};
51 +
52 +&esdhc {
53 + status = "okay";
54 +};
55 +
56 +&ifc {
57 + status = "okay";
58 + #address-cells = <2>;
59 + #size-cells = <1>;
60 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
61 + 0x2 0x0 0x5 0x30000000 0x00010000
62 + 0x3 0x0 0x5 0x20000000 0x00010000>;
63 +
64 + nor@0,0 {
65 + #address-cells = <1>;
66 + #size-cells = <1>;
67 + compatible = "cfi-flash";
68 + reg = <0x0 0x0 0x8000000>;
69 + bank-width = <2>;
70 + device-width = <1>;
71 + };
72 +
73 + nand@2,0 {
74 + compatible = "fsl,ifc-nand";
75 + reg = <0x2 0x0 0x10000>;
76 + };
77 +
78 + cpld@3,0 {
79 + reg = <0x3 0x0 0x10000>;
80 + compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
81 + "fsl,fpga-qixis";
82 + };
83 +};
84 +
85 +&ftm0 {
86 + status = "okay";
87 +};
88 +
89 +&i2c0 {
90 + status = "okay";
91 + pca9547@77 {
92 + compatible = "nxp,pca9547";
93 + reg = <0x77>;
94 + #address-cells = <1>;
95 + #size-cells = <0>;
96 + i2c@0 {
97 + #address-cells = <1>;
98 + #size-cells = <0>;
99 + reg = <0x00>;
100 + rtc@68 {
101 + compatible = "dallas,ds3232";
102 + reg = <0x68>;
103 + };
104 + };
105 +
106 + i2c@2 {
107 + #address-cells = <1>;
108 + #size-cells = <0>;
109 + reg = <0x02>;
110 +
111 + ina220@40 {
112 + compatible = "ti,ina220";
113 + reg = <0x40>;
114 + shunt-resistor = <500>;
115 + };
116 + ina220@41 {
117 + compatible = "ti,ina220";
118 + reg = <0x41>;
119 + shunt-resistor = <1000>;
120 + };
121 + };
122 +
123 + i2c@3 {
124 + #address-cells = <1>;
125 + #size-cells = <0>;
126 + reg = <0x3>;
127 +
128 + adt7481@4c {
129 + compatible = "adi,adt7461";
130 + reg = <0x4c>;
131 + };
132 + };
133 + };
134 +};
135 +
136 +&i2c1 {
137 + status = "disabled";
138 +};
139 +
140 +&i2c2 {
141 + status = "disabled";
142 +};
143 +
144 +&i2c3 {
145 + status = "disabled";
146 +};
147 +
148 +&dspi {
149 + status = "okay";
150 + dflash0: n25q128a {
151 + #address-cells = <1>;
152 + #size-cells = <1>;
153 + compatible = "st,m25p80";
154 + spi-max-frequency = <3000000>;
155 + reg = <0>;
156 + };
157 + dflash1: sst25wf040b {
158 + #address-cells = <1>;
159 + #size-cells = <1>;
160 + compatible = "st,m25p80";
161 + spi-max-frequency = <3000000>;
162 + reg = <1>;
163 + };
164 + dflash2: en25s64 {
165 + #address-cells = <1>;
166 + #size-cells = <1>;
167 + compatible = "st,m25p80";
168 + spi-max-frequency = <3000000>;
169 + reg = <2>;
170 + };
171 +};
172 +
173 +&qspi {
174 + status = "okay";
175 + qflash0: s25fs256s1@0 {
176 + #address-cells = <1>;
177 + #size-cells = <1>;
178 + compatible = "st,m25p80";
179 + spi-max-frequency = <20000000>;
180 + m25p,fast-read;
181 + reg = <0>;
182 + };
183 +
184 + qflash2: s25fs256s1@2 {
185 + #address-cells = <1>;
186 + #size-cells = <1>;
187 + compatible = "st,m25p80";
188 + spi-max-frequency = <20000000>;
189 + m25p,fast-read;
190 + reg = <2>;
191 + };
192 +};
193 +
194 +&sata0 {
195 + status = "okay";
196 +};
197 +
198 +&sata1 {
199 + status = "okay";
200 +};
201 +
202 +&usb0 {
203 + status = "okay";
204 +};
205 +
206 +&usb1 {
207 + status = "okay";
208 +};
209 +
210 +&ifc {
211 + boardctrl: board-control@3,0 {
212 + #address-cells = <1>;
213 + #size-cells = <1>;
214 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
215 + reg = <3 0 0x300>; /* TODO check address */
216 + ranges = <0 3 0 0x300>;
217 +
218 + mdio_mux_emi1 {
219 + compatible = "mdio-mux-mmioreg", "mdio-mux";
220 + mdio-parent-bus = <&emdio1>;
221 + reg = <0x54 1>; /* BRDCFG4 */
222 + mux-mask = <0xe0>; /* EMI1_MDIO */
223 +
224 + #address-cells=<1>;
225 + #size-cells = <0>;
226 +
227 + /* Child MDIO buses, one for each riser card:
228 + reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
229 +
230 + VSC8234 PHYs on the riser cards.
231 + */
232 +
233 + mdio_mux3: mdio@60 {
234 + reg = <0x60>;
235 + #address-cells = <1>;
236 + #size-cells = <0>;
237 +
238 + mdio0_phy12: mdio_phy0@1c {
239 + reg = <0x1c>;
240 + phy-connection-type = "sgmii";
241 + };
242 + mdio0_phy13: mdio_phy1@1d {
243 + reg = <0x1d>;
244 + phy-connection-type = "sgmii";
245 + };
246 + mdio0_phy14: mdio_phy2@1e {
247 + reg = <0x1e>;
248 + phy-connection-type = "sgmii";
249 + };
250 + mdio0_phy15: mdio_phy3@1f {
251 + reg = <0x1f>;
252 + phy-connection-type = "sgmii";
253 + };
254 + };
255 + };
256 + };
257 +};
258 +
259 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
260 +&dpmac9 {
261 + phy-handle = <&mdio0_phy12>;
262 +};
263 +&dpmac10 {
264 + phy-handle = <&mdio0_phy13>;
265 +};
266 +&dpmac11 {
267 + phy-handle = <&mdio0_phy14>;
268 +};
269 +&dpmac12 {
270 + phy-handle = <&mdio0_phy15>;
271 +};
272 --- /dev/null
273 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
274 @@ -0,0 +1,207 @@
275 +/*
276 + * Device Tree file for Freescale LS2080a RDB board
277 + *
278 + * Copyright (C) 2015, Freescale Semiconductor
279 + *
280 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
281 + *
282 + * This file is licensed under the terms of the GNU General Public
283 + * License version 2. This program is licensed "as is" without any
284 + * warranty of any kind, whether express or implied.
285 + */
286 +
287 +/dts-v1/;
288 +
289 +#include "fsl-ls2088a.dtsi"
290 +
291 +/ {
292 + model = "Freescale Layerscape 2088a RDB Board";
293 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
294 +};
295 +
296 +&esdhc {
297 + status = "okay";
298 +};
299 +
300 +&ifc {
301 + status = "okay";
302 + #address-cells = <2>;
303 + #size-cells = <1>;
304 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
305 + 0x2 0x0 0x5 0x30000000 0x00010000
306 + 0x3 0x0 0x5 0x20000000 0x00010000>;
307 +
308 + nor@0,0 {
309 + #address-cells = <1>;
310 + #size-cells = <1>;
311 + compatible = "cfi-flash";
312 + reg = <0x0 0x0 0x8000000>;
313 + bank-width = <2>;
314 + device-width = <1>;
315 + };
316 +
317 + nand@2,0 {
318 + compatible = "fsl,ifc-nand";
319 + reg = <0x2 0x0 0x10000>;
320 + };
321 +
322 + cpld@3,0 {
323 + reg = <0x3 0x0 0x10000>;
324 + compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
325 + "fsl,fpga-qixis";
326 + };
327 +};
328 +
329 +&ftm0 {
330 + status = "okay";
331 +};
332 +
333 +&i2c0 {
334 + status = "okay";
335 + pca9547@75 {
336 + compatible = "nxp,pca9547";
337 + reg = <0x75>;
338 + #address-cells = <1>;
339 + #size-cells = <0>;
340 + i2c-mux-never-disable;
341 + i2c@1 {
342 + #address-cells = <1>;
343 + #size-cells = <0>;
344 + reg = <0x01>;
345 + rtc@68 {
346 + compatible = "dallas,ds3232";
347 + reg = <0x68>;
348 + };
349 + };
350 +
351 + i2c@3 {
352 + #address-cells = <1>;
353 + #size-cells = <0>;
354 + reg = <0x3>;
355 +
356 + adt7481@4c {
357 + compatible = "adi,adt7461";
358 + reg = <0x4c>;
359 + };
360 + };
361 + };
362 +};
363 +
364 +&i2c1 {
365 + status = "disabled";
366 +};
367 +
368 +&i2c2 {
369 + status = "disabled";
370 +};
371 +
372 +&i2c3 {
373 + status = "disabled";
374 +};
375 +
376 +&dspi {
377 + status = "okay";
378 + dflash0: n25q512a {
379 + #address-cells = <1>;
380 + #size-cells = <1>;
381 + compatible = "st,m25p80";
382 + spi-max-frequency = <3000000>;
383 + reg = <0>;
384 + };
385 +};
386 +
387 +&qspi {
388 + status = "disabled";
389 +};
390 +
391 +&sata0 {
392 + status = "okay";
393 +};
394 +
395 +&sata1 {
396 + status = "okay";
397 +};
398 +
399 +&usb0 {
400 + status = "okay";
401 +};
402 +
403 +&usb1 {
404 + status = "okay";
405 +};
406 +
407 +&emdio1 {
408 + /* CS4340 PHYs */
409 + mdio1_phy1: emdio1_phy@1 {
410 + reg = <0x10>;
411 + phy-connection-type = "xfi";
412 + };
413 + mdio1_phy2: emdio1_phy@2 {
414 + reg = <0x11>;
415 + phy-connection-type = "xfi";
416 + };
417 + mdio1_phy3: emdio1_phy@3 {
418 + reg = <0x12>;
419 + phy-connection-type = "xfi";
420 + };
421 + mdio1_phy4: emdio1_phy@4 {
422 + reg = <0x13>;
423 + phy-connection-type = "xfi";
424 + };
425 +};
426 +
427 +&emdio2 {
428 + /* AQR405 PHYs */
429 + mdio2_phy1: emdio2_phy@1 {
430 + compatible = "ethernet-phy-ieee802.3-c45";
431 + interrupts = <0 1 0x4>; /* Level high type */
432 + reg = <0x0>;
433 + phy-connection-type = "xfi";
434 + };
435 + mdio2_phy2: emdio2_phy@2 {
436 + compatible = "ethernet-phy-ieee802.3-c45";
437 + interrupts = <0 2 0x4>; /* Level high type */
438 + reg = <0x1>;
439 + phy-connection-type = "xfi";
440 + };
441 + mdio2_phy3: emdio2_phy@3 {
442 + compatible = "ethernet-phy-ieee802.3-c45";
443 + interrupts = <0 4 0x4>; /* Level high type */
444 + reg = <0x2>;
445 + phy-connection-type = "xfi";
446 + };
447 + mdio2_phy4: emdio2_phy@4 {
448 + compatible = "ethernet-phy-ieee802.3-c45";
449 + interrupts = <0 5 0x4>; /* Level high type */
450 + reg = <0x3>;
451 + phy-connection-type = "xfi";
452 + };
453 +};
454 +
455 +/* Update DPMAC connections to external PHYs, under the assumption of
456 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
457 + */
458 +&dpmac1 {
459 + phy-handle = <&mdio1_phy1>;
460 +};
461 +&dpmac2 {
462 + phy-handle = <&mdio1_phy2>;
463 +};
464 +&dpmac3 {
465 + phy-handle = <&mdio1_phy3>;
466 +};
467 +&dpmac4 {
468 + phy-handle = <&mdio1_phy4>;
469 +};
470 +&dpmac5 {
471 + phy-handle = <&mdio2_phy1>;
472 +};
473 +&dpmac6 {
474 + phy-handle = <&mdio2_phy2>;
475 +};
476 +&dpmac7 {
477 + phy-handle = <&mdio2_phy3>;
478 +};
479 +&dpmac8 {
480 + phy-handle = <&mdio2_phy4>;
481 +};
482 --- /dev/null
483 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
484 @@ -0,0 +1,854 @@
485 +/*
486 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
487 + *
488 + * Copyright (C) 2016, Freescale Semiconductor
489 + *
490 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
491 + *
492 + * This file is dual-licensed: you can use it either under the terms
493 + * of the GPLv2 or the X11 license, at your option. Note that this dual
494 + * licensing only applies to this file, and not this project as a
495 + * whole.
496 + *
497 + * a) This library is free software; you can redistribute it and/or
498 + * modify it under the terms of the GNU General Public License as
499 + * published by the Free Software Foundation; either version 2 of the
500 + * License, or (at your option) any later version.
501 + *
502 + * This library is distributed in the hope that it will be useful,
503 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
504 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
505 + * GNU General Public License for more details.
506 + *
507 + * Or, alternatively,
508 + *
509 + * b) Permission is hereby granted, free of charge, to any person
510 + * obtaining a copy of this software and associated documentation
511 + * files (the "Software"), to deal in the Software without
512 + * restriction, including without limitation the rights to use,
513 + * copy, modify, merge, publish, distribute, sublicense, and/or
514 + * sell copies of the Software, and to permit persons to whom the
515 + * Software is furnished to do so, subject to the following
516 + * conditions:
517 + *
518 + * The above copyright notice and this permission notice shall be
519 + * included in all copies or substantial portions of the Software.
520 + *
521 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
522 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
523 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
524 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
525 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
526 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
527 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
528 + * OTHER DEALINGS IN THE SOFTWARE.
529 + */
530 +
531 +#include <dt-bindings/thermal/thermal.h>
532 +
533 +/memreserve/ 0x80000000 0x00010000;
534 +
535 +/ {
536 + compatible = "fsl,ls2088a";
537 + interrupt-parent = <&gic>;
538 + #address-cells = <2>;
539 + #size-cells = <2>;
540 +
541 + cpus {
542 + #address-cells = <2>;
543 + #size-cells = <0>;
544 +
545 + cpu0: cpu@0 {
546 + device_type = "cpu";
547 + compatible = "arm,cortex-a72";
548 + reg = <0x0 0x0>;
549 + clocks = <&clockgen 1 0>;
550 + #cooling-cells = <2>;
551 + cpu-idle-states = <&CPU_PW20>;
552 + };
553 +
554 + cpu1: cpu@1 {
555 + device_type = "cpu";
556 + compatible = "arm,cortex-a72";
557 + reg = <0x0 0x1>;
558 + clocks = <&clockgen 1 0>;
559 + cpu-idle-states = <&CPU_PW20>;
560 + };
561 +
562 + cpu2: cpu@100 {
563 + device_type = "cpu";
564 + compatible = "arm,cortex-a72";
565 + reg = <0x0 0x100>;
566 + clocks = <&clockgen 1 1>;
567 + #cooling-cells = <2>;
568 + cpu-idle-states = <&CPU_PW20>;
569 + };
570 +
571 + cpu3: cpu@101 {
572 + device_type = "cpu";
573 + compatible = "arm,cortex-a72";
574 + reg = <0x0 0x101>;
575 + clocks = <&clockgen 1 1>;
576 + cpu-idle-states = <&CPU_PW20>;
577 + };
578 +
579 + cpu4: cpu@200 {
580 + device_type = "cpu";
581 + compatible = "arm,cortex-a72";
582 + reg = <0x0 0x200>;
583 + clocks = <&clockgen 1 2>;
584 + #cooling-cells = <2>;
585 + cpu-idle-states = <&CPU_PW20>;
586 + };
587 +
588 + cpu5: cpu@201 {
589 + device_type = "cpu";
590 + compatible = "arm,cortex-a72";
591 + reg = <0x0 0x201>;
592 + clocks = <&clockgen 1 2>;
593 + cpu-idle-states = <&CPU_PW20>;
594 + };
595 +
596 + cpu6: cpu@300 {
597 + device_type = "cpu";
598 + compatible = "arm,cortex-a72";
599 + reg = <0x0 0x300>;
600 + clocks = <&clockgen 1 3>;
601 + #cooling-cells = <2>;
602 + cpu-idle-states = <&CPU_PW20>;
603 + };
604 +
605 + cpu7: cpu@301 {
606 + device_type = "cpu";
607 + compatible = "arm,cortex-a72";
608 + reg = <0x0 0x301>;
609 + clocks = <&clockgen 1 3>;
610 + cpu-idle-states = <&CPU_PW20>;
611 + };
612 + };
613 +
614 + pmu {
615 + compatible = "arm,armv8-pmuv3";
616 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
617 + };
618 +
619 + idle-states {
620 + entry-method = "arm,psci";
621 +
622 + CPU_PW20: cpu-pw20 {
623 + compatible = "arm,idle-state";
624 + idle-state-name = "PW20";
625 + arm,psci-suspend-param = <0x00010000>;
626 + entry-latency-us = <2000>;
627 + exit-latency-us = <2000>;
628 + min-residency-us = <6000>;
629 + };
630 + };
631 +
632 + gic: interrupt-controller@6000000 {
633 + compatible = "arm,gic-v3";
634 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
635 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
636 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
637 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
638 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
639 + #interrupt-cells = <3>;
640 + #address-cells = <2>;
641 + #size-cells = <2>;
642 + ranges;
643 + interrupt-controller;
644 + interrupts = <1 9 0x4>;
645 +
646 + its: gic-its@6020000 {
647 + compatible = "arm,gic-v3-its";
648 + msi-controller;
649 + reg = <0x0 0x6020000 0 0x20000>;
650 + };
651 + };
652 +
653 + sysclk: sysclk {
654 + compatible = "fixed-clock";
655 + #clock-cells = <0>;
656 + clock-frequency = <100000000>;
657 + clock-output-names = "sysclk";
658 + };
659 +
660 + clockgen: clocking@1300000 {
661 + compatible = "fsl,ls2088a-clockgen";
662 + reg = <0 0x1300000 0 0xa0000>;
663 + #clock-cells = <2>;
664 + clocks = <&sysclk>;
665 + };
666 +
667 + tmu: tmu@1f80000 {
668 + compatible = "fsl,qoriq-tmu", "fsl,ls2080a-tmu", "fsl,ls2088a-tmu";
669 + reg = <0x0 0x1f80000 0x0 0x10000>;
670 + interrupts = <0 23 0x4>;
671 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
672 + fsl,tmu-calibration = <0x00000000 0x00000026
673 + 0x00000001 0x0000002d
674 + 0x00000002 0x00000032
675 + 0x00000003 0x00000039
676 + 0x00000004 0x0000003f
677 + 0x00000005 0x00000046
678 + 0x00000006 0x0000004d
679 + 0x00000007 0x00000054
680 + 0x00000008 0x0000005a
681 + 0x00000009 0x00000061
682 + 0x0000000a 0x0000006a
683 + 0x0000000b 0x00000071
684 +
685 + 0x00010000 0x00000025
686 + 0x00010001 0x0000002c
687 + 0x00010002 0x00000035
688 + 0x00010003 0x0000003d
689 + 0x00010004 0x00000045
690 + 0x00010005 0x0000004e
691 + 0x00010006 0x00000057
692 + 0x00010007 0x00000061
693 + 0x00010008 0x0000006b
694 + 0x00010009 0x00000076
695 +
696 + 0x00020000 0x00000029
697 + 0x00020001 0x00000033
698 + 0x00020002 0x0000003d
699 + 0x00020003 0x00000049
700 + 0x00020004 0x00000056
701 + 0x00020005 0x00000061
702 + 0x00020006 0x0000006d
703 +
704 + 0x00030000 0x00000021
705 + 0x00030001 0x0000002a
706 + 0x00030002 0x0000003c
707 + 0x00030003 0x0000004e>;
708 + little-endian;
709 + #thermal-sensor-cells = <1>;
710 + };
711 +
712 + thermal-zones {
713 + cpu_thermal: cpu-thermal {
714 + polling-delay-passive = <1000>;
715 + polling-delay = <5000>;
716 +
717 + thermal-sensors = <&tmu 4>;
718 +
719 + trips {
720 + cpu_alert: cpu-alert {
721 + temperature = <75000>;
722 + hysteresis = <2000>;
723 + type = "passive";
724 + };
725 + cpu_crit: cpu-crit {
726 + temperature = <85000>;
727 + hysteresis = <2000>;
728 + type = "critical";
729 + };
730 + };
731 +
732 + cooling-maps {
733 + map0 {
734 + trip = <&cpu_alert>;
735 + cooling-device =
736 + <&cpu0 THERMAL_NO_LIMIT
737 + THERMAL_NO_LIMIT>;
738 + };
739 + map1 {
740 + trip = <&cpu_alert>;
741 + cooling-device =
742 + <&cpu2 THERMAL_NO_LIMIT
743 + THERMAL_NO_LIMIT>;
744 + };
745 + map2 {
746 + trip = <&cpu_alert>;
747 + cooling-device =
748 + <&cpu4 THERMAL_NO_LIMIT
749 + THERMAL_NO_LIMIT>;
750 + };
751 + map3 {
752 + trip = <&cpu_alert>;
753 + cooling-device =
754 + <&cpu6 THERMAL_NO_LIMIT
755 + THERMAL_NO_LIMIT>;
756 + };
757 + };
758 + };
759 + };
760 +
761 + serial0: serial@21c0500 {
762 + device_type = "serial";
763 + compatible = "fsl,ns16550", "ns16550a";
764 + reg = <0x0 0x21c0500 0x0 0x100>;
765 + clocks = <&clockgen 4 3>;
766 + interrupts = <0 32 0x4>; /* Level high type */
767 + };
768 +
769 + serial1: serial@21c0600 {
770 + device_type = "serial";
771 + compatible = "fsl,ns16550", "ns16550a";
772 + reg = <0x0 0x21c0600 0x0 0x100>;
773 + clocks = <&clockgen 4 3>;
774 + interrupts = <0 32 0x4>; /* Level high type */
775 + };
776 + cluster1_core0_watchdog: wdt@c000000 {
777 + compatible = "arm,sp805-wdt", "arm,primecell";
778 + reg = <0x0 0xc000000 0x0 0x1000>;
779 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
780 + clock-names = "apb_pclk", "wdog_clk";
781 + };
782 +
783 + cluster1_core1_watchdog: wdt@c010000 {
784 + compatible = "arm,sp805-wdt", "arm,primecell";
785 + reg = <0x0 0xc010000 0x0 0x1000>;
786 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
787 + clock-names = "apb_pclk", "wdog_clk";
788 + };
789 +
790 + cluster2_core0_watchdog: wdt@c100000 {
791 + compatible = "arm,sp805-wdt", "arm,primecell";
792 + reg = <0x0 0xc100000 0x0 0x1000>;
793 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
794 + clock-names = "apb_pclk", "wdog_clk";
795 + };
796 +
797 + cluster2_core1_watchdog: wdt@c110000 {
798 + compatible = "arm,sp805-wdt", "arm,primecell";
799 + reg = <0x0 0xc110000 0x0 0x1000>;
800 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
801 + clock-names = "apb_pclk", "wdog_clk";
802 + };
803 +
804 + cluster3_core0_watchdog: wdt@c200000 {
805 + compatible = "arm,sp805-wdt", "arm,primecell";
806 + reg = <0x0 0xc200000 0x0 0x1000>;
807 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
808 + clock-names = "apb_pclk", "wdog_clk";
809 + };
810 +
811 + cluster3_core1_watchdog: wdt@c210000 {
812 + compatible = "arm,sp805-wdt", "arm,primecell";
813 + reg = <0x0 0xc210000 0x0 0x1000>;
814 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
815 + clock-names = "apb_pclk", "wdog_clk";
816 + };
817 +
818 + cluster4_core0_watchdog: wdt@c300000 {
819 + compatible = "arm,sp805-wdt", "arm,primecell";
820 + reg = <0x0 0xc300000 0x0 0x1000>;
821 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
822 + clock-names = "apb_pclk", "wdog_clk";
823 + };
824 +
825 + cluster4_core1_watchdog: wdt@c310000 {
826 + compatible = "arm,sp805-wdt", "arm,primecell";
827 + reg = <0x0 0xc310000 0x0 0x1000>;
828 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
829 + clock-names = "apb_pclk", "wdog_clk";
830 + };
831 +
832 + gpio0: gpio@2300000 {
833 + compatible = "fsl,qoriq-gpio";
834 + reg = <0x0 0x2300000 0x0 0x10000>;
835 + interrupts = <0 36 0x4>; /* Level high type */
836 + gpio-controller;
837 + little-endian;
838 + #gpio-cells = <2>;
839 + interrupt-controller;
840 + #interrupt-cells = <2>;
841 + };
842 +
843 + gpio1: gpio@2310000 {
844 + compatible = "fsl,qoriq-gpio";
845 + reg = <0x0 0x2310000 0x0 0x10000>;
846 + interrupts = <0 36 0x4>; /* Level high type */
847 + gpio-controller;
848 + little-endian;
849 + #gpio-cells = <2>;
850 + interrupt-controller;
851 + #interrupt-cells = <2>;
852 + };
853 +
854 + gpio2: gpio@2320000 {
855 + compatible = "fsl,qoriq-gpio";
856 + reg = <0x0 0x2320000 0x0 0x10000>;
857 + interrupts = <0 37 0x4>; /* Level high type */
858 + gpio-controller;
859 + little-endian;
860 + #gpio-cells = <2>;
861 + interrupt-controller;
862 + #interrupt-cells = <2>;
863 + };
864 +
865 + gpio3: gpio@2330000 {
866 + compatible = "fsl,qoriq-gpio";
867 + reg = <0x0 0x2330000 0x0 0x10000>;
868 + interrupts = <0 37 0x4>; /* Level high type */
869 + gpio-controller;
870 + little-endian;
871 + #gpio-cells = <2>;
872 + interrupt-controller;
873 + #interrupt-cells = <2>;
874 + };
875 +
876 + /* TODO: WRIOP (CCSR?) */
877 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
878 + compatible = "fsl,fman-memac-mdio";
879 + reg = <0x0 0x8B96000 0x0 0x1000>;
880 + device_type = "mdio"; /* TODO: is this necessary? */
881 + little-endian; /* force the driver in LE mode */
882 +
883 + /* Not necessary on the QDS, but needed on the RDB */
884 + #address-cells = <1>;
885 + #size-cells = <0>;
886 + };
887 +
888 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
889 + compatible = "fsl,fman-memac-mdio";
890 + reg = <0x0 0x8B97000 0x0 0x1000>;
891 + device_type = "mdio"; /* TODO: is this necessary? */
892 + little-endian; /* force the driver in LE mode */
893 +
894 + #address-cells = <1>;
895 + #size-cells = <0>;
896 + };
897 +
898 + ifc: ifc@2240000 {
899 + compatible = "fsl,ifc", "simple-bus";
900 + reg = <0x0 0x2240000 0x0 0x20000>;
901 + interrupts = <0 21 0x4>; /* Level high type */
902 + little-endian;
903 + #address-cells = <2>;
904 + #size-cells = <1>;
905 +
906 + ranges = <0 0 0x5 0x80000000 0x08000000
907 + 2 0 0x5 0x30000000 0x00010000
908 + 3 0 0x5 0x20000000 0x00010000>;
909 + };
910 +
911 + esdhc: esdhc@2140000 {
912 + compatible = "fsl,ls2088a-esdhc", "fsl,ls2080a-esdhc",
913 + "fsl,esdhc";
914 + reg = <0x0 0x2140000 0x0 0x10000>;
915 + interrupts = <0 28 0x4>; /* Level high type */
916 + clock-frequency = <0>;
917 + voltage-ranges = <1800 1800 3300 3300>;
918 + sdhci,auto-cmd12;
919 + little-endian;
920 + bus-width = <4>;
921 + };
922 +
923 + ftm0: ftm0@2800000 {
924 + compatible = "fsl,ftm-alarm";
925 + reg = <0x0 0x2800000 0x0 0x10000>;
926 + interrupts = <0 44 4>;
927 + };
928 +
929 + reset: reset@1E60000 {
930 + compatible = "fsl,ls-reset";
931 + reg = <0x0 0x1E60000 0x0 0x10000>;
932 + };
933 +
934 + dspi: dspi@2100000 {
935 + compatible = "fsl,ls2088a-dspi", "fsl,ls2085a-dspi",
936 + "fsl,ls2080a-dspi";
937 + #address-cells = <1>;
938 + #size-cells = <0>;
939 + reg = <0x0 0x2100000 0x0 0x10000>;
940 + interrupts = <0 26 0x4>; /* Level high type */
941 + clocks = <&clockgen 4 3>;
942 + clock-names = "dspi";
943 + spi-num-chipselects = <5>;
944 + bus-num = <0>;
945 + };
946 +
947 + i2c0: i2c@2000000 {
948 + compatible = "fsl,vf610-i2c";
949 + #address-cells = <1>;
950 + #size-cells = <0>;
951 + reg = <0x0 0x2000000 0x0 0x10000>;
952 + interrupts = <0 34 0x4>; /* Level high type */
953 + clock-names = "i2c";
954 + clocks = <&clockgen 4 3>;
955 + };
956 +
957 + i2c1: i2c@2010000 {
958 + compatible = "fsl,vf610-i2c";
959 + #address-cells = <1>;
960 + #size-cells = <0>;
961 + reg = <0x0 0x2010000 0x0 0x10000>;
962 + interrupts = <0 34 0x4>; /* Level high type */
963 + clock-names = "i2c";
964 + clocks = <&clockgen 4 3>;
965 + };
966 +
967 + i2c2: i2c@2020000 {
968 + compatible = "fsl,vf610-i2c";
969 + #address-cells = <1>;
970 + #size-cells = <0>;
971 + reg = <0x0 0x2020000 0x0 0x10000>;
972 + interrupts = <0 35 0x4>; /* Level high type */
973 + clock-names = "i2c";
974 + clocks = <&clockgen 4 3>;
975 + };
976 +
977 + i2c3: i2c@2030000 {
978 + compatible = "fsl,vf610-i2c";
979 + #address-cells = <1>;
980 + #size-cells = <0>;
981 + reg = <0x0 0x2030000 0x0 0x10000>;
982 + interrupts = <0 35 0x4>; /* Level high type */
983 + clock-names = "i2c";
984 + clocks = <&clockgen 4 3>;
985 + };
986 +
987 + qspi: quadspi@20c0000 {
988 + compatible = "fsl,ls2088a-qspi", "fsl,ls2080a-qspi";
989 + #address-cells = <1>;
990 + #size-cells = <0>;
991 + reg = <0x0 0x20c0000 0x0 0x10000>,
992 + <0x0 0x20000000 0x0 0x10000000>;
993 + reg-names = "QuadSPI", "QuadSPI-memory";
994 + interrupts = <0 25 0x4>; /* Level high type */
995 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
996 + clock-names = "qspi_en", "qspi";
997 + };
998 +
999 + pcie1: pcie@3400000 {
1000 + compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
1001 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1002 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
1003 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
1004 + reg-names = "regs", "config";
1005 + interrupts = <0 108 0x4>; /* Level high type */
1006 + interrupt-names = "aer";
1007 + #address-cells = <3>;
1008 + #size-cells = <2>;
1009 + device_type = "pci";
1010 + dma-coherent;
1011 + fsl,lut_diff;
1012 + num-lanes = <4>;
1013 + bus-range = <0x0 0xff>;
1014 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
1015 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1016 + msi-parent = <&its>;
1017 + #interrupt-cells = <1>;
1018 + interrupt-map-mask = <0 0 0 7>;
1019 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1020 + <0000 0 0 2 &gic 0 0 0 110 4>,
1021 + <0000 0 0 3 &gic 0 0 0 111 4>,
1022 + <0000 0 0 4 &gic 0 0 0 112 4>;
1023 + };
1024 +
1025 + pcie2: pcie@3500000 {
1026 + compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
1027 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1028 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
1029 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
1030 + reg-names = "regs", "config";
1031 + interrupts = <0 113 0x4>; /* Level high type */
1032 + interrupt-names = "aer";
1033 + #address-cells = <3>;
1034 + #size-cells = <2>;
1035 + device_type = "pci";
1036 + dma-coherent;
1037 + fsl,lut_diff;
1038 + num-lanes = <4>;
1039 + bus-range = <0x0 0xff>;
1040 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
1041 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1042 + msi-parent = <&its>;
1043 + #interrupt-cells = <1>;
1044 + interrupt-map-mask = <0 0 0 7>;
1045 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1046 + <0000 0 0 2 &gic 0 0 0 115 4>,
1047 + <0000 0 0 3 &gic 0 0 0 116 4>,
1048 + <0000 0 0 4 &gic 0 0 0 117 4>;
1049 + };
1050 +
1051 + pcie3: pcie@3600000 {
1052 + compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
1053 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1054 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
1055 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
1056 + reg-names = "regs", "config";
1057 + interrupts = <0 118 0x4>; /* Level high type */
1058 + interrupt-names = "aer";
1059 + #address-cells = <3>;
1060 + #size-cells = <2>;
1061 + device_type = "pci";
1062 + dma-coherent;
1063 + fsl,lut_diff;
1064 + num-lanes = <8>;
1065 + bus-range = <0x0 0xff>;
1066 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
1067 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1068 + msi-parent = <&its>;
1069 + #interrupt-cells = <1>;
1070 + interrupt-map-mask = <0 0 0 7>;
1071 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1072 + <0000 0 0 2 &gic 0 0 0 120 4>,
1073 + <0000 0 0 3 &gic 0 0 0 121 4>,
1074 + <0000 0 0 4 &gic 0 0 0 122 4>;
1075 + };
1076 +
1077 + pcie4: pcie@3700000 {
1078 + compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
1079 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1080 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
1081 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
1082 + reg-names = "regs", "config";
1083 + interrupts = <0 123 0x4>; /* Level high type */
1084 + interrupt-names = "aer";
1085 + #address-cells = <3>;
1086 + #size-cells = <2>;
1087 + device_type = "pci";
1088 + dma-coherent;
1089 + fsl,lut_diff;
1090 + num-lanes = <4>;
1091 + bus-range = <0x0 0xff>;
1092 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 /* downstream I/O */
1093 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1094 + msi-parent = <&its>;
1095 + #interrupt-cells = <1>;
1096 + interrupt-map-mask = <0 0 0 7>;
1097 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1098 + <0000 0 0 2 &gic 0 0 0 125 4>,
1099 + <0000 0 0 3 &gic 0 0 0 126 4>,
1100 + <0000 0 0 4 &gic 0 0 0 127 4>;
1101 + };
1102 +
1103 + sata0: sata@3200000 {
1104 + status = "disabled";
1105 + compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
1106 + reg = <0x0 0x3200000 0x0 0x10000>;
1107 + interrupts = <0 133 0x4>; /* Level high type */
1108 + clocks = <&clockgen 4 3>;
1109 + };
1110 +
1111 + sata1: sata@3210000 {
1112 + status = "disabled";
1113 + compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
1114 + reg = <0x0 0x3210000 0x0 0x10000>;
1115 + interrupts = <0 136 0x4>; /* Level high type */
1116 + clocks = <&clockgen 4 3>;
1117 + };
1118 +
1119 + usb0: usb3@3100000 {
1120 + status = "disabled";
1121 + compatible = "snps,dwc3";
1122 + reg = <0x0 0x3100000 0x0 0x10000>;
1123 + interrupts = <0 80 0x4>; /* Level high type */
1124 + dr_mode = "host";
1125 + configure-gfladj;
1126 + snps,dis_rxdet_inp3_quirk;
1127 + };
1128 +
1129 + usb1: usb3@3110000 {
1130 + status = "disabled";
1131 + compatible = "snps,dwc3";
1132 + reg = <0x0 0x3110000 0x0 0x10000>;
1133 + interrupts = <0 81 0x4>; /* Level high type */
1134 + dr_mode = "host";
1135 + configure-gfladj;
1136 + snps,dis_rxdet_inp3_quirk;
1137 + };
1138 +
1139 + smmu: iommu@5000000 {
1140 + compatible = "arm,mmu-500";
1141 + reg = <0 0x5000000 0 0x800000>;
1142 + #global-interrupts = <12>;
1143 + interrupts = <0 13 4>, /* global secure fault */
1144 + <0 14 4>, /* combined secure interrupt */
1145 + <0 15 4>, /* global non-secure fault */
1146 + <0 16 4>, /* combined non-secure interrupt */
1147 + /* performance counter interrupts 0-7 */
1148 + <0 211 4>,
1149 + <0 212 4>,
1150 + <0 213 4>,
1151 + <0 214 4>,
1152 + <0 215 4>,
1153 + <0 216 4>,
1154 + <0 217 4>,
1155 + <0 218 4>,
1156 + /* per context interrupt, 64 interrupts */
1157 + <0 146 4>,
1158 + <0 147 4>,
1159 + <0 148 4>,
1160 + <0 149 4>,
1161 + <0 150 4>,
1162 + <0 151 4>,
1163 + <0 152 4>,
1164 + <0 153 4>,
1165 + <0 154 4>,
1166 + <0 155 4>,
1167 + <0 156 4>,
1168 + <0 157 4>,
1169 + <0 158 4>,
1170 + <0 159 4>,
1171 + <0 160 4>,
1172 + <0 161 4>,
1173 + <0 162 4>,
1174 + <0 163 4>,
1175 + <0 164 4>,
1176 + <0 165 4>,
1177 + <0 166 4>,
1178 + <0 167 4>,
1179 + <0 168 4>,
1180 + <0 169 4>,
1181 + <0 170 4>,
1182 + <0 171 4>,
1183 + <0 172 4>,
1184 + <0 173 4>,
1185 + <0 174 4>,
1186 + <0 175 4>,
1187 + <0 176 4>,
1188 + <0 177 4>,
1189 + <0 178 4>,
1190 + <0 179 4>,
1191 + <0 180 4>,
1192 + <0 181 4>,
1193 + <0 182 4>,
1194 + <0 183 4>,
1195 + <0 184 4>,
1196 + <0 185 4>,
1197 + <0 186 4>,
1198 + <0 187 4>,
1199 + <0 188 4>,
1200 + <0 189 4>,
1201 + <0 190 4>,
1202 + <0 191 4>,
1203 + <0 192 4>,
1204 + <0 193 4>,
1205 + <0 194 4>,
1206 + <0 195 4>,
1207 + <0 196 4>,
1208 + <0 197 4>,
1209 + <0 198 4>,
1210 + <0 199 4>,
1211 + <0 200 4>,
1212 + <0 201 4>,
1213 + <0 202 4>,
1214 + <0 203 4>,
1215 + <0 204 4>,
1216 + <0 205 4>,
1217 + <0 206 4>,
1218 + <0 207 4>,
1219 + <0 208 4>,
1220 + <0 209 4>;
1221 + mmu-masters = <&fsl_mc 0x300 0>;
1222 + };
1223 +
1224 + timer {
1225 + compatible = "arm,armv8-timer";
1226 + interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */
1227 + <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */
1228 + <1 11 0x1>, /* Virtual PPI, edge triggered */
1229 + <1 10 0x1>; /* Hypervisor PPI, edge triggered */
1230 + arm,reread-timer;
1231 + fsl,erratum-a008585;
1232 + };
1233 +
1234 + fsl_mc: fsl-mc@80c000000 {
1235 + compatible = "fsl,qoriq-mc";
1236 + #stream-id-cells = <2>;
1237 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
1238 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
1239 + msi-parent = <&its>;
1240 + #address-cells = <3>;
1241 + #size-cells = <1>;
1242 +
1243 + /*
1244 + * Region type 0x0 - MC portals
1245 + * Region type 0x1 - QBMAN portals
1246 + */
1247 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1248 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1249 +
1250 + /*
1251 + * Define the maximum number of MACs present on the SoC.
1252 + * They won't necessarily be all probed, since the
1253 + * Data Path Layout file and the MC firmware can put fewer
1254 + * actual DPMAC objects on the MC bus.
1255 + */
1256 + dpmacs {
1257 + #address-cells = <1>;
1258 + #size-cells = <0>;
1259 +
1260 + dpmac1: dpmac@1 {
1261 + compatible = "fsl,qoriq-mc-dpmac";
1262 + reg = <1>;
1263 + };
1264 + dpmac2: dpmac@2 {
1265 + compatible = "fsl,qoriq-mc-dpmac";
1266 + reg = <2>;
1267 + };
1268 + dpmac3: dpmac@3 {
1269 + compatible = "fsl,qoriq-mc-dpmac";
1270 + reg = <3>;
1271 + };
1272 + dpmac4: dpmac@4 {
1273 + compatible = "fsl,qoriq-mc-dpmac";
1274 + reg = <4>;
1275 + };
1276 + dpmac5: dpmac@5 {
1277 + compatible = "fsl,qoriq-mc-dpmac";
1278 + reg = <5>;
1279 + };
1280 + dpmac6: dpmac@6 {
1281 + compatible = "fsl,qoriq-mc-dpmac";
1282 + reg = <6>;
1283 + };
1284 + dpmac7: dpmac@7 {
1285 + compatible = "fsl,qoriq-mc-dpmac";
1286 + reg = <7>;
1287 + };
1288 + dpmac8: dpmac@8 {
1289 + compatible = "fsl,qoriq-mc-dpmac";
1290 + reg = <8>;
1291 + };
1292 + dpmac9: dpmac@9 {
1293 + compatible = "fsl,qoriq-mc-dpmac";
1294 + reg = <9>;
1295 + };
1296 + dpmac10: dpmac@10 {
1297 + compatible = "fsl,qoriq-mc-dpmac";
1298 + reg = <0xa>;
1299 + };
1300 + dpmac11: dpmac@11 {
1301 + compatible = "fsl,qoriq-mc-dpmac";
1302 + reg = <0xb>;
1303 + };
1304 + dpmac12: dpmac@12 {
1305 + compatible = "fsl,qoriq-mc-dpmac";
1306 + reg = <0xc>;
1307 + };
1308 + dpmac13: dpmac@13 {
1309 + compatible = "fsl,qoriq-mc-dpmac";
1310 + reg = <0xd>;
1311 + };
1312 + dpmac14: dpmac@14 {
1313 + compatible = "fsl,qoriq-mc-dpmac";
1314 + reg = <0xe>;
1315 + };
1316 + dpmac15: dpmac@15 {
1317 + compatible = "fsl,qoriq-mc-dpmac";
1318 + reg = <0xf>;
1319 + };
1320 + dpmac16: dpmac@16 {
1321 + compatible = "fsl,qoriq-mc-dpmac";
1322 + reg = <0x10>;
1323 + };
1324 + };
1325 + };
1326 +
1327 + ccn@4000000 {
1328 + compatible = "arm,ccn-504";
1329 + reg = <0x0 0x04000000 0x0 0x01000000>;
1330 + interrupts = <0 12 4>;
1331 + };
1332 +
1333 + memory@80000000 {
1334 + device_type = "memory";
1335 + reg = <0x00000000 0x80000000 0 0x80000000>;
1336 + /* DRAM space 1 - 2 GB DRAM */
1337 + };
1338 +};
lynxis staging tree