target/linux/brcm2708/patches-4.19/950-0404-ASoC-tlv320aic32x4-Model-DAC-ADC-dividers-in-CCF.patch

   1 From c4c080628e85c7860986c64a7a0b7f56a521fef6 Mon Sep 17 00:00:00 2001
   2 From: Annaliese McDermond <nh6z@nh6z.net>
   3 Date: Thu, 21 Mar 2019 17:58:47 -0700
   4 Subject: [PATCH 404/725] ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCF
   5
   6 commit a51b50062091619915c5155085bbe13a7aca6903 upstream.
   7
   8 Model and manage DAC/ADC dividers as components in the Core
   9 Clock Framework.  This should allow us to do some more complex
  10 clock management and power control.  Also, some of the
  11 on-board chip clocks can be exposed to the outside, and this
  12 change will make those clocks easier to consume by other
  13 parts of the kernel.
  14
  15 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
  16 Signed-off-by: Mark Brown <broonie@kernel.org>
  17 ---
  18  sound/soc/codecs/tlv320aic32x4-clk.c |  90 ++++++++++++++++++++++++
  19  sound/soc/codecs/tlv320aic32x4.c     | 101 +++++++++++++++------------
  20  sound/soc/codecs/tlv320aic32x4.h     |   4 ++
  21  3 files changed, 151 insertions(+), 44 deletions(-)
  22
  23 --- a/sound/soc/codecs/tlv320aic32x4-clk.c
  24 +++ b/sound/soc/codecs/tlv320aic32x4-clk.c
  25 @@ -289,6 +289,68 @@ static const struct clk_ops aic32x4_code
  26         .get_parent = clk_aic32x4_codec_clkin_get_parent,
  27  };
  28
  29 +static int clk_aic32x4_div_prepare(struct clk_hw *hw)
  30 +{
  31 +       struct clk_aic32x4 *div = to_clk_aic32x4(hw);
  32 +
  33 +       return regmap_update_bits(div->regmap, div->reg,
  34 +                               AIC32X4_DIVEN, AIC32X4_DIVEN);
  35 +}
  36 +
  37 +static void clk_aic32x4_div_unprepare(struct clk_hw *hw)
  38 +{
  39 +       struct clk_aic32x4 *div = to_clk_aic32x4(hw);
  40 +
  41 +       regmap_update_bits(div->regmap, div->reg,
  42 +                       AIC32X4_DIVEN, 0);
  43 +}
  44 +
  45 +static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate,
  46 +                               unsigned long parent_rate)
  47 +{
  48 +       struct clk_aic32x4 *div = to_clk_aic32x4(hw);
  49 +       u8 divisor;
  50 +
  51 +       divisor = DIV_ROUND_UP(parent_rate, rate);
  52 +       if (divisor > 128)
  53 +               return -EINVAL;
  54 +
  55 +       return regmap_update_bits(div->regmap, div->reg,
  56 +                               AIC32X4_DIV_MASK, divisor);
  57 +}
  58 +
  59 +static long clk_aic32x4_div_round_rate(struct clk_hw *hw, unsigned long rate,
  60 +                               unsigned long *parent_rate)
  61 +{
  62 +       unsigned long divisor;
  63 +
  64 +       divisor = DIV_ROUND_UP(*parent_rate, rate);
  65 +       if (divisor > 128)
  66 +               return -EINVAL;
  67 +
  68 +       return DIV_ROUND_UP(*parent_rate, divisor);
  69 +}
  70 +
  71 +static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw,
  72 +                                               unsigned long parent_rate)
  73 +{
  74 +       struct clk_aic32x4 *div = to_clk_aic32x4(hw);
  75 +
  76 +       unsigned int val;
  77 +
  78 +       regmap_read(div->regmap, div->reg, &val);
  79 +
  80 +       return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK);
  81 +}
  82 +
  83 +static const struct clk_ops aic32x4_div_ops = {
  84 +       .prepare = clk_aic32x4_div_prepare,
  85 +       .unprepare = clk_aic32x4_div_unprepare,
  86 +       .set_rate = clk_aic32x4_div_set_rate,
  87 +       .round_rate = clk_aic32x4_div_round_rate,
  88 +       .recalc_rate = clk_aic32x4_div_recalc_rate,
  89 +};
  90 +
  91  static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
  92         {
  93                 .name = "pll",
  94 @@ -306,6 +368,34 @@ static struct aic32x4_clkdesc aic32x4_cl
  95                 .ops = &aic32x4_codec_clkin_ops,
  96                 .reg = 0,
  97         },
  98 +       {
  99 +               .name = "ndac",
 100 +               .parent_names = (const char * []) { "codec_clkin" },
 101 +               .num_parents = 1,
 102 +               .ops = &aic32x4_div_ops,
 103 +               .reg = AIC32X4_NDAC,
 104 +       },
 105 +       {
 106 +               .name = "mdac",
 107 +               .parent_names = (const char * []) { "ndac" },
 108 +               .num_parents = 1,
 109 +               .ops = &aic32x4_div_ops,
 110 +               .reg = AIC32X4_MDAC,
 111 +       },
 112 +       {
 113 +               .name = "nadc",
 114 +               .parent_names = (const char * []) { "codec_clkin" },
 115 +               .num_parents = 1,
 116 +               .ops = &aic32x4_div_ops,
 117 +               .reg = AIC32X4_NADC,
 118 +       },
 119 +       {
 120 +               .name = "madc",
 121 +               .parent_names = (const char * []) { "nadc" },
 122 +               .num_parents = 1,
 123 +               .ops = &aic32x4_div_ops,
 124 +               .reg = AIC32X4_MADC,
 125 +       },
 126  };
 127
 128  static struct clk *aic32x4_register_clk(struct device *dev,
 129 --- a/sound/soc/codecs/tlv320aic32x4.c
 130 +++ b/sound/soc/codecs/tlv320aic32x4.c
 131 @@ -52,11 +52,11 @@ struct aic32x4_rate_divs {
 132         u32 rate;
 133         unsigned long pll_rate;
 134         u16 dosr;
 135 -       u8 ndac;
 136 -       u8 mdac;
 137 +       unsigned long ndac_rate;
 138 +       unsigned long mdac_rate;
 139         u8 aosr;
 140 -       u8 nadc;
 141 -       u8 madc;
 142 +       unsigned long nadc_rate;
 143 +       unsigned long madc_rate;
 144         u8 blck_N;
 145         u8 r_block;
 146         u8 p_block;
 147 @@ -309,34 +309,54 @@ static const struct snd_kcontrol_new aic
 148
 149  static const struct aic32x4_rate_divs aic32x4_divs[] = {
 150         /* 8k rate */
 151 -       { 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 },
 152 -       { 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
 153 -       { 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
 154 +       { 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000,
 155 +               1024000, 24, 1, 1 },
 156 +       { 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000,
 157 +               512000, 24, 1, 1 },
 158 +       { 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000,
 159 +               512000, 24, 1, 1 },
 160         /* 11.025k rate */
 161 -       { 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 },
 162 -       { 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 },
 163 +       { 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600,
 164 +               1411200, 16, 1, 1 },
 165 +       { 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400,
 166 +               705600, 16, 1, 1 },
 167         /* 16k rate */
 168 -       { 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 },
 169 -       { 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
 170 -       { 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
 171 +       { 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000,
 172 +               2048000, 12, 1, 1 },
 173 +       { 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000,
 174 +               1024000, 12, 1, 1 },
 175 +       { 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000,
 176 +               1024000, 12, 1, 1 },
 177         /* 22.05k rate */
 178 -       { 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 },
 179 -       { 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
 180 -       { 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
 181 +       { 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200,
 182 +               2822400, 8, 1, 1 },
 183 +       { 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800,
 184 +               1411200, 8, 1, 1 },
 185 +       { 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800,
 186 +               1411200, 8, 1, 1 },
 187         /* 32k rate */
 188 -       { 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 },
 189 -       { 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 },
 190 +       { 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000,
 191 +               2048000, 6, 1, 1 },
 192 +       { 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000,
 193 +               2048000, 6, 1, 1 },
 194         /* 44.1k rate */
 195 -       { 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
 196 -       { 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
 197 -       { 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
 198 +       { 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400,
 199 +               5644800, 4, 1, 1 },
 200 +       { 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600,
 201 +               2822400, 4, 1, 1 },
 202 +       { 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600,
 203 +               2822400, 4, 1, 1 },
 204         /* 48k rate */
 205 -       { 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
 206 -       { 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
 207 -       { 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
 208 +       { 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000,
 209 +               6144000, 4, 1, 1 },
 210 +       { 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000,
 211 +               3072000, 4, 1, 1 },
 212 +       { 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000,
 213 +               3072000, 4, 1, 1 },
 214
 215         /* 96k rate */
 216 -       { 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 },
 217 +       { 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000,
 218 +               6144000, 1, 1, 9 },
 219  };
 220
 221  static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 222 @@ -721,6 +741,10 @@ static int aic32x4_setup_clocks(struct s
 223
 224         struct clk_bulk_data clocks[] = {
 225                 { .id = "pll" },
 226 +               { .id = "nadc" },
 227 +               { .id = "madc" },
 228 +               { .id = "ndac" },
 229 +               { .id = "mdac" },
 230         };
 231
 232         i = aic32x4_get_divs(parent_rate, sample_rate);
 233 @@ -733,7 +757,11 @@ static int aic32x4_setup_clocks(struct s
 234         if (ret)
 235                 return ret;
 236
 237 -       clk_set_rate(clocks[0].clk, sample_rate);
 238 +       clk_set_rate(clocks[0].clk, aic32x4_divs[i].pll_rate);
 239 +       clk_set_rate(clocks[1].clk, aic32x4_divs[i].nadc_rate);
 240 +       clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate);
 241 +       clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate);
 242 +       clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate);
 243
 244         aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
 245
 246 @@ -742,26 +770,10 @@ static int aic32x4_setup_clocks(struct s
 247                                 AIC32X4_BDIVCLK_MASK,
 248                                 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
 249
 250 -       /* NDAC divider value */
 251 -       snd_soc_component_update_bits(component, AIC32X4_NDAC,
 252 -                               AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
 253 -
 254 -       /* MDAC divider value */
 255 -       snd_soc_component_update_bits(component, AIC32X4_MDAC,
 256 -                               AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
 257 -
 258         /* DOSR MSB & LSB values */
 259         snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
 260         snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
 261
 262 -       /* NADC divider value */
 263 -       snd_soc_component_update_bits(component, AIC32X4_NADC,
 264 -                               AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
 265 -
 266 -       /* MADC divider value */
 267 -       snd_soc_component_update_bits(component, AIC32X4_MADC,
 268 -                               AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
 269 -
 270         /* AOSR value */
 271         snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
 272
 273 @@ -773,8 +785,8 @@ static int aic32x4_setup_clocks(struct s
 274  }
 275
 276  static int aic32x4_hw_params(struct snd_pcm_substream *substream,
 277 -                            struct snd_pcm_hw_params *params,
 278 -                            struct snd_soc_dai *dai)
 279 +                                struct snd_pcm_hw_params *params,
 280 +                                struct snd_soc_dai *dai)
 281  {
 282         struct snd_soc_component *component = dai->component;
 283         struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 284 @@ -989,7 +1001,8 @@ static int aic32x4_component_probe(struc
 285         int ret;
 286
 287         struct clk_bulk_data clocks[] = {
 288 -           { .id = "codec_clkin" },
 289 +               { .id = "codec_clkin" },
 290 +               { .id = "pll" },
 291         };
 292
 293         ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
 294 --- a/sound/soc/codecs/tlv320aic32x4.h
 295 +++ b/sound/soc/codecs/tlv320aic32x4.h
 296 @@ -206,6 +206,10 @@ int aic32x4_register_clocks(struct devic
 297  #define AIC32X4_RMICPGANIN_IN1L_10K    0x10
 298  #define AIC32X4_RMICPGANIN_CM1R_10K    0x40
 299
 300 +/* Common mask and enable for all of the dividers */
 301 +#define AIC32X4_DIVEN           BIT(7)
 302 +#define AIC32X4_DIV_MASK        GENMASK(6, 0)
 303 +
 304  /* Clock Limits */
 305  #define AIC32X4_MAX_PLL_CLKIN          20000000
 306