target/linux/generic/backport-5.4/807-v5.8-i2c-pxa-re-arrange-register-field-definitions.patch

   1 From: Russell King <rmk+kernel@armlinux.org.uk>
   2 Bcc: linux@mail.armlinux.org.uk
   3 Cc: linux-i2c@vger.kernel.org
   4 Subject: [PATCH 05/17] i2c: pxa: re-arrange register field definitions
   5 MIME-Version: 1.0
   6 Content-Disposition: inline
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   8 Content-Type: text/plain; charset="utf-8"
   9
  10 Arrange the register field definitions to be grouped together, rather
  11 than the Armada-3700 definitions being separated from the rest of the
  12 definitions.
  13
  14 Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
  15 ---
  16  drivers/i2c/busses/i2c-pxa.c | 113 ++++++++++++++++-------------------
  17  1 file changed, 53 insertions(+), 60 deletions(-)
  18
  19 diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
  20 index e5f00ae39861..ea96dfa6b9d5 100644
  21 --- a/drivers/i2c/busses/i2c-pxa.c
  22 +++ b/drivers/i2c/busses/i2c-pxa.c
  23 @@ -33,6 +33,56 @@
  24  #include <linux/platform_data/i2c-pxa.h>
  25  #include <linux/slab.h>
  26
  27 +/* I2C register field definitions */
  28 +#define ICR_START      (1 << 0)           /* start bit */
  29 +#define ICR_STOP       (1 << 1)           /* stop bit */
  30 +#define ICR_ACKNAK     (1 << 2)           /* send ACK(0) or NAK(1) */
  31 +#define ICR_TB         (1 << 3)           /* transfer byte bit */
  32 +#define ICR_MA         (1 << 4)           /* master abort */
  33 +#define ICR_SCLE       (1 << 5)           /* master clock enable */
  34 +#define ICR_IUE                (1 << 6)           /* unit enable */
  35 +#define ICR_GCD                (1 << 7)           /* general call disable */
  36 +#define ICR_ITEIE      (1 << 8)           /* enable tx interrupts */
  37 +#define ICR_IRFIE      (1 << 9)           /* enable rx interrupts */
  38 +#define ICR_BEIE       (1 << 10)          /* enable bus error ints */
  39 +#define ICR_SSDIE      (1 << 11)          /* slave STOP detected int enable */
  40 +#define ICR_ALDIE      (1 << 12)          /* enable arbitration interrupt */
  41 +#define ICR_SADIE      (1 << 13)          /* slave address detected int enable */
  42 +#define ICR_UR         (1 << 14)          /* unit reset */
  43 +#define ICR_FM         (1 << 15)          /* fast mode */
  44 +#define ICR_HS         (1 << 16)          /* High Speed mode */
  45 +#define ICR_A3700_FM   (1 << 16)          /* fast mode for armada-3700 */
  46 +#define ICR_A3700_HS   (1 << 17)          /* high speed mode for armada-3700 */
  47 +#define ICR_GPIOEN     (1 << 19)          /* enable GPIO mode for SCL in HS */
  48 +
  49 +#define ISR_RWM                (1 << 0)           /* read/write mode */
  50 +#define ISR_ACKNAK     (1 << 1)           /* ack/nak status */
  51 +#define ISR_UB         (1 << 2)           /* unit busy */
  52 +#define ISR_IBB                (1 << 3)           /* bus busy */
  53 +#define ISR_SSD                (1 << 4)           /* slave stop detected */
  54 +#define ISR_ALD                (1 << 5)           /* arbitration loss detected */
  55 +#define ISR_ITE                (1 << 6)           /* tx buffer empty */
  56 +#define ISR_IRF                (1 << 7)           /* rx buffer full */
  57 +#define ISR_GCAD       (1 << 8)           /* general call address detected */
  58 +#define ISR_SAD                (1 << 9)           /* slave address detected */
  59 +#define ISR_BED                (1 << 10)          /* bus error no ACK/NAK */
  60 +
  61 +#define ILCR_SLV_SHIFT         0
  62 +#define ILCR_SLV_MASK          (0x1FF << ILCR_SLV_SHIFT)
  63 +#define ILCR_FLV_SHIFT         9
  64 +#define ILCR_FLV_MASK          (0x1FF << ILCR_FLV_SHIFT)
  65 +#define ILCR_HLVL_SHIFT                18
  66 +#define ILCR_HLVL_MASK         (0x1FF << ILCR_HLVL_SHIFT)
  67 +#define ILCR_HLVH_SHIFT                27
  68 +#define ILCR_HLVH_MASK         (0x1F << ILCR_HLVH_SHIFT)
  69 +
  70 +#define IWCR_CNT_SHIFT         0
  71 +#define IWCR_CNT_MASK          (0x1F << IWCR_CNT_SHIFT)
  72 +#define IWCR_HS_CNT1_SHIFT     5
  73 +#define IWCR_HS_CNT1_MASK      (0x1F << IWCR_HS_CNT1_SHIFT)
  74 +#define IWCR_HS_CNT2_SHIFT     10
  75 +#define IWCR_HS_CNT2_MASK      (0x1F << IWCR_HS_CNT2_SHIFT)
  76 +
  77  struct pxa_reg_layout {
  78         u32 ibmr;
  79         u32 idbr;
  80 @@ -53,12 +103,7 @@ enum pxa_i2c_types {
  81         REGS_A3700,
  82  };
  83
  84 -#define ICR_BUSMODE_FM (1 << 16)          /* shifted fast mode for armada-3700 */
  85 -#define ICR_BUSMODE_HS (1 << 17)          /* shifted high speed mode for armada-3700 */
  86 -
  87 -/*
  88 - * I2C registers definitions
  89 - */
  90 +/* I2C register layout definitions */
  91  static struct pxa_reg_layout pxa_reg_layout[] = {
  92         [REGS_PXA2XX] = {
  93                 .ibmr = 0x00,
  94 @@ -96,8 +141,8 @@ static struct pxa_reg_layout pxa_reg_layout[] = {
  95                 .icr =  0x08,
  96                 .isr =  0x0c,
  97                 .isar = 0x10,
  98 -               .fm = ICR_BUSMODE_FM,
  99 -               .hs = ICR_BUSMODE_HS,
 100 +               .fm = ICR_A3700_FM,
 101 +               .hs = ICR_A3700_HS,
 102         },
 103  };
 104
 105 @@ -111,58 +156,6 @@ static const struct platform_device_id i2c_pxa_id_table[] = {
 106  };
 107  MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
 108
 109 -/*
 110 - * I2C bit definitions
 111 - */
 112 -
 113 -#define ICR_START      (1 << 0)           /* start bit */
 114 -#define ICR_STOP       (1 << 1)           /* stop bit */
 115 -#define ICR_ACKNAK     (1 << 2)           /* send ACK(0) or NAK(1) */
 116 -#define ICR_TB         (1 << 3)           /* transfer byte bit */
 117 -#define ICR_MA         (1 << 4)           /* master abort */
 118 -#define ICR_SCLE       (1 << 5)           /* master clock enable */
 119 -#define ICR_IUE                (1 << 6)           /* unit enable */
 120 -#define ICR_GCD                (1 << 7)           /* general call disable */
 121 -#define ICR_ITEIE      (1 << 8)           /* enable tx interrupts */
 122 -#define ICR_IRFIE      (1 << 9)           /* enable rx interrupts */
 123 -#define ICR_BEIE       (1 << 10)          /* enable bus error ints */
 124 -#define ICR_SSDIE      (1 << 11)          /* slave STOP detected int enable */
 125 -#define ICR_ALDIE      (1 << 12)          /* enable arbitration interrupt */
 126 -#define ICR_SADIE      (1 << 13)          /* slave address detected int enable */
 127 -#define ICR_UR         (1 << 14)          /* unit reset */
 128 -#define ICR_FM         (1 << 15)          /* fast mode */
 129 -#define ICR_HS         (1 << 16)          /* High Speed mode */
 130 -#define ICR_GPIOEN     (1 << 19)          /* enable GPIO mode for SCL in HS */
 131 -
 132 -#define ISR_RWM                (1 << 0)           /* read/write mode */
 133 -#define ISR_ACKNAK     (1 << 1)           /* ack/nak status */
 134 -#define ISR_UB         (1 << 2)           /* unit busy */
 135 -#define ISR_IBB                (1 << 3)           /* bus busy */
 136 -#define ISR_SSD                (1 << 4)           /* slave stop detected */
 137 -#define ISR_ALD                (1 << 5)           /* arbitration loss detected */
 138 -#define ISR_ITE                (1 << 6)           /* tx buffer empty */
 139 -#define ISR_IRF                (1 << 7)           /* rx buffer full */
 140 -#define ISR_GCAD       (1 << 8)           /* general call address detected */
 141 -#define ISR_SAD                (1 << 9)           /* slave address detected */
 142 -#define ISR_BED                (1 << 10)          /* bus error no ACK/NAK */
 143 -
 144 -/* bit field shift & mask */
 145 -#define ILCR_SLV_SHIFT         0
 146 -#define ILCR_SLV_MASK          (0x1FF << ILCR_SLV_SHIFT)
 147 -#define ILCR_FLV_SHIFT         9
 148 -#define ILCR_FLV_MASK          (0x1FF << ILCR_FLV_SHIFT)
 149 -#define ILCR_HLVL_SHIFT                18
 150 -#define ILCR_HLVL_MASK         (0x1FF << ILCR_HLVL_SHIFT)
 151 -#define ILCR_HLVH_SHIFT                27
 152 -#define ILCR_HLVH_MASK         (0x1F << ILCR_HLVH_SHIFT)
 153 -
 154 -#define IWCR_CNT_SHIFT         0
 155 -#define IWCR_CNT_MASK          (0x1F << IWCR_CNT_SHIFT)
 156 -#define IWCR_HS_CNT1_SHIFT     5
 157 -#define IWCR_HS_CNT1_MASK      (0x1F << IWCR_HS_CNT1_SHIFT)
 158 -#define IWCR_HS_CNT2_SHIFT     10
 159 -#define IWCR_HS_CNT2_MASK      (0x1F << IWCR_HS_CNT2_SHIFT)
 160 -
 161  struct pxa_i2c {
 162         spinlock_t              lock;
 163         wait_queue_head_t       wait;
 164 --
 165 2.20.1
 166