mvebu: eDPU: add support for version with external switch
authorRobert Marko <robert.marko@sartura.hr>
Thu, 3 Aug 2023 11:16:05 +0000 (13:16 +0200)
committerRobert Marko <robert.marko@sartura.hr>
Tue, 19 Sep 2023 10:12:17 +0000 (12:12 +0200)
New revision of eDPU uses an Marvell MV88E6361 switch to connect the SFP
cage and G.hn IC instead of connecting them directly to the ethernet
controllers.

The same image can be used on both versions as U-Boot will enable the
switch node and disable the unused ethernet controller.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
target/linux/mvebu/cortexa53/base-files/etc/board.d/02_network
target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts

index 489090d77ca7724c34833a5eaf2bf714317e24f5..6789edb8613c33239458d21fa0a34bc032cfc009 100644 (file)
@@ -21,9 +21,16 @@ globalscale,espressobin-ultra)
        ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "wan"
        ;;
 marvell,armada-3720-db|\
-methode,udpu|\
+methode,udpu)
+       ucidef_set_interfaces_lan_wan "eth1" "eth0"
+       ;;
 methode,edpu)
+       # eDPU+ has a 88E6361 switch, so we check for it
+       if ip link | grep -q uplink; then
+       ucidef_set_interfaces_lan_wan "downlink" "uplink"
+       else
        ucidef_set_interfaces_lan_wan "eth1" "eth0"
+       fi
        ;;
 *)
        ucidef_set_interface_lan "eth0"
index 4db8b946df2e5f7c102648e35a404396dc58d7a9..35f107b63b543126e1141fa890e2003c5198a897 100644 (file)
 &eth0 {
        phy-mode = "1000base-x";
 };
+
+/*
+ * External MV88E6361 switch is only available on v2 of the board.
+ * U-Boot will enable the MDIO bus and switch nodes.
+ */
+&mdio {
+       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&smi_pins>;
+
+       /* Actual device is MV88E6361 */
+       switch: switch@0 {
+               compatible = "marvell,mv88e6190";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               label = "cpu";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               ethernet = <&eth0>;
+                       };
+
+                       port@9 {
+                               reg = <9>;
+                               label = "downlink";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                       };
+
+                       port@a {
+                               reg = <10>;
+                               label = "uplink";
+                               phy-mode = "2500base-x";
+                               managed = "in-band-status";
+                               sfp = <&sfp_eth1>;
+                       };
+               };
+       };
+};