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[openwrt/staging/jow.git] / target / linux / rtl838x / files-5.4 / drivers / net / dsa / rtl838x.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef _RTL838X_H
4 #define _RTL838X_H
5
6 #include <net/dsa.h>
7
8 /*
9 * Register definition
10 */
11 #define RTL838X_CPU_PORT 28
12 #define RTL839X_CPU_PORT 52
13
14 #define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7)))
15 #define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7)))
16 #define RTL838X_RST_GLB_CTRL_0 (0x003c)
17 #define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
18 #define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
19
20 #define RTL838X_DMY_REG31 (0x3b28)
21 #define RTL838X_SDS_MODE_SEL (0x0028)
22 #define RTL838X_SDS_CFG_REG (0x0034)
23 #define RTL838X_INT_MODE_CTRL (0x005c)
24 #define RTL838X_CHIP_INFO (0x00d8)
25 #define RTL839X_CHIP_INFO (0x0ff4)
26 #define RTL838X_SDS4_REG28 (0xef80)
27 #define RTL838X_SDS4_DUMMY0 (0xef8c)
28 #define RTL838X_SDS5_EXT_REG6 (0xf18c)
29 #define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
30 #define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3))
31 #define RTL8380_SDS4_FIB_REG0 (0xF800)
32 #define RTL838X_STAT_PORT_STD_MIB (0x1200)
33 #define RTL839X_STAT_PORT_STD_MIB (0xC000)
34 #define RTL838X_STAT_RST (0x3100)
35 #define RTL839X_STAT_RST (0xF504)
36 #define RTL838X_STAT_PORT_RST (0x3104)
37 #define RTL839X_STAT_PORT_RST (0xF508)
38 #define RTL838X_STAT_CTRL (0x3108)
39 #define RTL839X_STAT_CTRL (0x04cc)
40
41 /* Registers of the internal Serdes of the 8390 */
42 #define RTL8390_SDS0_1_XSG0 (0xA000)
43 #define RTL8390_SDS0_1_XSG1 (0xA100)
44 #define RTL839X_SDS12_13_XSG0 (0xB800)
45 #define RTL839X_SDS12_13_XSG1 (0xB900)
46 #define RTL839X_SDS12_13_PWR0 (0xb880)
47 #define RTL839X_SDS12_13_PWR1 (0xb980)
48
49 /* Registers of the internal Serdes of the 8380 */
50 #define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28
51 #define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100)
52 #define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0
53 #define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100)
54 #define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880)
55 #define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980)
56
57 /* Registers of the internal Serdes of the 8390 */
58 #define RTL8390_SDS0_1_XSG0 (0xA000)
59 #define RTL8390_SDS0_1_XSG1 (0xA100)
60 #define RTL839X_SDS12_13_XSG0 (0xB800)
61 #define RTL839X_SDS12_13_XSG1 (0xB900)
62 #define RTL839X_SDS12_13_PWR0 (0xb880)
63 #define RTL839X_SDS12_13_PWR1 (0xb980)
64
65 /* VLAN registers */
66 #define RTL838X_VLAN_PROFILE (0x3A88)
67 #define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
68 #define RTL838X_VLAN_PORT_PB_VLAN (0x3C00)
69 #define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C)
70 #define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C)
71 #define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A80)
72 #define RTL839X_VLAN_PROFILE (0x25C0)
73 #define RTL839X_VLAN_CTRL (0x26D4)
74 #define RTL839X_VLAN_PORT_PB_VLAN (0x26D8)
75 #define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4)
76 #define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4)
77
78 /* Table 0/1 access registers */
79 #define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
80 #define RTL838X_TBL_ACCESS_DATA_0 (0x6918)
81 #define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
82 #define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
83 #define RTL839X_TBL_ACCESS_CTRL_0 (0x1190)
84 #define RTL839X_TBL_ACCESS_DATA_0 (0x1194)
85 #define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80)
86 #define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2))
87
88 /* MAC handling */
89 #define RTL838X_MAC_LINK_STS (0xa188)
90 #define RTL839X_MAC_LINK_STS (0x0390)
91 #define RTL838X_MAC_LINK_SPD_STS(port) (0xa190 + (((port >> 4) << 2)))
92 #define RTL839X_MAC_LINK_SPD_STS(port) (0x03a0 + (((port >> 4) << 2)))
93 #define RTL838X_MAC_LINK_DUP_STS (0xa19c)
94 #define RTL839X_MAC_LINK_DUP_STS (0x03b0)
95 #define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
96 #define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
97 #define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
98 #define RTL839X_MAC_RX_PAUSE_STS (0x03c0)
99 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
100 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
101
102 #define RTL838X_DMA_IF_CTRL (0x9f58)
103
104 /* MAC link state bits */
105 #define FORCE_EN (1 << 0)
106 #define FORCE_LINK_EN (1 << 1)
107 #define NWAY_EN (1 << 2)
108 #define DUPLX_MODE (1 << 3)
109 #define TX_PAUSE_EN (1 << 6)
110 #define RX_PAUSE_EN (1 << 7)
111
112 /* EEE */
113 #define RTL838X_MAC_EEE_ABLTY (0xa1a8)
114 #define RTL838X_EEE_PORT_TX_EN (0x014c)
115 #define RTL838X_EEE_PORT_RX_EN (0x0150)
116 #define RTL838X_EEE_CLK_STOP_CTRL (0x0148)
117
118 /* L2 functionality */
119 #define RTL838X_L2_CTRL_0 (0x3200)
120 #define RTL839X_L2_CTRL_0 (0x3800)
121 #define RTL838X_L2_CTRL_1 (0x3204)
122 #define RTL839X_L2_CTRL_1 (0x3804)
123 #define RTL838X_L2_PORT_AGING_OUT (0x3358)
124 #define RTL839X_L2_PORT_AGING_OUT (0x3b74)
125 #define RTL838X_TBL_ACCESS_L2_CTRL (0x6900)
126 #define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
127 #define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2))
128 #define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
129 #define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
130 #define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
131 #define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2)))
132 #define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2)))
133 #define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2)))
134 #define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2)))
135 #define RTL838X_L2_PORT_SALRN(p) (0x328c + (((p >> 4) << 2)))
136 #define RTL839X_L2_PORT_SALRN(p) (0x38F0 + (((p >> 4) << 2)))
137
138 /* Port Mirroring */
139 #define RTL838X_MIR_CTRL(grp) (0x5D00 + (((grp) << 2)))
140 #define RTL838X_MIR_DPM_CTRL(grp) (0x5D20 + (((grp) << 2)))
141 #define RTL838X_MIR_SPM_CTRL(grp) (0x5D10 + (((grp) << 2)))
142 #define RTL839X_MIR_CTRL(grp) (0x2500 + (((grp) << 2)))
143 #define RTL839X_MIR_DPM_CTRL(grp) (0x2530 + (((grp) << 2)))
144 #define RTL839X_MIR_SPM_CTRL(grp) (0x2510 + (((grp) << 2)))
145
146 enum phy_type {
147 PHY_NONE = 0,
148 PHY_RTL838X_SDS = 1,
149 PHY_RTL8218B_INT = 2,
150 PHY_RTL8218B_EXT = 3,
151 PHY_RTL8214FC = 4,
152 PHY_RTL839X_SDS = 5,
153 };
154
155 struct rtl838x_port {
156 bool enable;
157 u64 pm;
158 u16 pvid;
159 bool eee_enabled;
160 enum phy_type phy;
161 };
162
163 struct rtl838x_vlan_info {
164 u64 untagged_ports;
165 u64 tagged_ports;
166 u8 profile_id;
167 bool hash_mc;
168 bool hash_uc;
169 u8 fid;
170 };
171
172 enum l2_entry_type {
173 L2_INVALID = 0,
174 L2_UNICAST = 1,
175 L2_MULTICAST = 2,
176 IP4_MULTICAST = 3,
177 IP6_MULTICAST = 4,
178 };
179
180 struct rtl838x_l2_entry {
181 u8 mac[ETH_ALEN];
182 u16 vid;
183 u16 rvid;
184 u8 port;
185 bool valid;
186 enum l2_entry_type type;
187 bool is_static;
188 bool is_ip_mc;
189 bool is_ipv6_mc;
190 bool block_da;
191 bool block_sa;
192 bool suspended;
193 bool next_hop;
194 int age;
195 u16 mc_portmask_index;
196 };
197
198 struct rtl838x_switch_priv;
199
200 struct rtl838x_reg {
201 void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
202 void (*set_port_reg_be)(u64 set, int reg);
203 u64 (*get_port_reg_be)(int reg);
204 void (*mask_port_reg_le)(u64 clear, u64 set, int reg);
205 void (*set_port_reg_le)(u64 set, int reg);
206 u64 (*get_port_reg_le)(int reg);
207 int stat_port_rst;
208 int stat_rst;
209 int (*stat_port_std_mib)(int p);
210 int (*port_iso_ctrl)(int p);
211 int l2_ctrl_0;
212 int l2_ctrl_1;
213 int l2_port_aging_out;
214 int smi_poll_ctrl;
215 int l2_tbl_flush_ctrl;
216 void (*exec_tbl0_cmd)(u32 cmd);
217 void (*exec_tbl1_cmd)(u32 cmd);
218 int (*tbl_access_data_0)(int i);
219 int isr_glb_src;
220 int isr_port_link_sts_chg;
221 int imr_port_link_sts_chg;
222 int imr_glb;
223 void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
224 void (*vlan_set_tagged)(u32 vlan, const struct rtl838x_vlan_info *info);
225 void (*vlan_set_untagged)(u32 vlan, u64 portmask);
226 int (*mac_force_mode_ctrl)(int port);
227 int (*mac_port_ctrl)(int port);
228 int (*l2_port_new_salrn)(int port);
229 int (*l2_port_new_sa_fwd)(int port);
230 int (*mir_ctrl)(int group);
231 int (*mir_dpm)(int group);
232 int (*mir_spm)(int group);
233 int mac_link_sts;
234 int mac_link_dup_sts;
235 int (*mac_link_spd_sts)(int port);
236 int mac_rx_pause_sts;
237 int mac_tx_pause_sts;
238 u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);
239 u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);
240 int (*vlan_profile)(int profile);
241 int (*vlan_port_egr_filter)(int port);
242 int (*vlan_port_igr_filter)(int port);
243 int (*vlan_port_pb)(int port);
244 };
245
246 struct rtl838x_switch_priv {
247 /* Switch operation */
248 struct dsa_switch *ds;
249 struct device *dev;
250 u16 id;
251 u16 family_id;
252 char version;
253 struct rtl838x_port ports[54]; /* TODO: correct size! */
254 struct mutex reg_mutex;
255 int link_state_irq;
256 int mirror_group_ports[4];
257 struct mii_bus *mii_bus;
258 const struct rtl838x_reg *r;
259 u8 cpu_port;
260 u8 port_mask;
261 u32 fib_entries;
262 };
263
264 extern struct rtl838x_soc_info soc_info;
265 extern void rtl8380_sds_rst(int mac);
266
267 extern int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
268 extern int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
269 extern int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
270 extern int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
271 extern int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val);
272 extern int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val);
273
274 #endif /* _RTL838X_H */
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