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realtek: update the tree to the latest refactored version
[openwrt/staging/jow.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_print_matrix(void)
14 {
15 unsigned volatile int *ptr8;
16 volatile u64 *ptr9;
17 int i;
18
19 if (soc_info.family == RTL8380_FAMILY_ID) {
20 ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
21 for (i = 0; i < 28; i += 8)
22 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
23 ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
24 ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
25 pr_debug("CPU_PORT> %8x\n", ptr8[28]);
26 } else {
27 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
28 for (i = 0; i < 52; i += 4)
29 pr_debug("> %16llx %16llx %16llx %16llx\n",
30 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
31 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
32 }
33
34 }
35
36 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
37 {
38 mutex_lock(&priv->reg_mutex);
39
40 /* Enable statistics module: all counters plus debug.
41 * On RTL839x all counters are enabled by default
42 */
43 if (priv->family_id == RTL8380_FAMILY_ID)
44 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
45
46 /* Reset statistics counters */
47 sw_w32_mask(0, 1, priv->r->stat_rst);
48
49 mutex_unlock(&priv->reg_mutex);
50 }
51
52 static void rtl83xx_write_cam(int idx, u32 *r)
53 {
54 u32 cmd = BIT(16) /* Execute cmd */
55 | BIT(15) /* Read */
56 | BIT(13) /* Table type 0b01 */
57 | (idx & 0x3f);
58
59 sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
60 sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
61 sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
62
63 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
64 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
65 }
66
67 static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
68 {
69 if (priv->family_id == RTL8380_FAMILY_ID)
70 return rtl838x_hash(priv, mac << 12 | vid);
71 else
72 return rtl839x_hash(priv, mac << 12 | vid);
73 }
74
75 static void rtl83xx_write_hash(int idx, u32 *r)
76 {
77 u32 cmd = BIT(16) /* Execute cmd */
78 | 0 << 15 /* Write */
79 | 0 << 13 /* Table type 0b00 */
80 | (idx & 0x1fff);
81
82 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
83 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
84 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
85 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
86 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
87 }
88
89 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
90 {
91 int i;
92 u64 v = 0;
93
94 msleep(1000);
95 /* Enable all ports with a PHY, including the SFP-ports */
96 for (i = 0; i < priv->cpu_port; i++) {
97 if (priv->ports[i].phy)
98 v |= BIT(i);
99 }
100
101 pr_debug("%s: %16llx\n", __func__, v);
102 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
103
104 /* PHY update complete */
105 if (priv->family_id == RTL8390_FAMILY_ID)
106 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
107 else
108 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
109 }
110
111 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
112 MIB_DESC(2, 0xf8, "ifInOctets"),
113 MIB_DESC(2, 0xf0, "ifOutOctets"),
114 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
115 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
116 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
117 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
118 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
119 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
120 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
121 MIB_DESC(1, 0xd0, "ifOutDiscards"),
122 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
123 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
124 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
125 MIB_DESC(1, 0xc0, ".3LateCollisions"),
126 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
127 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
128 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
129 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
130 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
131 MIB_DESC(1, 0xa8, "DropEvents"),
132 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
133 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
134 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
135 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
136 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
137 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
138 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
139 MIB_DESC(1, 0x88, "rx_OversizePkts"),
140 MIB_DESC(1, 0x84, "Fragments"),
141 MIB_DESC(1, 0x80, "Jabbers"),
142 MIB_DESC(1, 0x7c, "Collisions"),
143 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
144 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
145 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
146 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
147 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
148 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
149 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
150 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
151 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
152 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
153 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
154 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
155 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
156 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
157 MIB_DESC(1, 0x40, "rxMacDiscards")
158 };
159
160
161 /* DSA callbacks */
162
163
164 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
165 {
166 /* The switch does not tag the frames, instead internally the header
167 * structure for each packet is tagged accordingly.
168 */
169 return DSA_TAG_PROTO_TRAILER;
170 }
171
172 static int rtl83xx_setup(struct dsa_switch *ds)
173 {
174 int i;
175 struct rtl838x_switch_priv *priv = ds->priv;
176 u64 port_bitmap = BIT_ULL(priv->cpu_port);
177
178 pr_debug("%s called\n", __func__);
179
180 /* Disable MAC polling the PHY so that we can start configuration */
181 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
182
183 for (i = 0; i < ds->num_ports; i++)
184 priv->ports[i].enable = false;
185 priv->ports[priv->cpu_port].enable = true;
186
187 /* Isolate ports from each other: traffic only CPU <-> port */
188 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
189 * traffic from source port i to destination port j
190 */
191 for (i = 0; i < priv->cpu_port; i++) {
192 if (priv->ports[i].phy) {
193 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i),
194 priv->r->port_iso_ctrl(i));
195 port_bitmap |= BIT_ULL(i);
196 }
197 }
198 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
199
200 rtl83xx_print_matrix();
201
202 rtl83xx_init_stats(priv);
203
204 ds->configure_vlan_while_not_filtering = true;
205
206 /* Enable MAC Polling PHY again */
207 rtl83xx_enable_phy_polling(priv);
208 pr_debug("Please wait until PHY is settled\n");
209 msleep(1000);
210 return 0;
211 }
212
213 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
214 unsigned long *supported,
215 struct phylink_link_state *state)
216 {
217 struct rtl838x_switch_priv *priv = ds->priv;
218 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
219
220 pr_debug("In %s port %d", __func__, port);
221
222 if (!phy_interface_mode_is_rgmii(state->interface) &&
223 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
224 state->interface != PHY_INTERFACE_MODE_MII &&
225 state->interface != PHY_INTERFACE_MODE_REVMII &&
226 state->interface != PHY_INTERFACE_MODE_GMII &&
227 state->interface != PHY_INTERFACE_MODE_QSGMII &&
228 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
229 state->interface != PHY_INTERFACE_MODE_SGMII) {
230 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
231 dev_err(ds->dev,
232 "Unsupported interface: %d for port %d\n",
233 state->interface, port);
234 return;
235 }
236
237 /* Allow all the expected bits */
238 phylink_set(mask, Autoneg);
239 phylink_set_port_modes(mask);
240 phylink_set(mask, Pause);
241 phylink_set(mask, Asym_Pause);
242
243 /* With the exclusion of MII and Reverse MII, we support Gigabit,
244 * including Half duplex
245 */
246 if (state->interface != PHY_INTERFACE_MODE_MII &&
247 state->interface != PHY_INTERFACE_MODE_REVMII) {
248 phylink_set(mask, 1000baseT_Full);
249 phylink_set(mask, 1000baseT_Half);
250 }
251
252 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
253 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
254 phylink_set(mask, 1000baseX_Full);
255
256 phylink_set(mask, 10baseT_Half);
257 phylink_set(mask, 10baseT_Full);
258 phylink_set(mask, 100baseT_Half);
259 phylink_set(mask, 100baseT_Full);
260
261 bitmap_and(supported, supported, mask,
262 __ETHTOOL_LINK_MODE_MASK_NBITS);
263 bitmap_and(state->advertising, state->advertising, mask,
264 __ETHTOOL_LINK_MODE_MASK_NBITS);
265 }
266
267 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
268 struct phylink_link_state *state)
269 {
270 struct rtl838x_switch_priv *priv = ds->priv;
271 u64 speed;
272
273 if (port < 0 || port > priv->cpu_port)
274 return -EINVAL;
275
276 state->link = 0;
277 if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & BIT_ULL(port))
278 state->link = 1;
279 state->duplex = 0;
280 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
281 state->duplex = 1;
282
283 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
284 speed >>= (port % 16) << 1;
285 switch (speed & 0x3) {
286 case 0:
287 state->speed = SPEED_10;
288 break;
289 case 1:
290 state->speed = SPEED_100;
291 break;
292 case 2:
293 state->speed = SPEED_1000;
294 break;
295 case 3:
296 if (port == 24 || port == 26) /* Internal serdes */
297 state->speed = SPEED_2500;
298 else
299 state->speed = SPEED_100; /* Is in fact 500Mbit */
300 }
301
302 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
303 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
304 state->pause |= MLO_PAUSE_RX;
305 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
306 state->pause |= MLO_PAUSE_TX;
307 return 1;
308 }
309
310 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
311 unsigned int mode,
312 const struct phylink_link_state *state)
313 {
314 struct rtl838x_switch_priv *priv = ds->priv;
315 u32 reg;
316 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
317
318 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
319
320 if (port == priv->cpu_port) {
321 /* Set Speed, duplex, flow control
322 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
323 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
324 * | MEDIA_SEL
325 */
326 if (priv->family_id == RTL8380_FAMILY_ID) {
327 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
328 /* allow CRC errors on CPU-port */
329 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
330 } else {
331 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
332 }
333 return;
334 }
335
336 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
337 /* Auto-Negotiation does not work for MAC in RTL8390 */
338 if (priv->family_id == RTL8380_FAMILY_ID) {
339 if (mode == MLO_AN_PHY) {
340 pr_debug("PHY autonegotiates\n");
341 reg |= BIT(2);
342 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
343 return;
344 }
345 }
346
347 if (mode != MLO_AN_FIXED)
348 pr_debug("Fixed state.\n");
349
350 if (priv->family_id == RTL8380_FAMILY_ID) {
351 /* Clear id_mode_dis bit, and the existing port mode, let
352 * RGMII_MODE_EN bet set by mac_link_{up,down}
353 */
354 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
355
356 if (state->pause & MLO_PAUSE_TXRX_MASK) {
357 if (state->pause & MLO_PAUSE_TX)
358 reg |= TX_PAUSE_EN;
359 reg |= RX_PAUSE_EN;
360 }
361 }
362
363 reg &= ~(3 << speed_bit);
364 switch (state->speed) {
365 case SPEED_1000:
366 reg |= 2 << speed_bit;
367 break;
368 case SPEED_100:
369 reg |= 1 << speed_bit;
370 break;
371 }
372
373 if (priv->family_id == RTL8380_FAMILY_ID) {
374 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
375 if (state->link)
376 reg |= FORCE_LINK_EN;
377 if (state->duplex == DUPLEX_FULL)
378 reg |= DUPLX_MODE;
379 }
380
381 // Disable AN
382 if (priv->family_id == RTL8380_FAMILY_ID)
383 reg &= ~BIT(2);
384 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
385 }
386
387 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
388 unsigned int mode,
389 phy_interface_t interface)
390 {
391 struct rtl838x_switch_priv *priv = ds->priv;
392 /* Stop TX/RX to port */
393 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
394 }
395
396 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
397 unsigned int mode,
398 phy_interface_t interface,
399 struct phy_device *phydev)
400 {
401 struct rtl838x_switch_priv *priv = ds->priv;
402 /* Restart TX/RX to port */
403 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
404 }
405
406 static void rtl83xx_get_strings(struct dsa_switch *ds,
407 int port, u32 stringset, u8 *data)
408 {
409 int i;
410
411 if (stringset != ETH_SS_STATS)
412 return;
413
414 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
415 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
416 ETH_GSTRING_LEN);
417 }
418
419 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
420 uint64_t *data)
421 {
422 struct rtl838x_switch_priv *priv = ds->priv;
423 const struct rtl83xx_mib_desc *mib;
424 int i;
425 u64 high;
426
427 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
428 mib = &rtl83xx_mib[i];
429
430 data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset);
431 if (mib->size == 2) {
432 high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4);
433 data[i] |= high << 32;
434 }
435 }
436 }
437
438 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
439 {
440 if (sset != ETH_SS_STATS)
441 return 0;
442
443 return ARRAY_SIZE(rtl83xx_mib);
444 }
445
446 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
447 struct phy_device *phydev)
448 {
449 struct rtl838x_switch_priv *priv = ds->priv;
450
451 pr_debug("%s: %x %d", __func__, (u32) priv, port);
452 priv->ports[port].enable = true;
453
454 /* enable inner tagging on egress, do not keep any tags */
455 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl(port));
456
457 if (dsa_is_cpu_port(ds, port))
458 return 0;
459
460 /* add port to switch mask of CPU_PORT */
461 priv->r->mask_port_reg_be(0ULL, BIT_ULL(port), priv->r->port_iso_ctrl(priv->cpu_port));
462
463 /* add all other ports in the same bridge to switch mask of port */
464 priv->r->mask_port_reg_be(0ULL, priv->ports[port].pm, priv->r->port_iso_ctrl(port));
465
466 return 0;
467 }
468
469 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
470 {
471 struct rtl838x_switch_priv *priv = ds->priv;
472
473 pr_debug("%s %x: %d", __func__, (u32)priv, port);
474 /* you can only disable user ports */
475 if (!dsa_is_user_port(ds, port))
476 return;
477
478 /* remove port from switch mask of CPU_PORT */
479 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->port_iso_ctrl(priv->cpu_port));
480
481 /* remove all other ports in the same bridge from switch mask of port */
482 priv->r->mask_port_reg_be(priv->ports[port].pm, 0LL, priv->r->port_iso_ctrl(port));
483
484 priv->ports[port].enable = false;
485 }
486
487 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
488 struct ethtool_eee *e)
489 {
490 struct rtl838x_switch_priv *priv = ds->priv;
491
492 pr_debug("%s: port %d", __func__, port);
493 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
494 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(9))
495 e->advertised |= ADVERTISED_100baseT_Full;
496
497 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(10))
498 e->advertised |= ADVERTISED_1000baseT_Full;
499
500 e->eee_enabled = priv->ports[port].eee_enabled;
501 pr_debug("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
502
503 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
504 e->lp_advertised = ADVERTISED_100baseT_Full;
505 e->lp_advertised |= ADVERTISED_1000baseT_Full;
506 }
507
508 e->eee_active = !!(e->advertised & e->lp_advertised);
509 pr_debug("active: %d, lp %x\n", e->eee_active, e->lp_advertised);
510
511 return 0;
512 }
513
514 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
515 struct ethtool_eee *e)
516 {
517 struct rtl838x_switch_priv *priv = ds->priv;
518
519 pr_debug("%s: port %d", __func__, port);
520 if (e->eee_enabled) {
521 pr_debug("Globally enabling EEE\n");
522 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
523 }
524 if (e->eee_enabled) {
525 pr_debug("Enabling EEE for MAC %d\n", port);
526 sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
527 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
528 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
529 priv->ports[port].eee_enabled = true;
530 e->eee_enabled = true;
531 } else {
532 pr_debug("Disabling EEE for MAC %d\n", port);
533 sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
534 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
535 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
536 priv->ports[port].eee_enabled = false;
537 e->eee_enabled = false;
538 }
539 return 0;
540 }
541
542 /*
543 * Set Switch L2 Aging time, t is time in milliseconds
544 * t = 0: aging is disabled
545 */
546 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
547 {
548 struct rtl838x_switch_priv *priv = ds->priv;
549 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
550
551 /* Convert time in mseconds to internal value */
552 if (t > 0x10000000) { /* Set to maximum */
553 t = t_max;
554 } else {
555 if (priv->family_id == RTL8380_FAMILY_ID)
556 t = ((t * 625) / 1000 + 127) / 128;
557 else
558 t = (t * 5 + 2) / 3;
559 }
560 sw_w32(t, priv->r->l2_ctrl_1);
561 return 0;
562 }
563
564 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
565 struct net_device *bridge)
566 {
567 struct rtl838x_switch_priv *priv = ds->priv;
568 u64 port_bitmap = BIT_ULL(priv->cpu_port);
569 int i;
570
571 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
572 mutex_lock(&priv->reg_mutex);
573 for (i = 0; i < ds->num_ports; i++) {
574 /* Add this port to the port matrix of the other ports in the
575 * same bridge. If the port is disabled, port matrix is kept
576 * and not being setup until the port becomes enabled.
577 */
578 if (dsa_is_user_port(ds, i) && i != port) {
579 if (dsa_to_port(ds, i)->bridge_dev != bridge)
580 continue;
581 if (priv->ports[i].enable)
582 priv->r->mask_port_reg_be(0, BIT_ULL(port),
583 priv->r->port_iso_ctrl(i));
584 priv->ports[i].pm |= BIT_ULL(port);
585
586 port_bitmap |= BIT_ULL(i);
587 }
588 }
589
590 /* Add all other ports to this port matrix. */
591 if (priv->ports[port].enable) {
592 priv->r->mask_port_reg_be(0, BIT_ULL(port),
593 priv->r->port_iso_ctrl(priv->cpu_port));
594 priv->r->mask_port_reg_be(0, port_bitmap,
595 priv->r->port_iso_ctrl(port));
596 }
597 priv->ports[port].pm |= port_bitmap;
598 mutex_unlock(&priv->reg_mutex);
599
600 return 0;
601 }
602
603 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
604 struct net_device *bridge)
605 {
606 struct rtl838x_switch_priv *priv = ds->priv;
607 u64 port_bitmap = BIT_ULL(priv->cpu_port);
608 int i;
609
610 pr_debug("%s %x: %d", __func__, (u32)priv, port);
611 mutex_lock(&priv->reg_mutex);
612 for (i = 0; i < ds->num_ports; i++) {
613 /* Remove this port from the port matrix of the other ports
614 * in the same bridge. If the port is disabled, port matrix
615 * is kept and not being setup until the port becomes enabled.
616 * And the other port's port matrix cannot be broken when the
617 * other port is still a VLAN-aware port.
618 */
619 if (dsa_is_user_port(ds, i) && i != port) {
620 if (dsa_to_port(ds, i)->bridge_dev != bridge)
621 continue;
622 if (priv->ports[i].enable)
623 priv->r->mask_port_reg_be(BIT_ULL(port), 0,
624 priv->r->port_iso_ctrl(i));
625 priv->ports[i].pm &= ~BIT_ULL(port);
626
627 port_bitmap &= ~BIT_ULL(i);
628 }
629 }
630
631 /* Add all other ports to this port matrix. */
632 if (priv->ports[port].enable)
633 priv->r->mask_port_reg_be(0, port_bitmap, priv->r->port_iso_ctrl(port));
634 priv->ports[port].pm &= ~port_bitmap;
635
636 mutex_unlock(&priv->reg_mutex);
637 }
638
639 static void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port,
640 u8 state)
641 {
642 u32 cmd, msti = 0;
643 u32 port_state[4];
644 int index, bit, i;
645 int pos = port;
646 struct rtl838x_switch_priv *priv = ds->priv;
647 int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
648
649 pr_debug("%s: port %d state %2x\n", __func__, port, state);
650
651 /* CPU PORT can only be configured on RTL838x */
652 if (port >= priv->cpu_port || port > 51)
653 return;
654
655 mutex_lock(&priv->reg_mutex);
656
657 /* For the RTL839x, the bits are left-aligned in the 128 bit field */
658 if (priv->family_id == RTL8390_FAMILY_ID)
659 pos += 12;
660
661 index = n - (pos >> 4) - 1;
662 bit = (pos << 1) % 32;
663
664 if (priv->family_id == RTL8380_FAMILY_ID) {
665 cmd = BIT(15) /* Execute cmd */
666 | BIT(14) /* Read */
667 | 2 << 12 /* Table type 0b10 */
668 | (msti & 0xfff);
669 } else {
670 cmd = BIT(16) /* Execute cmd */
671 | 0 << 15 /* Read */
672 | 5 << 12 /* Table type 0b101 */
673 | (msti & 0xfff);
674 }
675 priv->r->exec_tbl0_cmd(cmd);
676
677 for (i = 0; i < n; i++)
678 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
679
680 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
681 port_state[index] &= ~(3 << bit);
682
683 switch (state) {
684 case BR_STATE_DISABLED: /* 0 */
685 port_state[index] |= (0 << bit);
686 break;
687 case BR_STATE_BLOCKING: /* 4 */
688 case BR_STATE_LISTENING: /* 1 */
689 port_state[index] |= (1 << bit);
690 break;
691 case BR_STATE_LEARNING: /* 2 */
692 port_state[index] |= (2 << bit);
693 break;
694 case BR_STATE_FORWARDING: /* 3*/
695 port_state[index] |= (3 << bit);
696 default:
697 break;
698 }
699
700 if (priv->family_id == RTL8380_FAMILY_ID) {
701 cmd = BIT(15) /* Execute cmd */
702 | 0 << 14 /* Write */
703 | 2 << 12 /* Table type 0b10 */
704 | (msti & 0xfff);
705 } else {
706 cmd = 1 << 16 /* Execute cmd */
707 | BIT(15) /* Write */
708 | 5 << 12 /* Table type 0b101 */
709 | (msti & 0xfff);
710 }
711 for (i = 0; i < n; i++)
712 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
713 priv->r->exec_tbl0_cmd(cmd);
714
715 mutex_unlock(&priv->reg_mutex);
716 }
717
718 static void rtl83xx_fast_age(struct dsa_switch *ds, int port)
719 {
720 struct rtl838x_switch_priv *priv = ds->priv;
721 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
722
723 pr_debug("FAST AGE port %d\n", port);
724 mutex_lock(&priv->reg_mutex);
725 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
726 * port fields:
727 * 0-4: Replacing port
728 * 5-9: Flushed/replaced port
729 * 10-21: FVID
730 * 22: Entry types: 1: dynamic, 0: also static
731 * 23: Match flush port
732 * 24: Match FVID
733 * 25: Flush (0) or replace (1) L2 entries
734 * 26: Status of action (1: Start, 0: Done)
735 */
736 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
737
738 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s)));
739
740 mutex_unlock(&priv->reg_mutex);
741 }
742
743 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
744 bool vlan_filtering)
745 {
746 struct rtl838x_switch_priv *priv = ds->priv;
747
748 pr_debug("%s: port %d\n", __func__, port);
749 mutex_lock(&priv->reg_mutex);
750
751 if (vlan_filtering) {
752 /* Enable ingress and egress filtering */
753 if (port != priv->cpu_port)
754 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
755 priv->r->vlan_port_igr_filter(port));
756 sw_w32_mask(0, 1 << (port % 32), priv->r->vlan_port_egr_filter(port));
757 } else {
758 /* Disable ingress and egress filtering */
759 if (port != priv->cpu_port)
760 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
761 priv->r->vlan_port_igr_filter(port));
762 sw_w32_mask(1 << (port % 32), 0, priv->r->vlan_port_egr_filter(port));
763 }
764
765 /* Do we need to do something to the CPU-Port, too? */
766 mutex_unlock(&priv->reg_mutex);
767
768 return 0;
769 }
770
771 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
772 const struct switchdev_obj_port_vlan *vlan)
773 {
774 struct rtl838x_vlan_info info;
775 struct rtl838x_switch_priv *priv = ds->priv;
776
777 pr_debug("%s: port %d\n", __func__, port);
778
779 mutex_lock(&priv->reg_mutex);
780
781 if (priv->family_id == RTL8380_FAMILY_ID)
782 rtl838x_vlan_profile_dump(0);
783 else
784 rtl839x_vlan_profile_dump(0);
785
786 priv->r->vlan_tables_read(0, &info);
787
788 pr_debug("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
789 info.tagged_ports, info.untagged_ports, info.profile_id,
790 info.hash_mc_fid, info.hash_uc_fid, info.fid);
791
792 mutex_unlock(&priv->reg_mutex);
793 return 0;
794 }
795
796 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
797 const struct switchdev_obj_port_vlan *vlan)
798 {
799 struct rtl838x_vlan_info info = {};
800 struct rtl838x_switch_priv *priv = ds->priv;
801 int v;
802
803 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
804 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
805
806 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
807 dev_err(priv->dev, "VLAN out of range: %d - %d",
808 vlan->vid_begin, vlan->vid_end);
809 return;
810 }
811
812 mutex_lock(&priv->reg_mutex);
813
814 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
815 /* Set both inner and outer PVID of the port */
816 sw_w32((vlan->vid_end << 16) | vlan->vid_end << 2, priv->r->vlan_port_pb(port));
817 priv->ports[port].pvid = vlan->vid_end;
818 }
819
820 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
821 /* Get port memberships of this vlan */
822 priv->r->vlan_tables_read(v, &info);
823
824 /* new VLAN? */
825 if (!info.tagged_ports) {
826 info.fid = 0;
827 info.hash_mc_fid = false;
828 info.hash_uc_fid = false;
829 info.profile_id = 0;
830 }
831
832 /* sanitize untagged_ports - must be a subset */
833 if (info.untagged_ports & ~info.tagged_ports)
834 info.untagged_ports = 0;
835
836 info.tagged_ports |= BIT_ULL(port);
837 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
838 info.untagged_ports |= BIT_ULL(port);
839
840 priv->r->vlan_set_untagged(v, info.untagged_ports);
841 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
842
843 priv->r->vlan_set_tagged(v, &info);
844 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
845 }
846
847 mutex_unlock(&priv->reg_mutex);
848 }
849
850 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
851 const struct switchdev_obj_port_vlan *vlan)
852 {
853 struct rtl838x_vlan_info info;
854 struct rtl838x_switch_priv *priv = ds->priv;
855 int v;
856 u16 pvid;
857
858 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
859 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
860
861 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
862 dev_err(priv->dev, "VLAN out of range: %d - %d",
863 vlan->vid_begin, vlan->vid_end);
864 return -ENOTSUPP;
865 }
866
867 mutex_lock(&priv->reg_mutex);
868 pvid = priv->ports[port].pvid;
869
870 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
871 /* Reset to default if removing the current PVID */
872 if (v == pvid)
873 sw_w32(0, priv->r->vlan_port_pb(port));
874
875 /* Get port memberships of this vlan */
876 priv->r->vlan_tables_read(v, &info);
877
878 /* remove port from both tables */
879 info.untagged_ports &= (~BIT_ULL(port));
880 /* always leave vid 1 */
881 if (v != 1)
882 info.tagged_ports &= (~BIT_ULL(port));
883
884 priv->r->vlan_set_untagged(v, info.untagged_ports);
885 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
886
887 priv->r->vlan_set_tagged(v, &info);
888 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
889 }
890 mutex_unlock(&priv->reg_mutex);
891
892 return 0;
893 }
894
895 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
896 const unsigned char *addr, u16 vid)
897 {
898 struct rtl838x_switch_priv *priv = ds->priv;
899 u64 mac = ether_addr_to_u64(addr);
900 u32 key = rtl83xx_hash_key(priv, mac, vid);
901 struct rtl838x_l2_entry e;
902 u32 r[3];
903 u64 entry;
904 int idx = -1, err = 0, i;
905
906 mutex_lock(&priv->reg_mutex);
907 for (i = 0; i < 4; i++) {
908 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
909 if (!e.valid) {
910 idx = (key << 2) | i;
911 break;
912 }
913 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
914 idx = (key << 2) | i;
915 break;
916 }
917 }
918 if (idx >= 0) {
919 r[0] = 3 << 17 | port << 12; // Aging and port
920 r[0] |= vid;
921 r[1] = mac >> 16;
922 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
923 rtl83xx_write_hash(idx, r);
924 goto out;
925 }
926
927 /* Hash buckets full, try CAM */
928 for (i = 0; i < 64; i++) {
929 entry = priv->r->read_cam(i, &e);
930 if (!e.valid) {
931 if (idx < 0) /* First empty entry? */
932 idx = i;
933 break;
934 } else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
935 pr_debug("Found entry in CAM\n");
936 idx = i;
937 break;
938 }
939 }
940 if (idx >= 0) {
941 r[0] = 3 << 17 | port << 12; // Aging
942 r[0] |= vid;
943 r[1] = mac >> 16;
944 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
945 rtl83xx_write_cam(idx, r);
946 goto out;
947 }
948 err = -ENOTSUPP;
949 out:
950 mutex_unlock(&priv->reg_mutex);
951 return err;
952 }
953
954 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
955 const unsigned char *addr, u16 vid)
956 {
957 struct rtl838x_switch_priv *priv = ds->priv;
958 u64 mac = ether_addr_to_u64(addr);
959 u32 key = rtl83xx_hash_key(priv, mac, vid);
960 struct rtl838x_l2_entry e;
961 u32 r[3];
962 u64 entry;
963 int idx = -1, err = 0, i;
964
965 pr_debug("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key);
966 mutex_lock(&priv->reg_mutex);
967 for (i = 0; i < 4; i++) {
968 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
969 if (!e.valid)
970 continue;
971 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
972 idx = (key << 2) | i;
973 break;
974 }
975 }
976
977 if (idx >= 0) {
978 r[0] = r[1] = r[2] = 0;
979 rtl83xx_write_hash(idx, r);
980 goto out;
981 }
982
983 /* Check CAM for spillover from hash buckets */
984 for (i = 0; i < 64; i++) {
985 entry = priv->r->read_cam(i, &e);
986 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
987 idx = i;
988 break;
989 }
990 }
991 if (idx >= 0) {
992 r[0] = r[1] = r[2] = 0;
993 rtl83xx_write_cam(idx, r);
994 goto out;
995 }
996 err = -ENOENT;
997 out:
998 mutex_unlock(&priv->reg_mutex);
999 return err;
1000 }
1001
1002 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1003 dsa_fdb_dump_cb_t *cb, void *data)
1004 {
1005 struct rtl838x_l2_entry e;
1006 struct rtl838x_switch_priv *priv = ds->priv;
1007 int i;
1008 u32 fid;
1009 u32 pkey;
1010 u64 mac;
1011
1012 mutex_lock(&priv->reg_mutex);
1013
1014 for (i = 0; i < priv->fib_entries; i++) {
1015 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1016
1017 if (!e.valid)
1018 continue;
1019
1020 if (e.port == port) {
1021 fid = (i & 0x3ff) | (e.rvid & ~0x3ff);
1022 mac = ether_addr_to_u64(&e.mac[0]);
1023 pkey = rtl838x_hash(priv, mac << 12 | fid);
1024 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1025 pr_debug("-> mac %016llx, fid: %d\n", mac, fid);
1026 cb(e.mac, e.vid, e.is_static, data);
1027 }
1028 }
1029
1030 for (i = 0; i < 64; i++) {
1031 priv->r->read_cam(i, &e);
1032
1033 if (!e.valid)
1034 continue;
1035
1036 if (e.port == port)
1037 cb(e.mac, e.vid, e.is_static, data);
1038 }
1039
1040 mutex_unlock(&priv->reg_mutex);
1041 return 0;
1042 }
1043
1044 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1045 struct dsa_mall_mirror_tc_entry *mirror,
1046 bool ingress)
1047 {
1048 /* We support 4 mirror groups, one destination port per group */
1049 int group;
1050 struct rtl838x_switch_priv *priv = ds->priv;
1051
1052 pr_debug("In %s\n", __func__);
1053
1054 for (group = 0; group < 4; group++) {
1055 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1056 break;
1057 }
1058 if (group >= 4) {
1059 for (group = 0; group < 4; group++) {
1060 if (priv->mirror_group_ports[group] < 0)
1061 break;
1062 }
1063 }
1064
1065 if (group >= 4)
1066 return -ENOSPC;
1067
1068 pr_debug("Using group %d\n", group);
1069 mutex_lock(&priv->reg_mutex);
1070
1071 if (priv->family_id == RTL8380_FAMILY_ID) {
1072 /* Enable mirroring to port across VLANs (bit 11) */
1073 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group));
1074 } else {
1075 /* Enable mirroring to destination port */
1076 sw_w32((mirror->to_local_port << 4) | 1, RTL839X_MIR_CTRL(group));
1077 }
1078
1079 if (ingress && (priv->r->get_port_reg_be(priv->r->mir_spm(group)) & (1ULL << port))) {
1080 mutex_unlock(&priv->reg_mutex);
1081 return -EEXIST;
1082 }
1083 if ((!ingress) && (priv->r->get_port_reg_be(priv->r->mir_dpm(group)) & (1ULL << port))) {
1084 mutex_unlock(&priv->reg_mutex);
1085 return -EEXIST;
1086 }
1087
1088 if (ingress)
1089 priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_spm(group));
1090 else
1091 priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_dpm(group));
1092
1093 priv->mirror_group_ports[group] = mirror->to_local_port;
1094 mutex_unlock(&priv->reg_mutex);
1095 return 0;
1096 }
1097
1098 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1099 struct dsa_mall_mirror_tc_entry *mirror)
1100 {
1101 int group = 0;
1102 struct rtl838x_switch_priv *priv = ds->priv;
1103
1104 pr_debug("In %s\n", __func__);
1105 for (group = 0; group < 4; group++) {
1106 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1107 break;
1108 }
1109 if (group >= 4)
1110 return;
1111
1112 mutex_lock(&priv->reg_mutex);
1113 if (mirror->ingress) {
1114 /* Ingress, clear source port matrix */
1115 priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_spm(group));
1116 } else {
1117 /* Egress, clear destination port matrix */
1118 priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_dpm(group));
1119 }
1120
1121 if (!(sw_r32(priv->r->mir_spm(group)) || sw_r32(priv->r->mir_dpm(group)))) {
1122 priv->mirror_group_ports[group] = -1;
1123 sw_w32(0, priv->r->mir_ctrl(group));
1124 }
1125
1126 mutex_unlock(&priv->reg_mutex);
1127 }
1128
1129 const struct dsa_switch_ops rtl83xx_switch_ops = {
1130 .get_tag_protocol = rtl83xx_get_tag_protocol,
1131 .setup = rtl83xx_setup,
1132
1133 .phy_read = rtl83xx_dsa_phy_read,
1134 .phy_write = rtl83xx_dsa_phy_write,
1135
1136 .phylink_validate = rtl83xx_phylink_validate,
1137 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1138 .phylink_mac_config = rtl83xx_phylink_mac_config,
1139 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1140 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1141
1142 .get_strings = rtl83xx_get_strings,
1143 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1144 .get_sset_count = rtl83xx_get_sset_count,
1145
1146 .port_enable = rtl83xx_port_enable,
1147 .port_disable = rtl83xx_port_disable,
1148
1149 .get_mac_eee = rtl83xx_get_mac_eee,
1150 .set_mac_eee = rtl83xx_set_mac_eee,
1151
1152 .set_ageing_time = rtl83xx_set_l2aging,
1153 .port_bridge_join = rtl83xx_port_bridge_join,
1154 .port_bridge_leave = rtl83xx_port_bridge_leave,
1155 .port_stp_state_set = rtl83xx_port_stp_state_set,
1156 .port_fast_age = rtl83xx_fast_age,
1157
1158 .port_vlan_filtering = rtl83xx_vlan_filtering,
1159 .port_vlan_prepare = rtl83xx_vlan_prepare,
1160 .port_vlan_add = rtl83xx_vlan_add,
1161 .port_vlan_del = rtl83xx_vlan_del,
1162
1163 .port_fdb_add = rtl83xx_port_fdb_add,
1164 .port_fdb_del = rtl83xx_port_fdb_del,
1165 .port_fdb_dump = rtl83xx_port_fdb_dump,
1166
1167 .port_mirror_add = rtl83xx_port_mirror_add,
1168 .port_mirror_del = rtl83xx_port_mirror_del,
1169 };
1170
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