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[openwrt/staging/jow.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/etherdevice.h>
5 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7
8 #include "rtl83xx.h"
9
10 extern struct rtl83xx_soc_info soc_info;
11
12 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
13 {
14 mutex_lock(&priv->reg_mutex);
15
16 /* Enable statistics module: all counters plus debug.
17 * On RTL839x all counters are enabled by default
18 */
19 if (priv->family_id == RTL8380_FAMILY_ID)
20 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
21
22 /* Reset statistics counters */
23 sw_w32_mask(0, 1, priv->r->stat_rst);
24
25 mutex_unlock(&priv->reg_mutex);
26 }
27
28 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
29 {
30 u64 v = 0;
31
32 msleep(1000);
33 /* Enable all ports with a PHY, including the SFP-ports */
34 for (int i = 0; i < priv->cpu_port; i++) {
35 if (priv->ports[i].phy)
36 v |= BIT_ULL(i);
37 }
38
39 pr_info("%s: %16llx\n", __func__, v);
40 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
41
42 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
45 else if(priv->family_id == RTL9300_FAMILY_ID)
46 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
47 }
48
49 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
50 MIB_DESC(2, 0xf8, "ifInOctets"),
51 MIB_DESC(2, 0xf0, "ifOutOctets"),
52 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
53 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
54 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
55 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
56 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
57 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
58 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
59 MIB_DESC(1, 0xd0, "ifOutDiscards"),
60 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
61 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
62 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
63 MIB_DESC(1, 0xc0, ".3LateCollisions"),
64 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
65 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
66 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
67 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
68 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
69 MIB_DESC(1, 0xa8, "DropEvents"),
70 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
71 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
72 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
73 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
74 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
75 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
76 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
77 MIB_DESC(1, 0x88, "rx_OversizePkts"),
78 MIB_DESC(1, 0x84, "Fragments"),
79 MIB_DESC(1, 0x80, "Jabbers"),
80 MIB_DESC(1, 0x7c, "Collisions"),
81 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
82 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
83 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
85 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
87 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
89 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
91 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
92 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
93 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
95 MIB_DESC(1, 0x40, "rxMacDiscards")
96 };
97
98
99 /* DSA callbacks */
100
101
102 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
103 int port,
104 enum dsa_tag_protocol mprot)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 /* Initialize all VLANS */
113 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
114 {
115 struct rtl838x_vlan_info info;
116
117 pr_info("In %s\n", __func__);
118
119 priv->r->vlan_profile_setup(0);
120 priv->r->vlan_profile_setup(1);
121 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
122 priv->r->vlan_profile_dump(0);
123
124 info.fid = 0; /* Default Forwarding ID / MSTI */
125 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
126 info.hash_mc_fid = false; /* Do the same for Multicast packets */
127 info.profile_id = 0; /* Use default Vlan Profile 0 */
128 info.tagged_ports = 0; /* Initially no port members */
129 if (priv->family_id == RTL9310_FAMILY_ID) {
130 info.if_id = 0;
131 info.multicast_grp_mask = 0;
132 info.l2_tunnel_list_id = -1;
133 }
134
135 /* Initialize all vlans 0-4095 */
136 for (int i = 0; i < MAX_VLANS; i ++)
137 priv->r->vlan_set_tagged(i, &info);
138
139 /* reset PVIDs; defaults to 1 on reset */
140 for (int i = 0; i <= priv->ds->num_ports; i++) {
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
142 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
145 }
146
147 /* Set forwarding action based on inner VLAN tag */
148 for (int i = 0; i < priv->cpu_port; i++)
149 priv->r->vlan_fwd_on_inner(i, true);
150 }
151
152 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
153 {
154 for (int i = 0; i < priv->cpu_port; i++)
155 priv->r->set_receive_management_action(i, BPDU, TRAP2CPU);
156 }
157
158 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
159 int port, bool enable)
160 {
161 int shift = SALRN_PORT_SHIFT(port);
162 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
163
164 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
165 priv->r->l2_port_new_salrn(port));
166 }
167
168 static int rtl83xx_setup(struct dsa_switch *ds)
169 {
170 struct rtl838x_switch_priv *priv = ds->priv;
171
172 pr_debug("%s called\n", __func__);
173
174 /* Disable MAC polling the PHY so that we can start configuration */
175 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
176
177 for (int i = 0; i < ds->num_ports; i++)
178 priv->ports[i].enable = false;
179 priv->ports[priv->cpu_port].enable = true;
180
181 /* Configure ports so they are disabled by default, but once enabled
182 * they will work in isolated mode (only traffic between port and CPU).
183 */
184 for (int i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
187 priv->r->traffic_set(i, BIT_ULL(i));
188 }
189 }
190 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
191
192 /* For standalone ports, forward packets even if a static fdb
193 * entry for the source address exists on another port.
194 */
195 if (priv->r->set_static_move_action) {
196 for (int i = 0; i <= priv->cpu_port; i++)
197 priv->r->set_static_move_action(i, true);
198 }
199
200 if (priv->family_id == RTL8380_FAMILY_ID)
201 rtl838x_print_matrix();
202 else
203 rtl839x_print_matrix();
204
205 rtl83xx_init_stats(priv);
206
207 rtl83xx_vlan_setup(priv);
208
209 rtl83xx_setup_bpdu_traps(priv);
210
211 ds->configure_vlan_while_not_filtering = true;
212
213 priv->r->l2_learning_setup();
214
215 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
216 ds->assisted_learning_on_cpu_port = true;
217
218 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
219 * 0: FWD, 1: DROP, 2: TRAP2CPU
220 */
221 if (priv->family_id == RTL8380_FAMILY_ID)
222 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
223 else
224 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
225
226 /* Enable MAC Polling PHY again */
227 rtl83xx_enable_phy_polling(priv);
228 pr_debug("Please wait until PHY is settled\n");
229 msleep(1000);
230 priv->r->pie_init(priv);
231
232 return 0;
233 }
234
235 static int rtl93xx_setup(struct dsa_switch *ds)
236 {
237 struct rtl838x_switch_priv *priv = ds->priv;
238
239 pr_info("%s called\n", __func__);
240
241 /* Disable MAC polling the PHY so that we can start configuration */
242 if (priv->family_id == RTL9300_FAMILY_ID)
243 sw_w32(0, RTL930X_SMI_POLL_CTRL);
244
245 if (priv->family_id == RTL9310_FAMILY_ID) {
246 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
247 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
248 }
249
250 /* Disable all ports except CPU port */
251 for (int i = 0; i < ds->num_ports; i++)
252 priv->ports[i].enable = false;
253 priv->ports[priv->cpu_port].enable = true;
254
255 /* Configure ports so they are disabled by default, but once enabled
256 * they will work in isolated mode (only traffic between port and CPU).
257 */
258 for (int i = 0; i < priv->cpu_port; i++) {
259 if (priv->ports[i].phy) {
260 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
261 priv->r->traffic_set(i, BIT_ULL(i));
262 }
263 }
264 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
265
266 rtl930x_print_matrix();
267
268 /* TODO: Initialize statistics */
269
270 rtl83xx_vlan_setup(priv);
271
272 ds->configure_vlan_while_not_filtering = true;
273
274 priv->r->l2_learning_setup();
275
276 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
277 ds->assisted_learning_on_cpu_port = true;
278
279 rtl83xx_enable_phy_polling(priv);
280
281 priv->r->pie_init(priv);
282
283 priv->r->led_init(priv);
284
285 return 0;
286 }
287
288 static int rtl93xx_get_sds(struct phy_device *phydev)
289 {
290 struct device *dev = &phydev->mdio.dev;
291 struct device_node *dn;
292 u32 sds_num;
293
294 if (!dev)
295 return -1;
296 if (dev->of_node) {
297 dn = dev->of_node;
298 if (of_property_read_u32(dn, "sds", &sds_num))
299 sds_num = -1;
300 } else {
301 dev_err(dev, "No DT node.\n");
302 return -1;
303 }
304
305 return sds_num;
306 }
307
308 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
309 unsigned long *supported,
310 struct phylink_link_state *state)
311 {
312 struct rtl838x_switch_priv *priv = ds->priv;
313 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
314
315 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
316
317 if (!phy_interface_mode_is_rgmii(state->interface) &&
318 state->interface != PHY_INTERFACE_MODE_NA &&
319 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
320 state->interface != PHY_INTERFACE_MODE_MII &&
321 state->interface != PHY_INTERFACE_MODE_REVMII &&
322 state->interface != PHY_INTERFACE_MODE_GMII &&
323 state->interface != PHY_INTERFACE_MODE_QSGMII &&
324 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
325 state->interface != PHY_INTERFACE_MODE_SGMII) {
326 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
327 dev_err(ds->dev,
328 "Unsupported interface: %d for port %d\n",
329 state->interface, port);
330 return;
331 }
332
333 /* Allow all the expected bits */
334 phylink_set(mask, Autoneg);
335 phylink_set_port_modes(mask);
336 phylink_set(mask, Pause);
337 phylink_set(mask, Asym_Pause);
338
339 /* With the exclusion of MII and Reverse MII, we support Gigabit,
340 * including Half duplex
341 */
342 if (state->interface != PHY_INTERFACE_MODE_MII &&
343 state->interface != PHY_INTERFACE_MODE_REVMII) {
344 phylink_set(mask, 1000baseT_Full);
345 phylink_set(mask, 1000baseT_Half);
346 }
347
348 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
349 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
350 phylink_set(mask, 1000baseX_Full);
351
352 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
353 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
354 phylink_set(mask, 1000baseX_Full);
355
356 phylink_set(mask, 10baseT_Half);
357 phylink_set(mask, 10baseT_Full);
358 phylink_set(mask, 100baseT_Half);
359 phylink_set(mask, 100baseT_Full);
360
361 bitmap_and(supported, supported, mask,
362 __ETHTOOL_LINK_MODE_MASK_NBITS);
363 bitmap_and(state->advertising, state->advertising, mask,
364 __ETHTOOL_LINK_MODE_MASK_NBITS);
365 }
366
367 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
368 unsigned long *supported,
369 struct phylink_link_state *state)
370 {
371 struct rtl838x_switch_priv *priv = ds->priv;
372 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
373
374 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
375 phy_modes(state->interface));
376
377 if (!phy_interface_mode_is_rgmii(state->interface) &&
378 state->interface != PHY_INTERFACE_MODE_NA &&
379 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
380 state->interface != PHY_INTERFACE_MODE_MII &&
381 state->interface != PHY_INTERFACE_MODE_REVMII &&
382 state->interface != PHY_INTERFACE_MODE_GMII &&
383 state->interface != PHY_INTERFACE_MODE_QSGMII &&
384 state->interface != PHY_INTERFACE_MODE_XGMII &&
385 state->interface != PHY_INTERFACE_MODE_HSGMII &&
386 state->interface != PHY_INTERFACE_MODE_10GBASER &&
387 state->interface != PHY_INTERFACE_MODE_10GKR &&
388 state->interface != PHY_INTERFACE_MODE_USXGMII &&
389 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
390 state->interface != PHY_INTERFACE_MODE_SGMII) {
391 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
392 dev_err(ds->dev,
393 "Unsupported interface: %d for port %d\n",
394 state->interface, port);
395 return;
396 }
397
398 /* Allow all the expected bits */
399 phylink_set(mask, Autoneg);
400 phylink_set_port_modes(mask);
401 phylink_set(mask, Pause);
402 phylink_set(mask, Asym_Pause);
403
404 /* With the exclusion of MII and Reverse MII, we support Gigabit,
405 * including Half duplex
406 */
407 if (state->interface != PHY_INTERFACE_MODE_MII &&
408 state->interface != PHY_INTERFACE_MODE_REVMII) {
409 phylink_set(mask, 1000baseT_Full);
410 phylink_set(mask, 1000baseT_Half);
411 }
412
413 /* Internal phys of the RTL93xx family provide 10G */
414 if (priv->ports[port].phy_is_integrated &&
415 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
416 phylink_set(mask, 1000baseX_Full);
417 } else if (priv->ports[port].phy_is_integrated) {
418 phylink_set(mask, 1000baseX_Full);
419 phylink_set(mask, 10000baseKR_Full);
420 phylink_set(mask, 10000baseSR_Full);
421 phylink_set(mask, 10000baseCR_Full);
422 }
423 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
424 phylink_set(mask, 1000baseX_Full);
425 phylink_set(mask, 1000baseT_Full);
426 phylink_set(mask, 10000baseKR_Full);
427 phylink_set(mask, 10000baseT_Full);
428 phylink_set(mask, 10000baseSR_Full);
429 phylink_set(mask, 10000baseCR_Full);
430 }
431
432 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
433 phylink_set(mask, 2500baseT_Full);
434 phylink_set(mask, 5000baseT_Full);
435 phylink_set(mask, 10000baseT_Full);
436 }
437
438 phylink_set(mask, 10baseT_Half);
439 phylink_set(mask, 10baseT_Full);
440 phylink_set(mask, 100baseT_Half);
441 phylink_set(mask, 100baseT_Full);
442
443 bitmap_and(supported, supported, mask,
444 __ETHTOOL_LINK_MODE_MASK_NBITS);
445 bitmap_and(state->advertising, state->advertising, mask,
446 __ETHTOOL_LINK_MODE_MASK_NBITS);
447 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
448 }
449
450 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
451 struct phylink_link_state *state)
452 {
453 struct rtl838x_switch_priv *priv = ds->priv;
454 u64 speed;
455 u64 link;
456
457 if (port < 0 || port > priv->cpu_port)
458 return -EINVAL;
459
460 state->link = 0;
461 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
462 if (link & BIT_ULL(port))
463 state->link = 1;
464 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
465
466 state->duplex = 0;
467 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
468 state->duplex = 1;
469
470 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
471 speed >>= (port % 16) << 1;
472 switch (speed & 0x3) {
473 case 0:
474 state->speed = SPEED_10;
475 break;
476 case 1:
477 state->speed = SPEED_100;
478 break;
479 case 2:
480 state->speed = SPEED_1000;
481 break;
482 case 3:
483 if (priv->family_id == RTL9300_FAMILY_ID
484 && (port == 24 || port == 26)) /* Internal serdes */
485 state->speed = SPEED_2500;
486 else
487 state->speed = SPEED_100; /* Is in fact 500Mbit */
488 }
489
490 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
491 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
492 state->pause |= MLO_PAUSE_RX;
493 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
494 state->pause |= MLO_PAUSE_TX;
495
496 return 1;
497 }
498
499 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
500 struct phylink_link_state *state)
501 {
502 struct rtl838x_switch_priv *priv = ds->priv;
503 u64 speed;
504 u64 link;
505 u64 media;
506
507 if (port < 0 || port > priv->cpu_port)
508 return -EINVAL;
509
510 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
511 * state needs to be read twice in order to read a correct result.
512 * This would not be necessary for ports connected e.g. to RTL8218D
513 * PHYs.
514 */
515 state->link = 0;
516 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
517 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
518 if (link & BIT_ULL(port))
519 state->link = 1;
520
521 if (priv->family_id == RTL9310_FAMILY_ID)
522 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
523
524 if (priv->family_id == RTL9300_FAMILY_ID)
525 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
526
527 if (media & BIT_ULL(port))
528 state->link = 1;
529
530 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
531 link & BIT_ULL(port), media);
532
533 state->duplex = 0;
534 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
535 state->duplex = 1;
536
537 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
538 speed >>= (port % 8) << 2;
539 switch (speed & 0xf) {
540 case 0:
541 state->speed = SPEED_10;
542 break;
543 case 1:
544 state->speed = SPEED_100;
545 break;
546 case 2:
547 case 7:
548 state->speed = SPEED_1000;
549 break;
550 case 4:
551 state->speed = SPEED_10000;
552 break;
553 case 5:
554 case 8:
555 state->speed = SPEED_2500;
556 break;
557 case 6:
558 state->speed = SPEED_5000;
559 break;
560 default:
561 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
562 }
563
564 if (priv->family_id == RTL9310_FAMILY_ID
565 && (port >= 52 && port <= 55)) { /* Internal serdes */
566 state->speed = SPEED_10000;
567 state->link = 1;
568 state->duplex = 1;
569 }
570
571 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
572 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
573 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
574 state->pause |= MLO_PAUSE_RX;
575 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
576 state->pause |= MLO_PAUSE_TX;
577
578 return 1;
579 }
580
581 static void rtl83xx_config_interface(int port, phy_interface_t interface)
582 {
583 u32 old, int_shift, sds_shift;
584
585 switch (port) {
586 case 24:
587 int_shift = 0;
588 sds_shift = 5;
589 break;
590 case 26:
591 int_shift = 3;
592 sds_shift = 0;
593 break;
594 default:
595 return;
596 }
597
598 old = sw_r32(RTL838X_SDS_MODE_SEL);
599 switch (interface) {
600 case PHY_INTERFACE_MODE_1000BASEX:
601 if ((old >> sds_shift & 0x1f) == 4)
602 return;
603 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
604 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
605 break;
606 case PHY_INTERFACE_MODE_SGMII:
607 if ((old >> sds_shift & 0x1f) == 2)
608 return;
609 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
610 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
611 break;
612 default:
613 return;
614 }
615 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
616 }
617
618 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
619 unsigned int mode,
620 const struct phylink_link_state *state)
621 {
622 struct rtl838x_switch_priv *priv = ds->priv;
623 u32 reg;
624 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
625
626 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
627
628 if (port == priv->cpu_port) {
629 /* Set Speed, duplex, flow control
630 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
631 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
632 * | MEDIA_SEL
633 */
634 if (priv->family_id == RTL8380_FAMILY_ID) {
635 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
636 /* allow CRC errors on CPU-port */
637 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
638 } else {
639 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
640 }
641 return;
642 }
643
644 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
645 /* Auto-Negotiation does not work for MAC in RTL8390 */
646 if (priv->family_id == RTL8380_FAMILY_ID) {
647 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
648 pr_debug("PHY autonegotiates\n");
649 reg |= RTL838X_NWAY_EN;
650 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
651 rtl83xx_config_interface(port, state->interface);
652 return;
653 }
654 }
655
656 if (mode != MLO_AN_FIXED)
657 pr_debug("Fixed state.\n");
658
659 /* Clear id_mode_dis bit, and the existing port mode, let
660 * RGMII_MODE_EN bet set by mac_link_{up,down} */
661 if (priv->family_id == RTL8380_FAMILY_ID) {
662 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
663 if (state->pause & MLO_PAUSE_TXRX_MASK) {
664 if (state->pause & MLO_PAUSE_TX)
665 reg |= RTL838X_TX_PAUSE_EN;
666 reg |= RTL838X_RX_PAUSE_EN;
667 }
668 } else if (priv->family_id == RTL8390_FAMILY_ID) {
669 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
670 if (state->pause & MLO_PAUSE_TXRX_MASK) {
671 if (state->pause & MLO_PAUSE_TX)
672 reg |= RTL839X_TX_PAUSE_EN;
673 reg |= RTL839X_RX_PAUSE_EN;
674 }
675 }
676
677
678 reg &= ~(3 << speed_bit);
679 switch (state->speed) {
680 case SPEED_1000:
681 reg |= 2 << speed_bit;
682 break;
683 case SPEED_100:
684 reg |= 1 << speed_bit;
685 break;
686 default:
687 break; /* Ignore, including 10MBit which has a speed value of 0 */
688 }
689
690 if (priv->family_id == RTL8380_FAMILY_ID) {
691 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
692 if (state->link)
693 reg |= RTL838X_FORCE_LINK_EN;
694 if (state->duplex == RTL838X_DUPLEX_MODE)
695 reg |= RTL838X_DUPLEX_MODE;
696 } else if (priv->family_id == RTL8390_FAMILY_ID) {
697 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
698 if (state->link)
699 reg |= RTL839X_FORCE_LINK_EN;
700 if (state->duplex == RTL839X_DUPLEX_MODE)
701 reg |= RTL839X_DUPLEX_MODE;
702 }
703
704 /* LAG members must use DUPLEX and we need to enable the link */
705 if (priv->lagmembers & BIT_ULL(port)) {
706 switch(priv->family_id) {
707 case RTL8380_FAMILY_ID:
708 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
709 break;
710 case RTL8390_FAMILY_ID:
711 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
712 break;
713 }
714 }
715
716 /* Disable AN */
717 if (priv->family_id == RTL8380_FAMILY_ID)
718 reg &= ~RTL838X_NWAY_EN;
719 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
720 }
721
722 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
723 unsigned int mode,
724 const struct phylink_link_state *state)
725 {
726 struct rtl838x_switch_priv *priv = ds->priv;
727 int sds_num;
728 u32 reg, band;
729
730 sds_num = priv->ports[port].sds_num;
731 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
732
733 switch (state->interface) {
734 case PHY_INTERFACE_MODE_HSGMII:
735 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
736 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
737 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
738 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
739 break;
740 case PHY_INTERFACE_MODE_1000BASEX:
741 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
742 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
743 break;
744 case PHY_INTERFACE_MODE_XGMII:
745 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
746 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
747 break;
748 case PHY_INTERFACE_MODE_10GBASER:
749 case PHY_INTERFACE_MODE_10GKR:
750 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
751 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
752 break;
753 case PHY_INTERFACE_MODE_USXGMII:
754 /* Translates to MII_USXGMII_10GSXGMII */
755 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
756 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
757 break;
758 case PHY_INTERFACE_MODE_SGMII:
759 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
760 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
761 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
762 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
763 break;
764 case PHY_INTERFACE_MODE_QSGMII:
765 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
766 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
767 break;
768 default:
769 pr_err("%s: unknown serdes mode: %s\n",
770 __func__, phy_modes(state->interface));
771 return;
772 }
773
774 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
775 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
776
777 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
778
779 reg &= ~(0xf << 12);
780 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
781
782 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
783
784 if (priv->lagmembers & BIT_ULL(port))
785 reg |= RTL931X_DUPLEX_MODE;
786
787 if (state->duplex == DUPLEX_FULL)
788 reg |= RTL931X_DUPLEX_MODE;
789
790 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
791
792 }
793
794 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
795 unsigned int mode,
796 const struct phylink_link_state *state)
797 {
798 struct rtl838x_switch_priv *priv = ds->priv;
799 int sds_num, sds_mode;
800 u32 reg;
801
802 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
803 port, mode, phy_modes(state->interface), state->speed, state->link);
804
805 /* Nothing to be done for the CPU-port */
806 if (port == priv->cpu_port)
807 return;
808
809 if (priv->family_id == RTL9310_FAMILY_ID)
810 return rtl931x_phylink_mac_config(ds, port, mode, state);
811
812 sds_num = priv->ports[port].sds_num;
813 pr_info("%s SDS is %d\n", __func__, sds_num);
814 if (sds_num >= 0) {
815 switch (state->interface) {
816 case PHY_INTERFACE_MODE_HSGMII:
817 sds_mode = 0x12;
818 break;
819 case PHY_INTERFACE_MODE_1000BASEX:
820 sds_mode = 0x04;
821 break;
822 case PHY_INTERFACE_MODE_XGMII:
823 sds_mode = 0x10;
824 break;
825 case PHY_INTERFACE_MODE_10GBASER:
826 case PHY_INTERFACE_MODE_10GKR:
827 sds_mode = 0x1b; /* 10G 1000X Auto */
828 break;
829 case PHY_INTERFACE_MODE_USXGMII:
830 sds_mode = 0x0d;
831 break;
832 default:
833 pr_err("%s: unknown serdes mode: %s\n",
834 __func__, phy_modes(state->interface));
835 return;
836 }
837 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
838 rtl9300_serdes_setup(sds_num, state->interface);
839 }
840
841 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
842 reg &= ~(0xf << 3);
843
844 switch (state->speed) {
845 case SPEED_10000:
846 reg |= 4 << 3;
847 break;
848 case SPEED_5000:
849 reg |= 6 << 3;
850 break;
851 case SPEED_2500:
852 reg |= 5 << 3;
853 break;
854 case SPEED_1000:
855 reg |= 2 << 3;
856 break;
857 case SPEED_100:
858 reg |= 1 << 3;
859 break;
860 default:
861 /* Also covers 10M */
862 break;
863 }
864
865 if (state->link)
866 reg |= RTL930X_FORCE_LINK_EN;
867
868 if (priv->lagmembers & BIT_ULL(port))
869 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
870
871 if (state->duplex == DUPLEX_FULL)
872 reg |= RTL930X_DUPLEX_MODE;
873
874 if (priv->ports[port].phy_is_integrated)
875 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
876 else
877 reg |= RTL930X_FORCE_EN;
878
879 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
880 }
881
882 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
883 unsigned int mode,
884 phy_interface_t interface)
885 {
886 struct rtl838x_switch_priv *priv = ds->priv;
887
888 /* Stop TX/RX to port */
889 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
890
891 /* No longer force link */
892 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
893 }
894
895 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
896 unsigned int mode,
897 phy_interface_t interface)
898 {
899 struct rtl838x_switch_priv *priv = ds->priv;
900 u32 v = 0;
901
902 /* Stop TX/RX to port */
903 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
904
905 /* No longer force link */
906 if (priv->family_id == RTL9300_FAMILY_ID)
907 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
908 else if (priv->family_id == RTL9310_FAMILY_ID)
909 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
910 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
911 }
912
913 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
914 unsigned int mode,
915 phy_interface_t interface,
916 struct phy_device *phydev,
917 int speed, int duplex,
918 bool tx_pause, bool rx_pause)
919 {
920 struct rtl838x_switch_priv *priv = ds->priv;
921 /* Restart TX/RX to port */
922 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
923 /* TODO: Set speed/duplex/pauses */
924 }
925
926 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
927 unsigned int mode,
928 phy_interface_t interface,
929 struct phy_device *phydev,
930 int speed, int duplex,
931 bool tx_pause, bool rx_pause)
932 {
933 struct rtl838x_switch_priv *priv = ds->priv;
934
935 /* Restart TX/RX to port */
936 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
937 /* TODO: Set speed/duplex/pauses */
938 }
939
940 static void rtl83xx_get_strings(struct dsa_switch *ds,
941 int port, u32 stringset, u8 *data)
942 {
943 if (stringset != ETH_SS_STATS)
944 return;
945
946 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
947 ethtool_puts(&data, rtl83xx_mib[i].name);
948 }
949
950 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
951 uint64_t *data)
952 {
953 struct rtl838x_switch_priv *priv = ds->priv;
954 const struct rtl83xx_mib_desc *mib;
955 u64 h;
956
957 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
958 mib = &rtl83xx_mib[i];
959
960 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
961 if (mib->size == 2) {
962 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
963 data[i] |= h << 32;
964 }
965 }
966 }
967
968 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
969 {
970 if (sset != ETH_SS_STATS)
971 return 0;
972
973 return ARRAY_SIZE(rtl83xx_mib);
974 }
975
976 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
977 {
978 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
979 u64 portmask;
980
981 if (mc_group >= MAX_MC_GROUPS - 1)
982 return -1;
983
984 set_bit(mc_group, priv->mc_group_bm);
985 portmask = BIT_ULL(port);
986 priv->r->write_mcast_pmask(mc_group, portmask);
987
988 return mc_group;
989 }
990
991 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
992 {
993 u64 portmask = priv->r->read_mcast_pmask(mc_group);
994
995 pr_debug("%s: %d\n", __func__, port);
996
997 portmask |= BIT_ULL(port);
998 priv->r->write_mcast_pmask(mc_group, portmask);
999
1000 return portmask;
1001 }
1002
1003 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1004 {
1005 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1006
1007 pr_debug("%s: %d\n", __func__, port);
1008
1009 portmask &= ~BIT_ULL(port);
1010 priv->r->write_mcast_pmask(mc_group, portmask);
1011 if (!portmask)
1012 clear_bit(mc_group, priv->mc_group_bm);
1013
1014 return portmask;
1015 }
1016
1017 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1018 struct phy_device *phydev)
1019 {
1020 struct rtl838x_switch_priv *priv = ds->priv;
1021 u64 v;
1022
1023 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1024 priv->ports[port].enable = true;
1025
1026 /* enable inner tagging on egress, do not keep any tags */
1027 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1028
1029 if (dsa_is_cpu_port(ds, port))
1030 return 0;
1031
1032 /* add port to switch mask of CPU_PORT */
1033 priv->r->traffic_enable(priv->cpu_port, port);
1034
1035 if (priv->is_lagmember[port]) {
1036 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1037 return 0;
1038 }
1039
1040 /* add all other ports in the same bridge to switch mask of port */
1041 v = priv->r->traffic_get(port);
1042 v |= priv->ports[port].pm;
1043 priv->r->traffic_set(port, v);
1044
1045 /* TODO: Figure out if this is necessary */
1046 if (priv->family_id == RTL9300_FAMILY_ID) {
1047 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1048 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1049 }
1050
1051 if (priv->ports[port].sds_num < 0)
1052 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1053
1054 return 0;
1055 }
1056
1057 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1058 {
1059 struct rtl838x_switch_priv *priv = ds->priv;
1060 u64 v;
1061
1062 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1063 /* you can only disable user ports */
1064 if (!dsa_is_user_port(ds, port))
1065 return;
1066
1067 /* BUG: This does not work on RTL931X */
1068 /* remove port from switch mask of CPU_PORT */
1069 priv->r->traffic_disable(priv->cpu_port, port);
1070
1071 /* remove all other ports in the same bridge from switch mask of port */
1072 v = priv->r->traffic_get(port);
1073 v &= ~priv->ports[port].pm;
1074 priv->r->traffic_set(port, v);
1075
1076 priv->ports[port].enable = false;
1077 }
1078
1079 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1080 struct ethtool_eee *e)
1081 {
1082 struct rtl838x_switch_priv *priv = ds->priv;
1083
1084 if (e->eee_enabled && !priv->eee_enabled) {
1085 pr_info("Globally enabling EEE\n");
1086 priv->r->init_eee(priv, true);
1087 }
1088
1089 priv->r->port_eee_set(priv, port, e->eee_enabled);
1090
1091 if (e->eee_enabled)
1092 pr_info("Enabled EEE for port %d\n", port);
1093 else
1094 pr_info("Disabled EEE for port %d\n", port);
1095
1096 return 0;
1097 }
1098
1099 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1100 struct ethtool_eee *e)
1101 {
1102 struct rtl838x_switch_priv *priv = ds->priv;
1103
1104 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1105
1106 priv->r->eee_port_ability(priv, e, port);
1107
1108 e->eee_enabled = priv->ports[port].eee_enabled;
1109
1110 e->eee_active = !!(e->advertised & e->lp_advertised);
1111
1112 return 0;
1113 }
1114
1115 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1116 struct ethtool_eee *e)
1117 {
1118 struct rtl838x_switch_priv *priv = ds->priv;
1119
1120 e->supported = SUPPORTED_100baseT_Full |
1121 SUPPORTED_1000baseT_Full |
1122 SUPPORTED_2500baseX_Full;
1123
1124 priv->r->eee_port_ability(priv, e, port);
1125
1126 e->eee_enabled = priv->ports[port].eee_enabled;
1127
1128 e->eee_active = !!(e->advertised & e->lp_advertised);
1129
1130 return 0;
1131 }
1132
1133 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1134 {
1135 struct rtl838x_switch_priv *priv = ds->priv;
1136
1137 priv->r->set_ageing_time(msec);
1138
1139 return 0;
1140 }
1141
1142 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1143 struct net_device *bridge)
1144 {
1145 struct rtl838x_switch_priv *priv = ds->priv;
1146 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1147
1148 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1149
1150 if (priv->is_lagmember[port]) {
1151 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1152 return 0;
1153 }
1154
1155 mutex_lock(&priv->reg_mutex);
1156 for (int i = 0; i < ds->num_ports; i++) {
1157 /* Add this port to the port matrix of the other ports in the
1158 * same bridge. If the port is disabled, port matrix is kept
1159 * and not being setup until the port becomes enabled.
1160 */
1161 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1162 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1163 continue;
1164 if (priv->ports[i].enable)
1165 priv->r->traffic_enable(i, port);
1166
1167 priv->ports[i].pm |= BIT_ULL(port);
1168 port_bitmap |= BIT_ULL(i);
1169 }
1170 }
1171
1172 /* Add all other ports to this port matrix. */
1173 if (priv->ports[port].enable) {
1174 priv->r->traffic_enable(priv->cpu_port, port);
1175 v = priv->r->traffic_get(port);
1176 v |= port_bitmap;
1177 priv->r->traffic_set(port, v);
1178 }
1179 priv->ports[port].pm |= port_bitmap;
1180
1181 if (priv->r->set_static_move_action)
1182 priv->r->set_static_move_action(port, false);
1183
1184 mutex_unlock(&priv->reg_mutex);
1185
1186 return 0;
1187 }
1188
1189 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1190 struct net_device *bridge)
1191 {
1192 struct rtl838x_switch_priv *priv = ds->priv;
1193 u64 port_bitmap = 0, v;
1194
1195 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1196 mutex_lock(&priv->reg_mutex);
1197 for (int i = 0; i < ds->num_ports; i++) {
1198 /* Remove this port from the port matrix of the other ports
1199 * in the same bridge. If the port is disabled, port matrix
1200 * is kept and not being setup until the port becomes enabled.
1201 * And the other port's port matrix cannot be broken when the
1202 * other port is still a VLAN-aware port.
1203 */
1204 if (dsa_is_user_port(ds, i) && i != port) {
1205 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1206 continue;
1207 if (priv->ports[i].enable)
1208 priv->r->traffic_disable(i, port);
1209
1210 priv->ports[i].pm &= ~BIT_ULL(port);
1211 port_bitmap |= BIT_ULL(i);
1212 }
1213 }
1214
1215 /* Remove all other ports from this port matrix. */
1216 if (priv->ports[port].enable) {
1217 v = priv->r->traffic_get(port);
1218 v &= ~port_bitmap;
1219 priv->r->traffic_set(port, v);
1220 }
1221 priv->ports[port].pm &= ~port_bitmap;
1222
1223 if (priv->r->set_static_move_action)
1224 priv->r->set_static_move_action(port, true);
1225
1226 mutex_unlock(&priv->reg_mutex);
1227 }
1228
1229 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1230 {
1231 u32 msti = 0;
1232 u32 port_state[4];
1233 int index, bit;
1234 int pos = port;
1235 struct rtl838x_switch_priv *priv = ds->priv;
1236 int n = priv->port_width << 1;
1237
1238 /* Ports above or equal CPU port can never be configured */
1239 if (port >= priv->cpu_port)
1240 return;
1241
1242 mutex_lock(&priv->reg_mutex);
1243
1244 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1245 * have 64 bit fields, 839x and 931x have 128 bit fields
1246 */
1247 if (priv->family_id == RTL8390_FAMILY_ID)
1248 pos += 12;
1249 if (priv->family_id == RTL9300_FAMILY_ID)
1250 pos += 3;
1251 if (priv->family_id == RTL9310_FAMILY_ID)
1252 pos += 8;
1253
1254 index = n - (pos >> 4) - 1;
1255 bit = (pos << 1) % 32;
1256
1257 priv->r->stp_get(priv, msti, port_state);
1258
1259 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1260 port_state[index] &= ~(3 << bit);
1261
1262 switch (state) {
1263 case BR_STATE_DISABLED: /* 0 */
1264 port_state[index] |= (0 << bit);
1265 break;
1266 case BR_STATE_BLOCKING: /* 4 */
1267 case BR_STATE_LISTENING: /* 1 */
1268 port_state[index] |= (1 << bit);
1269 break;
1270 case BR_STATE_LEARNING: /* 2 */
1271 port_state[index] |= (2 << bit);
1272 break;
1273 case BR_STATE_FORWARDING: /* 3 */
1274 port_state[index] |= (3 << bit);
1275 default:
1276 break;
1277 }
1278
1279 priv->r->stp_set(priv, msti, port_state);
1280
1281 mutex_unlock(&priv->reg_mutex);
1282 }
1283
1284 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1285 {
1286 struct rtl838x_switch_priv *priv = ds->priv;
1287 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1288
1289 pr_debug("FAST AGE port %d\n", port);
1290 mutex_lock(&priv->reg_mutex);
1291 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1292 * port fields:
1293 * 0-4: Replacing port
1294 * 5-9: Flushed/replaced port
1295 * 10-21: FVID
1296 * 22: Entry types: 1: dynamic, 0: also static
1297 * 23: Match flush port
1298 * 24: Match FVID
1299 * 25: Flush (0) or replace (1) L2 entries
1300 * 26: Status of action (1: Start, 0: Done)
1301 */
1302 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1303
1304 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1305
1306 mutex_unlock(&priv->reg_mutex);
1307 }
1308
1309 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1310 {
1311 struct rtl838x_switch_priv *priv = ds->priv;
1312
1313 pr_info("%s port %d\n", __func__, port);
1314 mutex_lock(&priv->reg_mutex);
1315 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1316
1317 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1318
1319 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1320
1321 mutex_unlock(&priv->reg_mutex);
1322 }
1323
1324 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1325 {
1326 struct rtl838x_switch_priv *priv = ds->priv;
1327
1328 if (priv->family_id == RTL9310_FAMILY_ID)
1329 return rtl931x_fast_age(ds, port);
1330
1331 pr_debug("FAST AGE port %d\n", port);
1332 mutex_lock(&priv->reg_mutex);
1333 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1334
1335 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1336
1337 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1338
1339 mutex_unlock(&priv->reg_mutex);
1340 }
1341
1342 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1343 bool vlan_filtering,
1344 struct netlink_ext_ack *extack)
1345 {
1346 struct rtl838x_switch_priv *priv = ds->priv;
1347
1348 pr_debug("%s: port %d\n", __func__, port);
1349 mutex_lock(&priv->reg_mutex);
1350
1351 if (vlan_filtering) {
1352 /* Enable ingress and egress filtering
1353 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1354 * the filter action:
1355 * 0: Always Forward
1356 * 1: Drop packet
1357 * 2: Trap packet to CPU port
1358 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1359 */
1360 if (port != priv->cpu_port)
1361 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1362
1363 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1364 } else {
1365 /* Disable ingress and egress filtering */
1366 if (port != priv->cpu_port)
1367 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1368
1369 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1370 }
1371
1372 /* Do we need to do something to the CPU-Port, too? */
1373 mutex_unlock(&priv->reg_mutex);
1374
1375 return 0;
1376 }
1377
1378 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1379 const struct switchdev_obj_port_vlan *vlan)
1380 {
1381 struct rtl838x_vlan_info info;
1382 struct rtl838x_switch_priv *priv = ds->priv;
1383
1384 priv->r->vlan_tables_read(0, &info);
1385
1386 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1387 info.tagged_ports, info.untagged_ports, info.profile_id,
1388 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1389
1390 priv->r->vlan_tables_read(1, &info);
1391 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1392 info.tagged_ports, info.untagged_ports, info.profile_id,
1393 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1394 priv->r->vlan_set_untagged(1, info.untagged_ports);
1395 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1396
1397 priv->r->vlan_set_tagged(1, &info);
1398 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1399
1400 return 0;
1401 }
1402
1403 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1404 int port, int pvid)
1405 {
1406 /* Set both inner and outer PVID of the port */
1407 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1408 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1409 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1410 PBVLAN_MODE_UNTAG_AND_PRITAG);
1411 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1412 PBVLAN_MODE_UNTAG_AND_PRITAG);
1413
1414 priv->ports[port].pvid = pvid;
1415 }
1416
1417 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1418 const struct switchdev_obj_port_vlan *vlan,
1419 struct netlink_ext_ack *extack)
1420 {
1421 struct rtl838x_vlan_info info;
1422 struct rtl838x_switch_priv *priv = ds->priv;
1423 int err;
1424
1425 pr_debug("%s port %d, vid %d, flags %x\n",
1426 __func__, port, vlan->vid, vlan->flags);
1427
1428 if (vlan->vid > 4095) {
1429 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1430 return -ENOTSUPP;
1431 }
1432
1433 err = rtl83xx_vlan_prepare(ds, port, vlan);
1434 if (err)
1435 return err;
1436
1437 mutex_lock(&priv->reg_mutex);
1438
1439 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1440 rtl83xx_vlan_set_pvid(priv, port, vlan->vid);
1441 else if (priv->ports[port].pvid == vlan->vid)
1442 rtl83xx_vlan_set_pvid(priv, port, 0);
1443
1444 /* Get port memberships of this vlan */
1445 priv->r->vlan_tables_read(vlan->vid, &info);
1446
1447 /* new VLAN? */
1448 if (!info.tagged_ports) {
1449 info.fid = 0;
1450 info.hash_mc_fid = false;
1451 info.hash_uc_fid = false;
1452 info.profile_id = 0;
1453 }
1454
1455 /* sanitize untagged_ports - must be a subset */
1456 if (info.untagged_ports & ~info.tagged_ports)
1457 info.untagged_ports = 0;
1458
1459 info.tagged_ports |= BIT_ULL(port);
1460 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1461 info.untagged_ports |= BIT_ULL(port);
1462 else
1463 info.untagged_ports &= ~BIT_ULL(port);
1464
1465 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1466 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1467
1468 priv->r->vlan_set_tagged(vlan->vid, &info);
1469 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1470
1471 mutex_unlock(&priv->reg_mutex);
1472
1473 return 0;
1474 }
1475
1476 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1477 const struct switchdev_obj_port_vlan *vlan)
1478 {
1479 struct rtl838x_vlan_info info;
1480 struct rtl838x_switch_priv *priv = ds->priv;
1481 u16 pvid;
1482
1483 pr_debug("%s: port %d, vid %d, flags %x\n",
1484 __func__, port, vlan->vid, vlan->flags);
1485
1486 if (vlan->vid > 4095) {
1487 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1488 return -ENOTSUPP;
1489 }
1490
1491 mutex_lock(&priv->reg_mutex);
1492 pvid = priv->ports[port].pvid;
1493
1494 /* Reset to default if removing the current PVID */
1495 if (vlan->vid == pvid) {
1496 rtl83xx_vlan_set_pvid(priv, port, 0);
1497 }
1498 /* Get port memberships of this vlan */
1499 priv->r->vlan_tables_read(vlan->vid, &info);
1500
1501 /* remove port from both tables */
1502 info.untagged_ports &= (~BIT_ULL(port));
1503 info.tagged_ports &= (~BIT_ULL(port));
1504
1505 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1506 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1507
1508 priv->r->vlan_set_tagged(vlan->vid, &info);
1509 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1510
1511 mutex_unlock(&priv->reg_mutex);
1512
1513 return 0;
1514 }
1515
1516 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1517 {
1518 memset(e, 0, sizeof(*e));
1519
1520 e->type = L2_UNICAST;
1521 e->valid = true;
1522
1523 e->age = 3;
1524 e->is_static = true;
1525
1526 e->port = port;
1527
1528 e->rvid = e->vid = vid;
1529 e->is_ip_mc = e->is_ipv6_mc = false;
1530 u64_to_ether_addr(mac, e->mac);
1531 }
1532
1533 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1534 {
1535 memset(e, 0, sizeof(*e));
1536
1537 e->type = L2_MULTICAST;
1538 e->valid = true;
1539
1540 e->mc_portmask_index = mc_group;
1541
1542 e->rvid = e->vid = vid;
1543 e->is_ip_mc = e->is_ipv6_mc = false;
1544 u64_to_ether_addr(mac, e->mac);
1545 }
1546
1547 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1548 * over the entries in the bucket until either a matching entry is found or an empty slot
1549 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1550 * when an empty slot was found and must exist is false, the index of the slot is returned
1551 * when no slots are available returns -1
1552 */
1553 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1554 bool must_exist, struct rtl838x_l2_entry *e)
1555 {
1556 int idx = -1;
1557 u32 key = priv->r->l2_hash_key(priv, seed);
1558 u64 entry;
1559
1560 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1561 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1562 for (int i = 0; i < priv->l2_bucket_size; i++) {
1563 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1564 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1565 if (must_exist && !e->valid)
1566 continue;
1567 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1568 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1569 break;
1570 }
1571 }
1572
1573 return idx;
1574 }
1575
1576 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1577 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1578 * when an empty slot was found the index of the slot is returned
1579 * when no slots are available returns -1
1580 */
1581 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1582 bool must_exist, struct rtl838x_l2_entry *e)
1583 {
1584 int idx = -1;
1585 u64 entry;
1586
1587 for (int i = 0; i < 64; i++) {
1588 entry = priv->r->read_cam(i, e);
1589 if (!must_exist && !e->valid) {
1590 if (idx < 0) /* First empty entry? */
1591 idx = i;
1592 break;
1593 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1594 pr_debug("Found entry in CAM\n");
1595 idx = i;
1596 break;
1597 }
1598 }
1599
1600 return idx;
1601 }
1602
1603 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1604 const unsigned char *addr, u16 vid)
1605 {
1606 struct rtl838x_switch_priv *priv = ds->priv;
1607 u64 mac = ether_addr_to_u64(addr);
1608 struct rtl838x_l2_entry e;
1609 int err = 0, idx;
1610 u64 seed = priv->r->l2_hash_seed(mac, vid);
1611
1612 if (priv->is_lagmember[port]) {
1613 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1614 return 0;
1615 }
1616
1617 mutex_lock(&priv->reg_mutex);
1618
1619 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1620
1621 /* Found an existing or empty entry */
1622 if (idx >= 0) {
1623 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1624 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1625 goto out;
1626 }
1627
1628 /* Hash buckets full, try CAM */
1629 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1630
1631 if (idx >= 0) {
1632 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1633 priv->r->write_cam(idx, &e);
1634 goto out;
1635 }
1636
1637 err = -ENOTSUPP;
1638
1639 out:
1640 mutex_unlock(&priv->reg_mutex);
1641
1642 return err;
1643 }
1644
1645 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1646 const unsigned char *addr, u16 vid)
1647 {
1648 struct rtl838x_switch_priv *priv = ds->priv;
1649 u64 mac = ether_addr_to_u64(addr);
1650 struct rtl838x_l2_entry e;
1651 int err = 0, idx;
1652 u64 seed = priv->r->l2_hash_seed(mac, vid);
1653
1654 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1655 mutex_lock(&priv->reg_mutex);
1656
1657 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1658
1659 if (idx >= 0) {
1660 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1661 e.valid = false;
1662 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1663 goto out;
1664 }
1665
1666 /* Check CAM for spillover from hash buckets */
1667 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1668
1669 if (idx >= 0) {
1670 e.valid = false;
1671 priv->r->write_cam(idx, &e);
1672 goto out;
1673 }
1674 err = -ENOENT;
1675
1676 out:
1677 mutex_unlock(&priv->reg_mutex);
1678
1679 return err;
1680 }
1681
1682 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1683 dsa_fdb_dump_cb_t *cb, void *data)
1684 {
1685 struct rtl838x_l2_entry e;
1686 struct rtl838x_switch_priv *priv = ds->priv;
1687
1688 mutex_lock(&priv->reg_mutex);
1689
1690 for (int i = 0; i < priv->fib_entries; i++) {
1691 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1692
1693 if (!e.valid)
1694 continue;
1695
1696 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1697 cb(e.mac, e.vid, e.is_static, data);
1698
1699 if (!((i + 1) % 64))
1700 cond_resched();
1701 }
1702
1703 for (int i = 0; i < 64; i++) {
1704 priv->r->read_cam(i, &e);
1705
1706 if (!e.valid)
1707 continue;
1708
1709 if (e.port == port)
1710 cb(e.mac, e.vid, e.is_static, data);
1711 }
1712
1713 mutex_unlock(&priv->reg_mutex);
1714
1715 return 0;
1716 }
1717
1718 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1719 const struct switchdev_obj_port_mdb *mdb)
1720 {
1721 struct rtl838x_switch_priv *priv = ds->priv;
1722 u64 mac = ether_addr_to_u64(mdb->addr);
1723 struct rtl838x_l2_entry e;
1724 int err = 0, idx;
1725 int vid = mdb->vid;
1726 u64 seed = priv->r->l2_hash_seed(mac, vid);
1727 int mc_group;
1728
1729 if (priv->id >= 0x9300)
1730 return -EOPNOTSUPP;
1731
1732 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1733
1734 if (priv->is_lagmember[port]) {
1735 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1736 return -EINVAL;
1737 }
1738
1739 mutex_lock(&priv->reg_mutex);
1740
1741 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1742
1743 /* Found an existing or empty entry */
1744 if (idx >= 0) {
1745 if (e.valid) {
1746 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1747 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1748 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1749 } else {
1750 pr_debug("New entry for seed %016llx\n", seed);
1751 mc_group = rtl83xx_mc_group_alloc(priv, port);
1752 if (mc_group < 0) {
1753 err = -ENOTSUPP;
1754 goto out;
1755 }
1756 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1757 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1758 }
1759 goto out;
1760 }
1761
1762 /* Hash buckets full, try CAM */
1763 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1764
1765 if (idx >= 0) {
1766 if (e.valid) {
1767 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1768 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1769 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1770 } else {
1771 pr_debug("New entry\n");
1772 mc_group = rtl83xx_mc_group_alloc(priv, port);
1773 if (mc_group < 0) {
1774 err = -ENOTSUPP;
1775 goto out;
1776 }
1777 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1778 priv->r->write_cam(idx, &e);
1779 }
1780 goto out;
1781 }
1782
1783 err = -ENOTSUPP;
1784
1785 out:
1786 mutex_unlock(&priv->reg_mutex);
1787 if (err)
1788 dev_err(ds->dev, "failed to add MDB entry\n");
1789
1790 return err;
1791 }
1792
1793 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1794 const struct switchdev_obj_port_mdb *mdb)
1795 {
1796 struct rtl838x_switch_priv *priv = ds->priv;
1797 u64 mac = ether_addr_to_u64(mdb->addr);
1798 struct rtl838x_l2_entry e;
1799 int err = 0, idx;
1800 int vid = mdb->vid;
1801 u64 seed = priv->r->l2_hash_seed(mac, vid);
1802 u64 portmask;
1803
1804 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1805
1806 if (priv->is_lagmember[port]) {
1807 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1808 return 0;
1809 }
1810
1811 mutex_lock(&priv->reg_mutex);
1812
1813 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1814
1815 if (idx >= 0) {
1816 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1817 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1818 if (!portmask) {
1819 e.valid = false;
1820 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1821 }
1822 goto out;
1823 }
1824
1825 /* Check CAM for spillover from hash buckets */
1826 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1827
1828 if (idx >= 0) {
1829 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1830 if (!portmask) {
1831 e.valid = false;
1832 priv->r->write_cam(idx, &e);
1833 }
1834 goto out;
1835 }
1836 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1837
1838 out:
1839 mutex_unlock(&priv->reg_mutex);
1840
1841 return err;
1842 }
1843
1844 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1845 struct dsa_mall_mirror_tc_entry *mirror,
1846 bool ingress)
1847 {
1848 /* We support 4 mirror groups, one destination port per group */
1849 int group;
1850 struct rtl838x_switch_priv *priv = ds->priv;
1851 int ctrl_reg, dpm_reg, spm_reg;
1852
1853 pr_debug("In %s\n", __func__);
1854
1855 for (group = 0; group < 4; group++) {
1856 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1857 break;
1858 }
1859 if (group >= 4) {
1860 for (group = 0; group < 4; group++) {
1861 if (priv->mirror_group_ports[group] < 0)
1862 break;
1863 }
1864 }
1865
1866 if (group >= 4)
1867 return -ENOSPC;
1868
1869 ctrl_reg = priv->r->mir_ctrl + group * 4;
1870 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1871 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1872
1873 pr_debug("Using group %d\n", group);
1874 mutex_lock(&priv->reg_mutex);
1875
1876 if (priv->family_id == RTL8380_FAMILY_ID) {
1877 /* Enable mirroring to port across VLANs (bit 11) */
1878 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1879 } else {
1880 /* Enable mirroring to destination port */
1881 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1882 }
1883
1884 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1885 mutex_unlock(&priv->reg_mutex);
1886 return -EEXIST;
1887 }
1888 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1889 mutex_unlock(&priv->reg_mutex);
1890 return -EEXIST;
1891 }
1892
1893 if (ingress)
1894 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1895 else
1896 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1897
1898 priv->mirror_group_ports[group] = mirror->to_local_port;
1899 mutex_unlock(&priv->reg_mutex);
1900
1901 return 0;
1902 }
1903
1904 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1905 struct dsa_mall_mirror_tc_entry *mirror)
1906 {
1907 int group = 0;
1908 struct rtl838x_switch_priv *priv = ds->priv;
1909 int ctrl_reg, dpm_reg, spm_reg;
1910
1911 pr_debug("In %s\n", __func__);
1912 for (group = 0; group < 4; group++) {
1913 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1914 break;
1915 }
1916 if (group >= 4)
1917 return;
1918
1919 ctrl_reg = priv->r->mir_ctrl + group * 4;
1920 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1921 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1922
1923 mutex_lock(&priv->reg_mutex);
1924 if (mirror->ingress) {
1925 /* Ingress, clear source port matrix */
1926 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1927 } else {
1928 /* Egress, clear destination port matrix */
1929 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1930 }
1931
1932 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1933 priv->mirror_group_ports[group] = -1;
1934 sw_w32(0, ctrl_reg);
1935 }
1936
1937 mutex_unlock(&priv->reg_mutex);
1938 }
1939
1940 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1941 {
1942 struct rtl838x_switch_priv *priv = ds->priv;
1943 unsigned long features = 0;
1944 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1945 if (priv->r->enable_learning)
1946 features |= BR_LEARNING;
1947 if (priv->r->enable_flood)
1948 features |= BR_FLOOD;
1949 if (priv->r->enable_mcast_flood)
1950 features |= BR_MCAST_FLOOD;
1951 if (priv->r->enable_bcast_flood)
1952 features |= BR_BCAST_FLOOD;
1953 if (flags.mask & ~(features))
1954 return -EINVAL;
1955
1956 return 0;
1957 }
1958
1959 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1960 {
1961 struct rtl838x_switch_priv *priv = ds->priv;
1962
1963 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1964 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1965 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1966
1967 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
1968 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
1969
1970 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
1971 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
1972
1973 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
1974 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
1975
1976 return 0;
1977 }
1978
1979 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1980 struct net_device *lag,
1981 struct netdev_lag_upper_info *info)
1982 {
1983 int id;
1984
1985 id = dsa_lag_id(ds->dst, lag);
1986 if (id < 0 || id >= ds->num_lag_ids)
1987 return false;
1988
1989 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1990 return false;
1991 }
1992 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
1993 return false;
1994
1995 return true;
1996 }
1997
1998 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
1999 {
2000 pr_debug("%s: %d\n", __func__, port);
2001 /* Nothing to be done... */
2002
2003 return 0;
2004 }
2005
2006 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2007 struct net_device *lag,
2008 struct netdev_lag_upper_info *info)
2009 {
2010 struct rtl838x_switch_priv *priv = ds->priv;
2011 int i, err = 0;
2012
2013 if (!rtl83xx_lag_can_offload(ds, lag, info))
2014 return -EOPNOTSUPP;
2015
2016 mutex_lock(&priv->reg_mutex);
2017
2018 for (i = 0; i < priv->n_lags; i++) {
2019 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2020 break;
2021 }
2022 if (port >= priv->cpu_port) {
2023 err = -EINVAL;
2024 goto out;
2025 }
2026 pr_info("port_lag_join: group %d, port %d\n",i, port);
2027 if (!priv->lag_devs[i])
2028 priv->lag_devs[i] = lag;
2029
2030 if (priv->lag_primary[i] == -1) {
2031 priv->lag_primary[i] = port;
2032 } else
2033 priv->is_lagmember[port] = 1;
2034
2035 priv->lagmembers |= (1ULL << port);
2036
2037 pr_debug("lag_members = %llX\n", priv->lagmembers);
2038 err = rtl83xx_lag_add(priv->ds, i, port, info);
2039 if (err) {
2040 err = -EINVAL;
2041 goto out;
2042 }
2043
2044 out:
2045 mutex_unlock(&priv->reg_mutex);
2046
2047 return err;
2048 }
2049
2050 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2051 struct net_device *lag)
2052 {
2053 int i, group = -1, err;
2054 struct rtl838x_switch_priv *priv = ds->priv;
2055
2056 mutex_lock(&priv->reg_mutex);
2057 for (i = 0; i < priv->n_lags; i++) {
2058 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2059 group = i;
2060 break;
2061 }
2062 }
2063
2064 if (group == -1) {
2065 pr_info("port_lag_leave: port %d is not a member\n", port);
2066 err = -EINVAL;
2067 goto out;
2068 }
2069
2070 if (port >= priv->cpu_port) {
2071 err = -EINVAL;
2072 goto out;
2073 }
2074 pr_info("port_lag_del: group %d, port %d\n",group, port);
2075 priv->lagmembers &=~ (1ULL << port);
2076 priv->lag_primary[i] = -1;
2077 priv->is_lagmember[port] = 0;
2078 pr_debug("lag_members = %llX\n", priv->lagmembers);
2079 err = rtl83xx_lag_del(priv->ds, group, port);
2080 if (err) {
2081 err = -EINVAL;
2082 goto out;
2083 }
2084 if (!priv->lags_port_members[i])
2085 priv->lag_devs[i] = NULL;
2086
2087 out:
2088 mutex_unlock(&priv->reg_mutex);
2089 return 0;
2090 }
2091
2092 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2093 {
2094 u32 val;
2095 u32 offset = 0;
2096 struct rtl838x_switch_priv *priv = ds->priv;
2097
2098 if ((phy_addr >= 24) &&
2099 (phy_addr <= 27) &&
2100 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2101 if (phy_addr == 26)
2102 offset = 0x100;
2103 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2104 return val;
2105 }
2106
2107 read_phy(phy_addr, 0, phy_reg, &val);
2108 return val;
2109 }
2110
2111 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2112 {
2113 u32 offset = 0;
2114 struct rtl838x_switch_priv *priv = ds->priv;
2115
2116 if ((phy_addr >= 24) &&
2117 (phy_addr <= 27) &&
2118 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2119 if (phy_addr == 26)
2120 offset = 0x100;
2121 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2122 return 0;
2123 }
2124 return write_phy(phy_addr, 0, phy_reg, val);
2125 }
2126
2127 const struct dsa_switch_ops rtl83xx_switch_ops = {
2128 .get_tag_protocol = rtl83xx_get_tag_protocol,
2129 .setup = rtl83xx_setup,
2130
2131 .phy_read = dsa_phy_read,
2132 .phy_write = dsa_phy_write,
2133
2134 .phylink_validate = rtl83xx_phylink_validate,
2135 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2136 .phylink_mac_config = rtl83xx_phylink_mac_config,
2137 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2138 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2139
2140 .get_strings = rtl83xx_get_strings,
2141 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2142 .get_sset_count = rtl83xx_get_sset_count,
2143
2144 .port_enable = rtl83xx_port_enable,
2145 .port_disable = rtl83xx_port_disable,
2146
2147 .get_mac_eee = rtl83xx_get_mac_eee,
2148 .set_mac_eee = rtl83xx_set_mac_eee,
2149
2150 .set_ageing_time = rtl83xx_set_ageing_time,
2151 .port_bridge_join = rtl83xx_port_bridge_join,
2152 .port_bridge_leave = rtl83xx_port_bridge_leave,
2153 .port_stp_state_set = rtl83xx_port_stp_state_set,
2154 .port_fast_age = rtl83xx_fast_age,
2155
2156 .port_vlan_filtering = rtl83xx_vlan_filtering,
2157 .port_vlan_add = rtl83xx_vlan_add,
2158 .port_vlan_del = rtl83xx_vlan_del,
2159
2160 .port_fdb_add = rtl83xx_port_fdb_add,
2161 .port_fdb_del = rtl83xx_port_fdb_del,
2162 .port_fdb_dump = rtl83xx_port_fdb_dump,
2163
2164 .port_mdb_add = rtl83xx_port_mdb_add,
2165 .port_mdb_del = rtl83xx_port_mdb_del,
2166
2167 .port_mirror_add = rtl83xx_port_mirror_add,
2168 .port_mirror_del = rtl83xx_port_mirror_del,
2169
2170 .port_lag_change = rtl83xx_port_lag_change,
2171 .port_lag_join = rtl83xx_port_lag_join,
2172 .port_lag_leave = rtl83xx_port_lag_leave,
2173
2174 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2175 .port_bridge_flags = rtl83xx_port_bridge_flags,
2176 };
2177
2178 const struct dsa_switch_ops rtl930x_switch_ops = {
2179 .get_tag_protocol = rtl83xx_get_tag_protocol,
2180 .setup = rtl93xx_setup,
2181
2182 .phy_read = dsa_phy_read,
2183 .phy_write = dsa_phy_write,
2184
2185 .phylink_validate = rtl93xx_phylink_validate,
2186 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2187 .phylink_mac_config = rtl93xx_phylink_mac_config,
2188 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2189 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2190
2191 .get_strings = rtl83xx_get_strings,
2192 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2193 .get_sset_count = rtl83xx_get_sset_count,
2194
2195 .port_enable = rtl83xx_port_enable,
2196 .port_disable = rtl83xx_port_disable,
2197
2198 .get_mac_eee = rtl93xx_get_mac_eee,
2199 .set_mac_eee = rtl83xx_set_mac_eee,
2200
2201 .set_ageing_time = rtl83xx_set_ageing_time,
2202 .port_bridge_join = rtl83xx_port_bridge_join,
2203 .port_bridge_leave = rtl83xx_port_bridge_leave,
2204 .port_stp_state_set = rtl83xx_port_stp_state_set,
2205 .port_fast_age = rtl930x_fast_age,
2206
2207 .port_vlan_filtering = rtl83xx_vlan_filtering,
2208 .port_vlan_add = rtl83xx_vlan_add,
2209 .port_vlan_del = rtl83xx_vlan_del,
2210
2211 .port_fdb_add = rtl83xx_port_fdb_add,
2212 .port_fdb_del = rtl83xx_port_fdb_del,
2213 .port_fdb_dump = rtl83xx_port_fdb_dump,
2214
2215 .port_mdb_add = rtl83xx_port_mdb_add,
2216 .port_mdb_del = rtl83xx_port_mdb_del,
2217
2218 .port_lag_change = rtl83xx_port_lag_change,
2219 .port_lag_join = rtl83xx_port_lag_join,
2220 .port_lag_leave = rtl83xx_port_lag_leave,
2221
2222 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2223 .port_bridge_flags = rtl83xx_port_bridge_flags,
2224 };
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