target/linux/ramips/patches-6.1/108-v6.3-PCI-mt7621-Delay-phy-ports-initialization.patch

   1 From 0cb2a8f3456ff1cc51d571e287a48e8fddc98ec2 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Sat, 31 Dec 2022 08:40:41 +0100
   4 Subject: PCI: mt7621: Delay phy ports initialization
   5
   6 Some devices like ZBT WE1326 and ZBT WF3526-P and some Netgear models need
   7 to delay phy port initialization after calling the mt7621_pcie_init_port()
   8 driver function to get into reliable boots for both warm and hard resets.
   9
  10 The delay required to detect the ports seems to be in the range [75-100]
  11 milliseconds.
  12
  13 If the ports are not detected the controller is not functional.
  14
  15 There is no datasheet or something similar to really understand why this
  16 extra delay is needed only for these devices and it is not for most of
  17 the boards that are built on mt7621 SoC.
  18
  19 This issue has been reported by openWRT community and the complete
  20 discussion is in [0]. The 100 milliseconds delay has been tested in all
  21 devices to validate it.
  22
  23 Add the extra 100 milliseconds delay to fix the issue.
  24
  25 [0]: https://github.com/openwrt/openwrt/pull/11220
  26
  27 Link: https://lore.kernel.org/r/20221231074041.264738-1-sergio.paracuellos@gmail.com
  28 Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver")
  29 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  30 Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
  31 ---
  32  drivers/pci/controller/pcie-mt7621.c | 2 ++
  33  1 file changed, 2 insertions(+)
  34
  35 --- a/drivers/pci/controller/pcie-mt7621.c
  36 +++ b/drivers/pci/controller/pcie-mt7621.c
  37 @@ -58,6 +58,7 @@
  38  #define PCIE_PORT_LINKUP               BIT(0)
  39  #define PCIE_PORT_CNT                  3
  40
  41 +#define INIT_PORTS_DELAY_MS            100
  42  #define PERST_DELAY_MS                 100
  43
  44  /**
  45 @@ -374,6 +375,7 @@ static int mt7621_pcie_init_ports(struct
  46                 }
  47         }
  48
  49 +       msleep(INIT_PORTS_DELAY_MS);
  50         mt7621_pcie_reset_ep_deassert(pcie);
  51
  52         tmp = NULL;