target/linux/ramips/patches-4.14/0043-spi-add-mt7621-support.patch

   1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 09:49:07 +0100
   4 Subject: [PATCH 43/53] spi: add mt7621 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8 Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d9e8610c85
   9
  10  drivers/spi/Kconfig      |    6 +
  11  drivers/spi/Makefile     |    1 +
  12  drivers/spi/spi-mt7621.c |  480 ++++++++++++++++++++++++++++++++++++++++++++++
  13  3 files changed, 487 insertions(+)
  14  create mode 100644 drivers/spi/spi-mt7621.c
  15
  16 --- a/drivers/spi/Kconfig
  17 +++ b/drivers/spi/Kconfig
  18 @@ -569,6 +569,12 @@ config SPI_RT2880
  19         help
  20           This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  21
  22 +config SPI_MT7621
  23 +       tristate "MediaTek MT7621 SPI Controller"
  24 +       depends on RALINK
  25 +       help
  26 +         This selects a driver for the MediaTek MT7621 SPI Controller.
  27 +
  28  config SPI_S3C24XX
  29         tristate "Samsung S3C24XX series SPI"
  30         depends on ARCH_S3C24XX
  31 --- a/drivers/spi/Makefile
  32 +++ b/drivers/spi/Makefile
  33 @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC)         += spi-mp
  34  obj-$(CONFIG_SPI_MPC52xx_PSC)          += spi-mpc52xx-psc.o
  35  obj-$(CONFIG_SPI_MPC52xx)              += spi-mpc52xx.o
  36  obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
  37 +obj-$(CONFIG_SPI_MT7621)               += spi-mt7621.o
  38  obj-$(CONFIG_SPI_MXS)                  += spi-mxs.o
  39  obj-$(CONFIG_SPI_NUC900)               += spi-nuc900.o
  40  obj-$(CONFIG_SPI_OC_TINY)              += spi-oc-tiny.o
  41 --- /dev/null
  42 +++ b/drivers/spi/spi-mt7621.c
  43 @@ -0,0 +1,515 @@
  44 +/*
  45 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  46 + *
  47 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  48 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  49 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  50 + *
  51 + * Some parts are based on spi-orion.c:
  52 + *   Author: Shadi Ammouri <shadi@marvell.com>
  53 + *   Copyright (C) 2007-2008 Marvell Ltd.
  54 + *
  55 + * This program is free software; you can redistribute it and/or modify
  56 + * it under the terms of the GNU General Public License version 2 as
  57 + * published by the Free Software Foundation.
  58 + */
  59 +
  60 +#include <linux/init.h>
  61 +#include <linux/module.h>
  62 +#include <linux/clk.h>
  63 +#include <linux/err.h>
  64 +#include <linux/delay.h>
  65 +#include <linux/io.h>
  66 +#include <linux/reset.h>
  67 +#include <linux/spi/spi.h>
  68 +#include <linux/of_device.h>
  69 +#include <linux/platform_device.h>
  70 +#include <linux/swab.h>
  71 +
  72 +#include <ralink_regs.h>
  73 +
  74 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
  75 +
  76 +#define DRIVER_NAME                    "spi-mt7621"
  77 +/* in usec */
  78 +#define RALINK_SPI_WAIT_MAX_LOOP       2000
  79 +
  80 +/* SPISTAT register bit field */
  81 +#define SPISTAT_BUSY                   BIT(0)
  82 +
  83 +#define MT7621_SPI_TRANS       0x00
  84 +#define SPITRANS_BUSY          BIT(16)
  85 +
  86 +#define MT7621_SPI_OPCODE      0x04
  87 +#define MT7621_SPI_DATA0       0x08
  88 +#define MT7621_SPI_DATA4       0x18
  89 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
  90 +#define SPI_CTL_START          BIT(8)
  91 +
  92 +#define MT7621_SPI_POLAR       0x38
  93 +#define MT7621_SPI_MASTER      0x28
  94 +#define MT7621_SPI_MOREBUF     0x2c
  95 +#define MT7621_SPI_SPACE       0x3c
  96 +
  97 +#define MT7621_CPHA            BIT(5)
  98 +#define MT7621_CPOL            BIT(4)
  99 +#define MT7621_LSB_FIRST       BIT(3)
 100 +
 101 +#define RT2880_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA |          \
 102 +                                SPI_LSB_FIRST | SPI_CS_HIGH)
 103 +
 104 +struct mt7621_spi;
 105 +
 106 +struct mt7621_spi {
 107 +       struct spi_master       *master;
 108 +       void __iomem            *base;
 109 +       unsigned int            sys_freq;
 110 +       unsigned int            speed;
 111 +       struct clk              *clk;
 112 +       int                     pending_write;
 113 +
 114 +       struct mt7621_spi_ops   *ops;
 115 +};
 116 +
 117 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
 118 +{
 119 +       return spi_master_get_devdata(spi->master);
 120 +}
 121 +
 122 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
 123 +{
 124 +       return ioread32(rs->base + reg);
 125 +}
 126 +
 127 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
 128 +{
 129 +       iowrite32(val, rs->base + reg);
 130 +}
 131 +
 132 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
 133 +{
 134 +       u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
 135 +
 136 +       master |= 7 << 29;
 137 +       master |= 1 << 2;
 138 +       if (duplex)
 139 +               master |= 1 << 10;
 140 +       else
 141 +               master &= ~(1 << 10);
 142 +
 143 +       mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
 144 +       rs->pending_write = 0;
 145 +}
 146 +
 147 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
 148 +{
 149 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 150 +       int cs = spi->chip_select;
 151 +       u32 polar = 0;
 152 +
 153 +       mt7621_spi_reset(rs, cs);
 154 +       if (enable)
 155 +               polar = BIT(cs);
 156 +       mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
 157 +}
 158 +
 159 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
 160 +{
 161 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 162 +       u32 rate;
 163 +       u32 reg;
 164 +
 165 +       dev_dbg(&spi->dev, "speed:%u\n", speed);
 166 +
 167 +       rate = DIV_ROUND_UP(rs->sys_freq, speed);
 168 +       dev_dbg(&spi->dev, "rate-1:%u\n", rate);
 169 +
 170 +       if (rate > 4097)
 171 +               return -EINVAL;
 172 +
 173 +       if (rate < 2)
 174 +               rate = 2;
 175 +
 176 +       reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
 177 +       reg &= ~(0xfff << 16);
 178 +       reg |= (rate - 2) << 16;
 179 +       rs->speed = speed;
 180 +
 181 +       reg &= ~MT7621_LSB_FIRST;
 182 +       if (spi->mode & SPI_LSB_FIRST)
 183 +               reg |= MT7621_LSB_FIRST;
 184 +
 185 +       reg &= ~(MT7621_CPHA | MT7621_CPOL);
 186 +       switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
 187 +       case SPI_MODE_0:
 188 +               break;
 189 +       case SPI_MODE_1:
 190 +               reg |= MT7621_CPHA;
 191 +               break;
 192 +       case SPI_MODE_2:
 193 +               reg |= MT7621_CPOL;
 194 +               break;
 195 +       case SPI_MODE_3:
 196 +               reg |= MT7621_CPOL | MT7621_CPHA;
 197 +               break;
 198 +       }
 199 +       mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
 200 +
 201 +       return 0;
 202 +}
 203 +
 204 +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
 205 +{
 206 +       int i;
 207 +
 208 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 209 +               u32 status;
 210 +
 211 +               status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 212 +               if ((status & SPITRANS_BUSY) == 0)
 213 +                       return 0;
 214 +               cpu_relax();
 215 +               udelay(1);
 216 +       }
 217 +
 218 +       return -ETIMEDOUT;
 219 +}
 220 +
 221 +static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
 222 +                                       int rx_len, u8 *buf)
 223 +{
 224 +       /* Combine with any pending write, and perform one or
 225 +        * more half-duplex transactions reading 'len' bytes.
 226 +        * Data to be written is already in MT7621_SPI_DATA*
 227 +        */
 228 +       int tx_len = rs->pending_write;
 229 +
 230 +       rs->pending_write = 0;
 231 +
 232 +       while (rx_len || tx_len) {
 233 +               int i;
 234 +               u32 val = (min(tx_len, 4) * 8) << 24;
 235 +               int rx = min(rx_len, 32);
 236 +
 237 +               if (tx_len > 4)
 238 +                       val |= (tx_len - 4) * 8;
 239 +               val |= (rx * 8) << 12;
 240 +               mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
 241 +
 242 +               tx_len = 0;
 243 +
 244 +               val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 245 +               val |= SPI_CTL_START;
 246 +               mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
 247 +
 248 +               mt7621_spi_wait_till_ready(rs);
 249 +
 250 +               for (i = 0; i < rx; i++) {
 251 +                       if ((i % 4) == 0)
 252 +                               val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
 253 +                       *buf++ = val & 0xff;
 254 +                       val >>= 8;
 255 +               }
 256 +               rx_len -= i;
 257 +       }
 258 +}
 259 +
 260 +static inline void mt7621_spi_flush(struct mt7621_spi *rs)
 261 +{
 262 +       mt7621_spi_read_half_duplex(rs, 0, NULL);
 263 +}
 264 +
 265 +static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
 266 +                                        int tx_len, const u8 *buf)
 267 +{
 268 +       int val = 0;
 269 +       int len = rs->pending_write;
 270 +
 271 +       if (len & 3) {
 272 +               val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
 273 +               if (len < 4) {
 274 +                       val <<= (4 - len) * 8;
 275 +                       val = swab32(val);
 276 +               }
 277 +       }
 278 +
 279 +       while (tx_len > 0) {
 280 +               if (len >= 36) {
 281 +                       rs->pending_write = len;
 282 +                       mt7621_spi_flush(rs);
 283 +                       len = 0;
 284 +               }
 285 +
 286 +               val |= *buf++ << (8 * (len & 3));
 287 +               len++;
 288 +               if ((len & 3) == 0) {
 289 +                       if (len == 4)
 290 +                               /* The byte-order of the opcode is weird! */
 291 +                               val = swab32(val);
 292 +                       mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
 293 +                       val = 0;
 294 +               }
 295 +               tx_len -= 1;
 296 +       }
 297 +       if (len & 3) {
 298 +               if (len < 4) {
 299 +                       val = swab32(val);
 300 +                       val >>= (4 - len) * 8;
 301 +               }
 302 +               mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
 303 +       }
 304 +       rs->pending_write = len;
 305 +}
 306 +
 307 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
 308 +                                          struct spi_message *m)
 309 +{
 310 +       struct mt7621_spi *rs = spi_master_get_devdata(master);
 311 +       struct spi_device *spi = m->spi;
 312 +       unsigned int speed = spi->max_speed_hz;
 313 +       struct spi_transfer *t = NULL;
 314 +       int status = 0;
 315 +
 316 +       mt7621_spi_wait_till_ready(rs);
 317 +
 318 +       list_for_each_entry(t, &m->transfers, transfer_list)
 319 +               if (t->speed_hz < speed)
 320 +                       speed = t->speed_hz;
 321 +
 322 +       if (mt7621_spi_prepare(spi, speed)) {
 323 +               status = -EIO;
 324 +               goto msg_done;
 325 +       }
 326 +
 327 +       mt7621_spi_set_cs(spi, 1);
 328 +       m->actual_length = 0;
 329 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 330 +               if (t->rx_buf)
 331 +                       mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
 332 +               else if (t->tx_buf)
 333 +                       mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
 334 +               m->actual_length += t->len;
 335 +       }
 336 +       mt7621_spi_flush(rs);
 337 +
 338 +       mt7621_spi_set_cs(spi, 0);
 339 +msg_done:
 340 +       m->status = status;
 341 +       spi_finalize_current_message(master);
 342 +
 343 +       return 0;
 344 +}
 345 +
 346 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
 347 +                                          struct spi_message *m)
 348 +{
 349 +       struct mt7621_spi *rs = spi_master_get_devdata(master);
 350 +       struct spi_device *spi = m->spi;
 351 +       unsigned int speed = spi->max_speed_hz;
 352 +       struct spi_transfer *t = NULL;
 353 +       int status = 0;
 354 +       int i, len = 0;
 355 +       int rx_len = 0;
 356 +       u32 data[9] = { 0 };
 357 +       u32 val = 0;
 358 +
 359 +       mt7621_spi_wait_till_ready(rs);
 360 +
 361 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 362 +               const u8 *buf = t->tx_buf;
 363 +
 364 +               if (t->rx_buf)
 365 +                       rx_len += t->len;
 366 +
 367 +               if (!buf)
 368 +                       continue;
 369 +
 370 +               if (WARN_ON(len + t->len > 16)) {
 371 +                       status = -EIO;
 372 +                       goto msg_done;
 373 +               }
 374 +
 375 +               for (i = 0; i < t->len; i++, len++)
 376 +                       data[len / 4] |= buf[i] << (8 * (len & 3));
 377 +               if (speed > t->speed_hz)
 378 +                       speed = t->speed_hz;
 379 +       }
 380 +
 381 +       if (WARN_ON(rx_len > 16)) {
 382 +               status = -EIO;
 383 +               goto msg_done;
 384 +       }
 385 +
 386 +       if (mt7621_spi_prepare(spi, speed)) {
 387 +               status = -EIO;
 388 +               goto msg_done;
 389 +       }
 390 +
 391 +       for (i = 0; i < len; i += 4)
 392 +               mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
 393 +
 394 +       val |= len * 8;
 395 +       val |= (rx_len * 8) << 12;
 396 +       mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
 397 +
 398 +       mt7621_spi_set_cs(spi, 1);
 399 +
 400 +       val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 401 +       val |= SPI_CTL_START;
 402 +       mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
 403 +
 404 +       mt7621_spi_wait_till_ready(rs);
 405 +
 406 +       mt7621_spi_set_cs(spi, 0);
 407 +
 408 +       for (i = 0; i < rx_len; i += 4)
 409 +               data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
 410 +
 411 +       m->actual_length = rx_len;
 412 +
 413 +       len = 0;
 414 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 415 +               u8 *buf = t->rx_buf;
 416 +
 417 +               if (!buf)
 418 +                       continue;
 419 +
 420 +               for (i = 0; i < t->len; i++, len++)
 421 +                       buf[i] = data[len / 4] >> (8 * (len & 3));
 422 +       }
 423 +
 424 +msg_done:
 425 +       m->status = status;
 426 +       spi_finalize_current_message(master);
 427 +
 428 +       return 0;
 429 +}
 430 +
 431 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
 432 +                                          struct spi_message *m)
 433 +{
 434 +       struct spi_device *spi = m->spi;
 435 +       int cs = spi->chip_select;
 436 +
 437 +       if (cs)
 438 +               return mt7621_spi_transfer_full_duplex(master, m);
 439 +       return mt7621_spi_transfer_half_duplex(master, m);
 440 +}
 441 +
 442 +static int mt7621_spi_setup(struct spi_device *spi)
 443 +{
 444 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 445 +
 446 +       if ((spi->max_speed_hz == 0) ||
 447 +               (spi->max_speed_hz > (rs->sys_freq / 2)))
 448 +               spi->max_speed_hz = (rs->sys_freq / 2);
 449 +
 450 +       if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
 451 +               dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
 452 +                       spi->max_speed_hz);
 453 +               return -EINVAL;
 454 +       }
 455 +
 456 +       return 0;
 457 +}
 458 +
 459 +static const struct of_device_id mt7621_spi_match[] = {
 460 +       { .compatible = "ralink,mt7621-spi" },
 461 +       {},
 462 +};
 463 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
 464 +
 465 +static int mt7621_spi_probe(struct platform_device *pdev)
 466 +{
 467 +       const struct of_device_id *match;
 468 +       struct spi_master *master;
 469 +       struct mt7621_spi *rs;
 470 +       void __iomem *base;
 471 +       struct resource *r;
 472 +       int status = 0;
 473 +       struct clk *clk;
 474 +       struct mt7621_spi_ops *ops;
 475 +
 476 +       match = of_match_device(mt7621_spi_match, &pdev->dev);
 477 +       if (!match)
 478 +               return -EINVAL;
 479 +       ops = (struct mt7621_spi_ops *)match->data;
 480 +
 481 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 482 +       base = devm_ioremap_resource(&pdev->dev, r);
 483 +       if (IS_ERR(base))
 484 +               return PTR_ERR(base);
 485 +
 486 +       clk = devm_clk_get(&pdev->dev, NULL);
 487 +       if (IS_ERR(clk)) {
 488 +               dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 489 +                       status);
 490 +               return PTR_ERR(clk);
 491 +       }
 492 +
 493 +       status = clk_prepare_enable(clk);
 494 +       if (status)
 495 +               return status;
 496 +
 497 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 498 +       if (master == NULL) {
 499 +               dev_info(&pdev->dev, "master allocation failed\n");
 500 +               return -ENOMEM;
 501 +       }
 502 +
 503 +       master->mode_bits = RT2880_SPI_MODE_BITS;
 504 +
 505 +       master->setup = mt7621_spi_setup;
 506 +       master->transfer_one_message = mt7621_spi_transfer_one_message;
 507 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 508 +       master->dev.of_node = pdev->dev.of_node;
 509 +       master->num_chipselect = 2;
 510 +
 511 +       dev_set_drvdata(&pdev->dev, master);
 512 +
 513 +       rs = spi_master_get_devdata(master);
 514 +       rs->base = base;
 515 +       rs->clk = clk;
 516 +       rs->master = master;
 517 +       rs->sys_freq = clk_get_rate(rs->clk);
 518 +       rs->ops = ops;
 519 +       rs->pending_write = 0;
 520 +       dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 521 +
 522 +       device_reset(&pdev->dev);
 523 +
 524 +       mt7621_spi_reset(rs, 0);
 525 +
 526 +       return spi_register_master(master);
 527 +}
 528 +
 529 +static int mt7621_spi_remove(struct platform_device *pdev)
 530 +{
 531 +       struct spi_master *master;
 532 +       struct mt7621_spi *rs;
 533 +
 534 +       master = dev_get_drvdata(&pdev->dev);
 535 +       rs = spi_master_get_devdata(master);
 536 +
 537 +       clk_disable(rs->clk);
 538 +       spi_unregister_master(master);
 539 +
 540 +       return 0;
 541 +}
 542 +
 543 +MODULE_ALIAS("platform:" DRIVER_NAME);
 544 +
 545 +static struct platform_driver mt7621_spi_driver = {
 546 +       .driver = {
 547 +               .name = DRIVER_NAME,
 548 +               .of_match_table = mt7621_spi_match,
 549 +       },
 550 +       .probe = mt7621_spi_probe,
 551 +       .remove = mt7621_spi_remove,
 552 +};
 553 +
 554 +module_platform_driver(mt7621_spi_driver);
 555 +
 556 +MODULE_DESCRIPTION("MT7621 SPI driver");
 557 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
 558 +MODULE_LICENSE("GPL");