target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi

   1 #include "mt7621.dtsi"
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         aliases {
   8                 label-mac-device = &gmac0;
   9         };
  10
  11         keys {
  12                 compatible = "gpio-keys";
  13
  14                 reset {
  15                         label = "reset";
  16                         gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  17                         linux,code = <KEY_RESTART>;
  18                 };
  19         };
  20 };
  21
  22 &gmac0 {
  23         nvmem-cells = <&macaddr_factory_22 0>;
  24         nvmem-cell-names = "mac-address";
  25         label = "dsa";
  26 };
  27
  28 &switch0 {
  29         ports {
  30                 port@0 {
  31                         status = "okay";
  32                         label = "eth0";
  33                 };
  34
  35                 port@1 {
  36                         status = "okay";
  37                         label = "eth1";
  38                         nvmem-cells = <&macaddr_factory_22 1>;
  39                         nvmem-cell-names = "mac-address";
  40                 };
  41
  42                 port@2 {
  43                         status = "okay";
  44                         label = "eth2";
  45                         nvmem-cells = <&macaddr_factory_22 2>;
  46                         nvmem-cell-names = "mac-address";
  47                 };
  48
  49                 port@3 {
  50                         status = "okay";
  51                         label = "eth3";
  52                         nvmem-cells = <&macaddr_factory_22 3>;
  53                         nvmem-cell-names = "mac-address";
  54                 };
  55
  56                 port@4 {
  57                         status = "okay";
  58                         label = "eth4";
  59                         nvmem-cells = <&macaddr_factory_22 4>;
  60                         nvmem-cell-names = "mac-address";
  61                 };
  62         };
  63 };
  64
  65 &nand {
  66         status = "okay";
  67
  68         partitions {
  69                 compatible = "fixed-partitions";
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72
  73                 partition@0 {
  74                         label = "u-boot";
  75                         reg = <0x0 0x80000>;
  76                         read-only;
  77                 };
  78
  79                 partition@80000 {
  80                         label = "u-boot-env";
  81                         reg = <0x80000 0x60000>;
  82                         read-only;
  83                 };
  84
  85                 factory: partition@e0000 {
  86                         label = "factory";
  87                         reg = <0xe0000 0x60000>;
  88
  89                         nvmem-layout {
  90                                 compatible = "fixed-layout";
  91                                 #address-cells = <1>;
  92                                 #size-cells = <1>;
  93
  94                                 macaddr_factory_22: macaddr@22 {
  95                                         compatible = "mac-base";
  96                                         reg = <0x22 0x6>;
  97                                         #nvmem-cell-cells = <1>;
  98                                 };
  99                         };
 100                 };
 101
 102                 partition@140000 {
 103                         label = "kernel1";
 104                         reg = <0x140000 0x300000>;
 105                 };
 106
 107                 partition@440000 {
 108                         label = "kernel2";
 109                         reg = <0x440000 0x300000>;
 110                 };
 111
 112                 partition@740000 {
 113                         label = "ubi";
 114                         reg = <0x740000 0xf7c0000>;
 115                 };
 116         };
 117 };
 118
 119 &state_default {
 120         gpio {
 121                 groups = "uart2", "uart3", "pcie", "jtag";
 122                 function = "gpio";
 123         };
 124 };
 125
 126 &spi0 {
 127         /*
 128          * This board has 2Mb spi flash soldered in and visible
 129          * from manufacturer's firmware.
 130          * But this SoC shares spi and nand pins,
 131          * and current driver doesn't handle this sharing well
 132          */
 133         status = "disabled";
 134
 135         flash@1 {
 136                 compatible = "jedec,spi-nor";
 137                 reg = <1>;
 138                 spi-max-frequency = <10000000>;
 139
 140                 partitions {
 141                         compatible = "fixed-partitions";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144
 145                         partition@0 {
 146                                 label = "spi";
 147                                 reg = <0x0 0x200000>;
 148                                 read-only;
 149                         };
 150                 };
 151         };
 152 };
 153
 154 &xhci {
 155         status = "disabled";
 156 };