ramips: mt7620a: convert to nvmem-layout
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7620a_edimax_ew-747x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
8
9 / {
10 compatible = "ralink,mt7620a-soc";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
17 };
18
19 keys {
20 compatible = "gpio-keys";
21
22 reset_wps {
23 label = "reset_wps";
24 gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
25 linux,code = <KEY_RESTART>;
26 };
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 led_power: power {
33 label = "green:power";
34 gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
35 };
36
37 lan {
38 label = "green:lan";
39 gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
40 };
41
42 wps {
43 label = "green:wps";
44 gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
45 };
46 };
47 };
48
49 &gpio1 {
50 status = "okay";
51 };
52
53 &gpio2 {
54 status = "okay";
55 };
56
57 &spi0 {
58 status = "okay";
59
60 flash@0 {
61 compatible = "jedec,spi-nor";
62 reg = <0>;
63 spi-max-frequency = <10000000>;
64
65 partitions {
66 compatible = "fixed-partitions";
67 #address-cells = <1>;
68 #size-cells = <1>;
69
70 partition@0 {
71 label = "u-boot";
72 reg = <0x0 0x30000>;
73 read-only;
74 };
75
76 partition@30000 {
77 label = "u-boot-env";
78 reg = <0x30000 0x10000>;
79 read-only;
80 };
81
82 factory: partition@40000 {
83 label = "factory";
84 reg = <0x40000 0x10000>;
85 read-only;
86
87 nvmem-layout {
88 compatible = "fixed-layout";
89 #address-cells = <1>;
90 #size-cells = <1>;
91
92 eeprom_factory_0: eeprom@0 {
93 reg = <0x0 0x200>;
94 };
95
96 eeprom_factory_8000: eeprom@8000 {
97 reg = <0x8000 0x200>;
98 };
99
100 macaddr_factory_4: macaddr@4 {
101 reg = <0x4 0x6>;
102 };
103 };
104 };
105
106 partition@50000 {
107 label = "cimage";
108 reg = <0x50000 0x20000>;
109 read-only;
110 };
111
112 partition@70000 {
113 compatible = "openwrt,uimage", "denx,uimage";
114 openwrt,offset = <FW_EDIMAX_OFFSET>;
115 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
116 label = "firmware";
117 reg = <0x00070000 0x00790000>;
118 };
119 };
120 };
121 };
122
123 &state_default {
124 gpio {
125 groups = "i2c", "uartf", "nd_sd", "rgmii2";
126 function = "gpio";
127 };
128 };
129
130 &pinctrl {
131 phy_reset_pins: phy-reset {
132 gpio {
133 groups = "spi refclk";
134 function = "gpio";
135 };
136 };
137 };
138
139 &ethernet {
140 pinctrl-names = "default";
141 pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
142
143 nvmem-cells = <&macaddr_factory_4>;
144 nvmem-cell-names = "mac-address";
145
146 phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
147 phy-reset-duration = <30>;
148
149 port@5 {
150 status = "okay";
151 mediatek,fixed-link = <1000 1 1 1>;
152 phy-mode = "rgmii";
153 };
154
155 mdio-bus {
156 status = "okay";
157
158 phy0: ethernet-phy@0 {
159 status = "disabled";
160 reg = <0>;
161 phy-mode = "rgmii";
162 };
163
164 phy1: ethernet-phy@1 {
165 status = "disabled";
166 reg = <1>;
167 phy-mode = "rgmii";
168 };
169
170 phy2: ethernet-phy@2 {
171 status = "disabled";
172 reg = <2>;
173 phy-mode = "rgmii";
174 };
175
176 phy3: ethernet-phy@3 {
177 status = "disabled";
178 reg = <3>;
179 phy-mode = "rgmii";
180 };
181
182 phy4: ethernet-phy@4 {
183 status = "disabled";
184 reg = <4>;
185 phy-mode = "rgmii";
186 };
187 };
188 };
189
190 &gsw {
191 mediatek,ephy-base = /bits/ 8 <8>;
192 };
193
194 &wmac {
195 nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_4>;
196 nvmem-cell-names = "eeprom", "mac-address";
197 };
198
199 &pcie {
200 status = "okay";
201 };
202
203 &pcie0 {
204 wifi@0,0 {
205 reg = <0x0000 0 0 0 0>;
206 ieee80211-freq-limit = <5000000 6000000>;
207 nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_4>;
208 nvmem-cell-names = "eeprom", "mac-address";
209 mac-address-increment = <2>;
210 };
211 };