7c32b122ccfce4ae8ad485340fa5f48d7e626f80
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7620a_dlink_dir-510l.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/mtd/partitions/uimage.h>
9
10 / {
11 compatible = "dlink,dir-510l", "ralink,mt7620a-soc";
12 model = "D-Link DIR-510L";
13
14 aliases {
15 led-boot = &led_status;
16 led-failsafe = &led_status;
17 led-running = &led_status;
18 led-upgrade = &led_status;
19 };
20
21 chosen {
22 bootargs = "console=ttyS1,57600";
23 };
24
25 keys {
26 compatible = "gpio-keys";
27
28 reset {
29 label = "reset";
30 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
31 linux,code = <KEY_RESTART>;
32 };
33
34 wps {
35 label = "wps";
36 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
37 linux,code = <KEY_WPS_BUTTON>;
38 };
39 };
40
41 leds {
42 compatible = "gpio-leds";
43
44 led_status: status {
45 function = LED_FUNCTION_STATUS;
46 color = <LED_COLOR_ID_GREEN>;
47 gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
48 };
49
50 status-red {
51 function = LED_FUNCTION_STATUS;
52 color = <LED_COLOR_ID_RED>;
53 gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
54 };
55 };
56 };
57
58 &ethernet {
59 mediatek,portmap = "llllw";
60 };
61
62 &uart {
63 status = "okay";
64 };
65
66 &spi0 {
67 status = "okay";
68
69 flash@0 {
70 compatible = "jedec,spi-nor";
71 reg = <0>;
72 spi-max-frequency = <50000000>;
73
74 partitions {
75 compatible = "fixed-partitions";
76 #address-cells = <1>;
77 #size-cells = <1>;
78
79 partition@0 {
80 label = "jboot";
81 reg = <0x0 0x10000>;
82 read-only;
83 };
84
85 partition@10000 {
86 label = "recovery";
87 reg = <0x10000 0x200000>;
88 read-only;
89 };
90
91 partition@210000 {
92 compatible = "openwrt,uimage", "denx,uimage";
93 openwrt,ih-magic = <IH_MAGIC_OKLI>;
94 openwrt,offset = <0x10000>;
95 label = "firmware";
96 reg = <0x210000 0xde0000>;
97 };
98
99 config: partition@ff0000 {
100 label = "config";
101 reg = <0xff0000 0x10000>;
102 read-only;
103
104 nvmem-layout {
105 compatible = "fixed-layout";
106 #address-cells = <1>;
107 #size-cells = <1>;
108
109 eeprom_config_e05d: eeprom@e05d {
110 reg = <0xe05d 0x200>;
111 };
112
113 macaddr_config_e490: macaddr@e490 {
114 compatible = "mac-base";
115 reg = <0xe490 0x6>;
116 #nvmem-cell-cells = <1>;
117 };
118 };
119 };
120 };
121 };
122 };
123
124 &ehci {
125 status = "okay";
126 };
127
128 &ohci {
129 status = "okay";
130 };
131
132 &pcie {
133 status = "okay";
134 };
135
136 &pcie0 {
137 mt76x0e@0,0 {
138 reg = <0x0000 0 0 0 0>;
139 nvmem-cells = <&eeprom_config_e05d>, <&macaddr_config_e490 2>;
140 nvmem-cell-names = "eeprom", "mac-address";
141 };
142 };
143
144 &state_default {
145 default {
146 groups = "i2c", "uartf";
147 function = "gpio";
148 };
149 };