target/linux/qualcommax/patches-6.1/0135-arm64-dts-qcom-ipq6018-include-the-GPLL0-as-clock-pr.patch

   1 From a120815200adaf3ac28ccf3a1813c78b4be02cc4 Mon Sep 17 00:00:00 2001
   2 From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
   3 Date: Thu, 14 Sep 2023 12:29:59 +0530
   4 Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
   5  provider for mailbox
   6
   7 While the kernel is booting up, APSS PLL will be running at 800MHz with
   8 GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
   9 configured to the rate based on the opp table and the source also will
  10 be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
  11 with this inclusion, CPU Freq correctly reports that CPU is running at
  12 800MHz rather than 24MHz.
  13
  14 Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
  15 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  16 ---
  17  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
  18  1 file changed, 2 insertions(+), 2 deletions(-)
  19
  20 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  21 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  22 @@ -504,8 +504,8 @@
  23                         compatible = "qcom,ipq6018-apcs-apps-global";
  24                         reg = <0x0 0x0b111000 0x0 0x1000>;
  25                         #clock-cells = <1>;
  26 -                       clocks = <&a53pll>, <&xo>;
  27 -                       clock-names = "pll", "xo";
  28 +                       clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
  29 +                       clock-names = "pll", "xo", "gpll0";
  30                         #mbox-cells = <1>;
  31                 };
  32