target/linux/qualcommax/patches-6.1/0134-PCI-qcom-Fixing-broken-pcie-enumeration-for-2_3_3-co.patch

   1 From f92c2f22197b7beed59b81f2aa179e16987c02e4 Mon Sep 17 00:00:00 2001
   2 From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
   3 Date: Mon, 24 Jul 2023 12:04:29 +0530
   4 Subject: [PATCH] PCI: qcom: Fixing broken pcie enumeration for 2_3_3 configs
   5  ops
   6
   7 PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074 2_3_3 post_init.
   8 PCIe slave addr register offset is 0x358, but was wrongly changed to
   9 0x168 as a part of commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix
  10 from register definitions"). Fixing it, by using the right macro and remove
  11 the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3.
  12
  13 Without this access to the registers of slave addr space like iATU etc
  14 are broken leading to pcie enumeration failure.
  15
  16 Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")
  17 Cc: <Stable@vger.kernel.org>
  18 Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
  19 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  20 Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
  21 ---
  22  drivers/pci/controller/dwc/pcie-qcom.c | 4 +---
  23  1 file changed, 1 insertion(+), 3 deletions(-)
  24
  25 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  26 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  27 @@ -40,7 +40,6 @@
  28  #define PARF_PHY_REFCLK                                0x4c
  29  #define PARF_CONFIG_BITS                       0x50
  30  #define PARF_DBI_BASE_ADDR                     0x168
  31 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3         0x16c /* Register offset specific to IP ver 2.3.3 */
  32  #define PARF_MHI_CLOCK_RESET_CTRL              0x174
  33  #define PARF_AXI_MSTR_WR_ADDR_HALT             0x178
  34  #define PARF_AXI_MSTR_WR_ADDR_HALT_V2          0x1a8
  35 @@ -1148,8 +1147,7 @@ static int qcom_pcie_post_init_2_3_3(str
  36         u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
  37         u32 val;
  38
  39 -       writel(SLV_ADDR_SPACE_SZ,
  40 -               pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);
  41 +       writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
  42
  43         val = readl(pcie->parf + PARF_PHY_CTRL);
  44         val &= ~BIT(0);