target/linux/qualcommax/patches-6.1/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch

   1 From 04d2fc6a551bbd972a6428059b45ce79cb9de9d7 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Fri, 6 May 2022 22:38:24 +0200
   4 Subject: [PATCH] arm64: dts: qcom: ipq8074: add QFPROM fuses
   5
   6 Add the QFPROM node and CPR fuses.
   7
   8 Signed-off-by: Robert Marko <robimarko@gmail.com>
   9 ---
  10  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 107 ++++++++++++++++++++++++++
  11  1 file changed, 107 insertions(+)
  12
  13 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  14 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  15 @@ -343,6 +343,113 @@
  16                         status = "disabled";
  17                 };
  18
  19 +               qfprom: efuse@a4000 {
  20 +                       compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
  21 +                       reg = <0x000a4000 0x1000>;
  22 +                       #address-cells = <1>;
  23 +                       #size-cells = <1>;
  24 +
  25 +                       cpr_efuse_speedbin: speedbin@125 {
  26 +                               reg = <0x125 0x1>;
  27 +                               bits = <0 3>;
  28 +                       };
  29 +
  30 +                       cpr_efuse_boost_cfg: boost_cfg@125 {
  31 +                               reg = <0x125 0x1>;
  32 +                               bits = <3 3>;
  33 +                       };
  34 +
  35 +                       cpr_efuse_misc_volt_adj: misc_volt_adj@125 {
  36 +                               reg = <0x125 0x1>;
  37 +                               bits = <3 3>;
  38 +                       };
  39 +
  40 +                       cpr_efuse_boost_volt: boost_volt@126 {
  41 +                               reg = <0x126 0x1>;
  42 +                               bits = <6 1>;
  43 +                       };
  44 +
  45 +                       cpr_efuse_revision: revision@23e {
  46 +                               reg = <0x23e 0x1>;
  47 +                               bits = <5 3>;
  48 +                       };
  49 +
  50 +                       cpr_efuse_ro_sel0: rosel0@249 {
  51 +                               reg = <0x249 0x1>;
  52 +                               bits = <0 4>;
  53 +                       };
  54 +
  55 +                       cpr_efuse_ro_sel1: rosel1@248 {
  56 +                               reg = <0x248 0x1>;
  57 +                               bits = <4 4>;
  58 +                       };
  59 +
  60 +                       cpr_efuse_ro_sel2: rosel2@248 {
  61 +                               reg = <0x248 0x2>;
  62 +                               bits = <0 4>;
  63 +                       };
  64 +
  65 +                       cpr_efuse_ro_sel3: rosel3@249 {
  66 +                               reg = <0x249 0x1>;
  67 +                               bits = <4 4>;
  68 +                       };
  69 +
  70 +                       cpr_efuse_init_voltage0: ivoltage0@23a {
  71 +                               reg = <0x23a 0x1>;
  72 +                               bits = <2 6>;
  73 +                       };
  74 +
  75 +                       cpr_efuse_init_voltage1: ivoltage1@239 {
  76 +                               reg = <0x239 0x2>;
  77 +                               bits = <4 6>;
  78 +                       };
  79 +
  80 +                       cpr_efuse_init_voltage2: ivoltage2@238 {
  81 +                               reg = <0x238 0x2>;
  82 +                               bits = <6 6>;
  83 +                       };
  84 +
  85 +                       cpr_efuse_init_voltage3: ivoltage3@238 {
  86 +                               reg = <0x238 0x1>;
  87 +                               bits = <0 6>;
  88 +                       };
  89 +
  90 +                       cpr_efuse_quot0: quot0@244 {
  91 +                               reg = <0x244 0x2>;
  92 +                               bits = <0 12>;
  93 +                       };
  94 +
  95 +                       cpr_efuse_quot1: quot1@242 {
  96 +                               reg = <0x242 0x2>;
  97 +                               bits = <4 12>;
  98 +                       };
  99 +
 100 +                       cpr_efuse_quot2: quot2@241 {
 101 +                               reg = <0x241 0x2>;
 102 +                               bits = <0 12>;
 103 +                       };
 104 +
 105 +                       cpr_efuse_quot3: quot3@245 {
 106 +                               reg = <0x245 0x2>;
 107 +                               bits = <4 12>;
 108 +                       };
 109 +
 110 +                       cpr_efuse_quot0_offset: quot0_offset@23d {
 111 +                               reg = <0x23d 0x2>;
 112 +                               bits = <6 7>;
 113 +                       };
 114 +
 115 +                       cpr_efuse_quot1_offset: quot1_offset@23c {
 116 +                               reg = <0x23c 0x2>;
 117 +                               bits = <7 7>;
 118 +                       };
 119 +
 120 +                       cpr_efuse_quot2_offset: quot2_offset@23c {
 121 +                               reg = <0x23c 0x1>;
 122 +                               bits = <0 7>;
 123 +                       };
 124 +               };
 125 +
 126                 prng: rng@e3000 {
 127                         compatible = "qcom,prng-ee";
 128                         reg = <0x000e3000 0x1000>;