target/linux/qualcommax/patches-6.1/0122-arm64-dts-ipq8074-add-CPU-clock.patch

   1 From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Fri, 31 Dec 2021 17:56:14 +0100
   4 Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
   5
   6 Now that CPU clock is exposed and can be controlled, add the necessary
   7 properties to the CPU nodes.
   8
   9 Signed-off-by: Robert Marko <robimarko@gmail.com>
  10 ---
  11  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
  12  1 file changed, 9 insertions(+)
  13
  14 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  15 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  16 @@ -5,6 +5,7 @@
  17
  18  #include <dt-bindings/interrupt-controller/arm-gic.h>
  19  #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  20 +#include <dt-bindings/clock/qcom,apss-ipq.h>
  21
  22  / {
  23         #address-cells = <2>;
  24 @@ -38,6 +39,8 @@
  25                         reg = <0x0>;
  26                         next-level-cache = <&L2_0>;
  27                         enable-method = "psci";
  28 +                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  29 +                       clock-names = "cpu";
  30                 };
  31
  32                 CPU1: cpu@1 {
  33 @@ -46,6 +49,8 @@
  34                         enable-method = "psci";
  35                         reg = <0x1>;
  36                         next-level-cache = <&L2_0>;
  37 +                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  38 +                       clock-names = "cpu";
  39                 };
  40
  41                 CPU2: cpu@2 {
  42 @@ -54,6 +59,8 @@
  43                         enable-method = "psci";
  44                         reg = <0x2>;
  45                         next-level-cache = <&L2_0>;
  46 +                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  47 +                       clock-names = "cpu";
  48                 };
  49
  50                 CPU3: cpu@3 {
  51 @@ -62,6 +69,8 @@
  52                         enable-method = "psci";
  53                         reg = <0x3>;
  54                         next-level-cache = <&L2_0>;
  55 +                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  56 +                       clock-names = "cpu";
  57                 };
  58
  59                 L2_0: l2-cache {