target/linux/qualcommax/patches-6.1/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch

   1 From 7388400b8bd42f71d040dbf2fdbdcb834fcc0ede Mon Sep 17 00:00:00 2001
   2 From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
   3 Date: Sat, 30 Jan 2021 10:50:13 +0530
   4 Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
   5
   6 Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
   7 Also enables smp2p and mailboxes required for IPC.
   8
   9 Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
  10 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  11 Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
  12 Signed-off-by: Robert Marko <robimarko@gmail.com>
  13 ---
  14  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
  15  1 file changed, 81 insertions(+)
  16
  17 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  18 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  19 @@ -141,6 +141,32 @@
  20                 };
  21         };
  22
  23 +       wcss: smp2p-wcss {
  24 +               compatible = "qcom,smp2p";
  25 +               qcom,smem = <435>, <428>;
  26 +
  27 +               interrupt-parent = <&intc>;
  28 +               interrupts = <0 322 1>;
  29 +
  30 +               mboxes = <&apcs_glb 9>;
  31 +
  32 +               qcom,local-pid = <0>;
  33 +               qcom,remote-pid = <1>;
  34 +
  35 +               wcss_smp2p_out: master-kernel {
  36 +                       qcom,entry-name = "master-kernel";
  37 +                       qcom,smp2p-feature-ssr-ack;
  38 +                       #qcom,smem-state-cells = <1>;
  39 +               };
  40 +
  41 +               wcss_smp2p_in: slave-kernel {
  42 +                       qcom,entry-name = "slave-kernel";
  43 +
  44 +                       interrupt-controller;
  45 +                       #interrupt-cells = <2>;
  46 +               };
  47 +       };
  48 +
  49         soc: soc {
  50                 #address-cells = <0x1>;
  51                 #size-cells = <0x1>;
  52 @@ -417,6 +443,11 @@
  53                         reg = <0x01937000 0x21000>;
  54                 };
  55
  56 +               tcsr_q6: syscon@1945000 {
  57 +                       compatible = "syscon";
  58 +                       reg = <0x01945000 0xe000>;
  59 +               };
  60 +
  61                 spmi_bus: spmi@200f000 {
  62                         compatible = "qcom,spmi-pmic-arb";
  63                         reg = <0x0200f000 0x001000>,
  64 @@ -935,6 +966,56 @@
  65                                       "axi_s_sticky";
  66                         status = "disabled";
  67                 };
  68 +
  69 +               q6v5_wcss: q6v5_wcss@cd00000 {
  70 +                       compatible = "qcom,ipq8074-wcss-pil";
  71 +                       reg = <0x0cd00000 0x4040>,
  72 +                             <0x004ab000 0x20>;
  73 +                       reg-names = "qdsp6",
  74 +                                   "rmb";
  75 +                       qca,auto-restart;
  76 +                       qca,extended-intc;
  77 +                       interrupts-extended = <&intc 0 325 1>,
  78 +                                             <&wcss_smp2p_in 0 0>,
  79 +                                             <&wcss_smp2p_in 1 0>,
  80 +                                             <&wcss_smp2p_in 2 0>,
  81 +                                             <&wcss_smp2p_in 3 0>;
  82 +                       interrupt-names = "wdog",
  83 +                                         "fatal",
  84 +                                         "ready",
  85 +                                         "handover",
  86 +                                         "stop-ack";
  87 +
  88 +                       resets = <&gcc GCC_WCSSAON_RESET>,
  89 +                                <&gcc GCC_WCSS_BCR>,
  90 +                                <&gcc GCC_WCSS_Q6_BCR>;
  91 +
  92 +                       reset-names = "wcss_aon_reset",
  93 +                                     "wcss_reset",
  94 +                                     "wcss_q6_reset";
  95 +
  96 +                       clocks = <&gcc GCC_PRNG_AHB_CLK>;
  97 +                       clock-names = "prng";
  98 +
  99 +                       qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
 100 +
 101 +                       qcom,smem-states = <&wcss_smp2p_out 0>,
 102 +                                          <&wcss_smp2p_out 1>;
 103 +                       qcom,smem-state-names = "shutdown",
 104 +                                               "stop";
 105 +
 106 +                       memory-region = <&q6_region>;
 107 +
 108 +                       glink-edge {
 109 +                               interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
 110 +                               qcom,remote-pid = <1>;
 111 +                               mboxes = <&apcs_glb 8>;
 112 +
 113 +                               rpm_requests {
 114 +                                       qcom,glink-channels = "IPCRTR";
 115 +                               };
 116 +                       };
 117 +               };
 118         };
 119
 120         timer {