61cc2a459bb1b5e8a15832b3324b4364e2cc18be
[openwrt/staging/jow.git] / target / linux / qualcommax / patches-6.1 / 0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
1 From df75a00c60c6e58bc36e4c63e9d7f1910412b132 Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Fri, 13 Oct 2023 19:20:02 +0200
4 Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
5
6 IPQ8074 comes in 3 families:
7 * IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
8 * IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
9 * IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
10
11 So, in order to be able to share one OPP table lets add support for IPQ8074
12 family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
13
14 IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
15 will get created by NVMEM CPUFreq driver.
16
17 Signed-off-by: Robert Marko <robimarko@gmail.com>
18 Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
19 Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
20 ---
21 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
22 drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
23 2 files changed, 49 insertions(+)
24
25 --- a/drivers/cpufreq/cpufreq-dt-platdev.c
26 +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
27 @@ -164,6 +164,7 @@ static const struct of_device_id blockli
28 { .compatible = "ti,omap3", },
29
30 { .compatible = "qcom,ipq8064", },
31 + { .compatible = "qcom,ipq8074", },
32 { .compatible = "qcom,apq8064", },
33 { .compatible = "qcom,msm8974", },
34 { .compatible = "qcom,msm8960", },
35 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
36 +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
37 @@ -31,6 +31,11 @@
38
39 #include <dt-bindings/arm/qcom,ids.h>
40
41 +enum ipq8074_versions {
42 + IPQ8074_HAWKEYE_VERSION = 0,
43 + IPQ8074_ACORN_VERSION,
44 +};
45 +
46 struct qcom_cpufreq_drv;
47
48 struct qcom_cpufreq_match_data {
49 @@ -204,6 +209,44 @@ len_error:
50 return ret;
51 }
52
53 +static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
54 + struct nvmem_cell *speedbin_nvmem,
55 + char **pvs_name,
56 + struct qcom_cpufreq_drv *drv)
57 +{
58 + u32 msm_id;
59 + int ret;
60 + *pvs_name = NULL;
61 +
62 + ret = qcom_smem_get_soc_id(&msm_id);
63 + if (ret)
64 + return ret;
65 +
66 + switch (msm_id) {
67 + case QCOM_ID_IPQ8070A:
68 + case QCOM_ID_IPQ8071A:
69 + case QCOM_ID_IPQ8172:
70 + case QCOM_ID_IPQ8173:
71 + case QCOM_ID_IPQ8174:
72 + drv->versions = BIT(IPQ8074_ACORN_VERSION);
73 + break;
74 + case QCOM_ID_IPQ8072A:
75 + case QCOM_ID_IPQ8074A:
76 + case QCOM_ID_IPQ8076A:
77 + case QCOM_ID_IPQ8078A:
78 + drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
79 + break;
80 + default:
81 + dev_err(cpu_dev,
82 + "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
83 + msm_id);
84 + drv->versions = BIT(IPQ8074_ACORN_VERSION);
85 + break;
86 + }
87 +
88 + return 0;
89 +}
90 +
91 static const struct qcom_cpufreq_match_data match_data_kryo = {
92 .get_version = qcom_cpufreq_kryo_name_version,
93 };
94 @@ -218,6 +261,10 @@ static const struct qcom_cpufreq_match_d
95 .genpd_names = qcs404_genpd_names,
96 };
97
98 +static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
99 + .get_version = qcom_cpufreq_ipq8074_name_version,
100 +};
101 +
102 static int qcom_cpufreq_probe(struct platform_device *pdev)
103 {
104 struct qcom_cpufreq_drv *drv;
105 @@ -363,6 +410,7 @@ static const struct of_device_id qcom_cp
106 { .compatible = "qcom,msm8996", .data = &match_data_kryo },
107 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
108 { .compatible = "qcom,ipq8064", .data = &match_data_krait },
109 + { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
110 { .compatible = "qcom,apq8064", .data = &match_data_krait },
111 { .compatible = "qcom,msm8974", .data = &match_data_krait },
112 { .compatible = "qcom,msm8960", .data = &match_data_krait },