ipq807x: rename target to qualcommax
[openwrt/staging/jow.git] / target / linux / qualcommax / patches-6.1 / 0013-v6.2-arm64-dts-qcom-add-PMP8074-DTSI.patch
1 From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Fri, 19 Aug 2022 00:18:14 +0200
4 Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
5
6 PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
7 controlled via SPMI.
8
9 Add DTSI for it providing GPIO, regulator, RTC and VADC support.
10
11 RTC is disabled by default as there is no built-in battery so it will
12 loose time unless board vendor added a battery, so make it optional.
13
14 Signed-off-by: Robert Marko <robimarko@gmail.com>
15 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
16 Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
17 ---
18 arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
19 1 file changed, 125 insertions(+)
20 create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
21
22 --- /dev/null
23 +++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
24 @@ -0,0 +1,125 @@
25 +// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
26 +
27 +#include <dt-bindings/spmi/spmi.h>
28 +#include <dt-bindings/iio/qcom,spmi-vadc.h>
29 +
30 +&spmi_bus {
31 + pmic@0 {
32 + compatible = "qcom,pmp8074", "qcom,spmi-pmic";
33 + reg = <0x0 SPMI_USID>;
34 + #address-cells = <1>;
35 + #size-cells = <0>;
36 +
37 + pmp8074_adc: adc@3100 {
38 + compatible = "qcom,spmi-adc-rev2";
39 + reg = <0x3100>;
40 + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
41 + #address-cells = <1>;
42 + #size-cells = <0>;
43 + #io-channel-cells = <1>;
44 +
45 + ref-gnd@0 {
46 + reg = <ADC5_REF_GND>;
47 + qcom,pre-scaling = <1 1>;
48 + };
49 +
50 + vref-1p25@1 {
51 + reg = <ADC5_1P25VREF>;
52 + qcom,pre-scaling = <1 1>;
53 + };
54 +
55 + vref-vadc@2 {
56 + reg = <ADC5_VREF_VADC>;
57 + qcom,pre-scaling = <1 1>;
58 + };
59 +
60 + pmic_die: die-temp@6 {
61 + reg = <ADC5_DIE_TEMP>;
62 + qcom,pre-scaling = <1 1>;
63 + };
64 +
65 + xo_therm: xo-temp@76 {
66 + reg = <ADC5_XO_THERM_100K_PU>;
67 + qcom,ratiometric;
68 + qcom,hw-settle-time = <200>;
69 + qcom,pre-scaling = <1 1>;
70 + };
71 +
72 + pa_therm1: thermistor1@77 {
73 + reg = <ADC5_AMUX_THM1_100K_PU>;
74 + qcom,ratiometric;
75 + qcom,hw-settle-time = <200>;
76 + qcom,pre-scaling = <1 1>;
77 + };
78 +
79 + pa_therm2: thermistor2@78 {
80 + reg = <ADC5_AMUX_THM2_100K_PU>;
81 + qcom,ratiometric;
82 + qcom,hw-settle-time = <200>;
83 + qcom,pre-scaling = <1 1>;
84 + };
85 +
86 + pa_therm3: thermistor3@79 {
87 + reg = <ADC5_AMUX_THM3_100K_PU>;
88 + qcom,ratiometric;
89 + qcom,hw-settle-time = <200>;
90 + qcom,pre-scaling = <1 1>;
91 + };
92 +
93 + vph-pwr@131 {
94 + reg = <ADC5_VPH_PWR>;
95 + qcom,pre-scaling = <1 3>;
96 + };
97 + };
98 +
99 + pmp8074_rtc: rtc@6000 {
100 + compatible = "qcom,pm8941-rtc";
101 + reg = <0x6000>;
102 + reg-names = "rtc", "alarm";
103 + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
104 + allow-set-time;
105 + status = "disabled";
106 + };
107 +
108 + pmp8074_gpios: gpio@c000 {
109 + compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
110 + reg = <0xc000>;
111 + gpio-controller;
112 + #gpio-cells = <2>;
113 + gpio-ranges = <&pmp8074_gpios 0 0 12>;
114 + interrupt-controller;
115 + #interrupt-cells = <2>;
116 + };
117 + };
118 +
119 + pmic@1 {
120 + compatible = "qcom,pmp8074", "qcom,spmi-pmic";
121 + reg = <0x1 SPMI_USID>;
122 +
123 + regulators {
124 + compatible = "qcom,pmp8074-regulators";
125 +
126 + s3: s3 {
127 + regulator-name = "vdd_s3";
128 + regulator-min-microvolt = <592000>;
129 + regulator-max-microvolt = <1064000>;
130 + regulator-always-on;
131 + regulator-boot-on;
132 + };
133 +
134 + s4: s4 {
135 + regulator-name = "vdd_s4";
136 + regulator-min-microvolt = <712000>;
137 + regulator-max-microvolt = <992000>;
138 + regulator-always-on;
139 + regulator-boot-on;
140 + };
141 +
142 + l11: l11 {
143 + regulator-name = "l11";
144 + regulator-min-microvolt = <1800000>;
145 + regulator-max-microvolt = <3300000>;
146 + };
147 + };
148 + };
149 +};