qualcommax: ipq807x: MX4200 convert qca807x PHY to new implementation
[openwrt/staging/jow.git] / target / linux / qualcommax / files / arch / arm64 / boot / dts / qcom / ipq8174-mx4200.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* Copyright (c) 2023, Mohammad Sayful Islam <Sayf.mohammad01@gmail.com> */
3
4 #include "ipq8074.dtsi"
5 #include "ipq8074-ac-cpu.dtsi"
6 #include "ipq8074-ess.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10
11 / {
12
13 aliases {
14 serial0 = &blsp1_uart5;
15 serial1 = &blsp1_uart3;
16 /*
17 * Aliases as required by u-boot
18 * to patch MAC addresses
19 */
20 ethernet1 = &dp2;
21 ethernet2 = &dp3;
22 ethernet3 = &dp4;
23 ethernet4 = &dp5;
24 led-boot = &led_system_blue;
25 led-running = &led_system_blue;
26 led-failsafe = &led_system_red;
27 led-upgrade = &led_system_green;
28 };
29
30 chosen {
31 stdout-path = "serial0:115200n8";
32 bootargs-append = " root=/dev/ubiblock0_0";
33 };
34
35 keys {
36 compatible = "gpio-keys";
37 pinctrl-0 = <&button_pins>;
38 pinctrl-names = "default";
39
40 reset-button {
41 label = "reset";
42 gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
43 linux,code = <KEY_RESTART>;
44 };
45
46 wps-button {
47 label = "wps";
48 gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
49 linux,code = <KEY_WPS_BUTTON>;
50 };
51 };
52 };
53
54 &tlmm {
55 button_pins: button-state {
56 pins = "gpio52", "gpio67";
57 function = "gpio";
58 drive-strength = <8>;
59 bias-pull-up;
60 };
61
62 mdio_pins: mdio-state {
63 mdc-pins {
64 pins = "gpio68";
65 function = "mdc";
66 drive-strength = <8>;
67 bias-pull-up;
68 };
69
70 mdio-pins {
71 pins = "gpio69";
72 function = "mdio";
73 drive-strength = <8>;
74 bias-pull-up;
75 };
76 };
77
78 iot_pins: iot-state {
79 recovery-pins {
80 pins = "gpio22";
81 function = "gpio";
82 input;
83 };
84
85 reset-pins {
86 pins = "gpio21";
87 function = "gpio";
88 bias-pull-up;
89 };
90 };
91 };
92
93 &blsp1_uart3 {
94 status = "okay";
95
96 pinctrl-0 = <&hsuart_pins &iot_pins>;
97 pinctrl-names = "default";
98
99 /* Silicon Labs EFR32MG21 IoT */
100 };
101
102 &blsp1_uart5 {
103 status = "okay";
104 };
105
106 &prng {
107 status = "okay";
108 };
109
110 &cryptobam {
111 status = "okay";
112 };
113
114 &crypto {
115 status = "okay";
116 };
117
118 &qpic_bam {
119 status = "okay";
120 };
121
122 &qpic_nand {
123 status = "okay";
124
125 /*
126 * Bootloader will find the NAND DT node by the compatible and
127 * then "fixup" it by adding the partitions from the SMEM table
128 * using the legacy bindings thus making it impossible for us
129 * to change the partition table or utilize NVMEM for calibration.
130 * So add a dummy partitions node that bootloader will populate
131 * and set it as disabled so the kernel ignores it instead of
132 * printing warnings due to the broken way bootloader adds the
133 * partitions.
134 */
135 partitions {
136 status = "disabled";
137 };
138
139 nand@0 {
140 reg = <0>;
141 nand-ecc-strength = <4>;
142 nand-ecc-step-size = <512>;
143 nand-bus-width = <8>;
144
145 partitions {
146 compatible = "fixed-partitions";
147 #address-cells = <1>;
148 #size-cells = <1>;
149
150 partition@0 {
151 label = "0:sbl1";
152 reg = <0x0 0x100000>;
153 read-only;
154 };
155
156 partition@100000 {
157 label = "0:mibib";
158 reg = <0x100000 0x100000>;
159 read-only;
160 };
161
162 partition@200000 {
163 label = "0:bootconfig";
164 reg = <0x200000 0x80000>;
165 read-only;
166 };
167
168 partition@280000 {
169 label = "0:bootconfig1";
170 reg = <0x280000 0x80000>;
171 read-only;
172 };
173
174 partition@300000 {
175 label = "0:qsee";
176 reg = <0x300000 0x300000>;
177 read-only;
178 };
179
180 partition@600000 {
181 label = "0:qsee_1";
182 reg = <0x600000 0x300000>;
183 read-only;
184 };
185
186 partition@900000 {
187 label = "0:devcfg";
188 reg = <0x900000 0x80000>;
189 read-only;
190 };
191
192 partition@980000 {
193 label = "0:devcfg_1";
194 reg = <0x980000 0x80000>;
195 read-only;
196 };
197
198 partition@a00000 {
199 label = "0:apdp";
200 reg = <0xa00000 0x80000>;
201 read-only;
202 };
203
204 partition@a80000 {
205 label = "0:apdp_1";
206 reg = <0xa80000 0x80000>;
207 read-only;
208 };
209
210 partition@b00000 {
211 label = "0:rpm";
212 reg = <0xb00000 0x80000>;
213 read-only;
214 };
215
216 partition@b80000 {
217 label = "0:rpm_1";
218 reg = <0xb80000 0x80000>;
219 read-only;
220 };
221
222 partition@c00000 {
223 label = "0:cdt";
224 reg = <0xc00000 0x80000>;
225 read-only;
226 };
227
228 partition@c80000 {
229 label = "0:cdt_1";
230 reg = <0xc80000 0x80000>;
231 read-only;
232 };
233
234 partition@d00000 {
235 label = "0:appsblenv";
236 reg = <0xd00000 0x80000>;
237 };
238
239 partition@d80000 {
240 label = "0:appsbl";
241 reg = <0xd80000 0x100000>;
242 read-only;
243 };
244
245 partition@e80000 {
246 label = "0:appsbl_1";
247 reg = <0xe80000 0x100000>;
248 read-only;
249 };
250
251 partition@f80000 {
252 label = "0:art";
253 reg = <0xf80000 0x80000>;
254 read-only;
255 };
256
257 partition@1000000 {
258 label = "u_env";
259 reg = <0x1000000 0x40000>;
260 };
261
262 partition@1040000 {
263 label = "s_env";
264 reg = <0x1040000 0x20000>;
265 };
266
267 partition@1060000 {
268 label = "devinfo";
269 reg = <0x1060000 0x20000>;
270 read-only;
271 };
272
273 partition@1080000 {
274 label = "kernel";
275 reg = <0x1080000 0x9600000>;
276 };
277
278 partition@1680000 {
279 label = "rootfs";
280 reg = <0x1680000 0x9000000>;
281 };
282
283 partition@a680000 {
284 label = "alt_kernel";
285 reg = <0xa680000 0x9600000>;
286 };
287
288 partition@ac80000 {
289 label = "alt_rootfs";
290 reg = <0xac80000 0x9000000>;
291 };
292 partition@13c80000 {
293 label = "sysdiag";
294 reg = <0x13c80000 0x200000>;
295 read-only;
296 };
297 partition@13e80000 {
298 label = "0:ethphyfw";
299 reg = <0x13e80000 0x80000>;
300 read-only;
301 };
302 partition@13f00000 {
303 label = "syscfg";
304 reg = <0x13f00000 0xb800000>;
305 read-only;
306 };
307 partition@1f700000 {
308 label = "0:wififw";
309 reg = <0x1f700000 0x900000>;
310 read-only;
311 };
312 };
313 };
314 };
315
316 &blsp1_i2c2 {
317 status = "okay";
318
319 led-controller@62 {
320 compatible = "nxp,pca9633";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg = <0x62>;
324 nxp,hw-blink;
325
326 led_system_red: led@0 {
327 reg = <0>;
328 color = <LED_COLOR_ID_RED>;
329 function = LED_FUNCTION_STATUS;
330 };
331
332 led_system_green: led@1 {
333 reg = <1>;
334 color = <LED_COLOR_ID_GREEN>;
335 function = LED_FUNCTION_STATUS;
336 };
337
338 led_system_blue: led@2 {
339 reg = <2>;
340 color = <LED_COLOR_ID_BLUE>;
341 function = LED_FUNCTION_STATUS;
342 };
343 };
344 };
345
346 &mdio {
347 status = "okay";
348
349 pinctrl-0 = <&mdio_pins>;
350 pinctrl-names = "default";
351 reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
352
353 ethernet-phy-package@0 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356 compatible = "qcom,qca8075-package";
357 reg = <0>;
358
359 qca8075_1: ethernet-phy@1 {
360 compatible = "ethernet-phy-ieee802.3-c22";
361 reg = <1>;
362 };
363
364 qca8075_2: ethernet-phy@2 {
365 compatible = "ethernet-phy-ieee802.3-c22";
366 reg = <2>;
367 };
368
369 qca8075_3: ethernet-phy@3 {
370 compatible = "ethernet-phy-ieee802.3-c22";
371 reg = <3>;
372 };
373
374 qca8075_4: ethernet-phy@4 {
375 compatible = "ethernet-phy-ieee802.3-c22";
376 reg = <4>;
377 };
378 };
379 };
380
381 &switch {
382 status = "okay";
383
384 switch_lan_bmp = <(ESS_PORT3 | ESS_PORT4 | ESS_PORT5)>; /* lan port bitmap */
385 switch_wan_bmp = <ESS_PORT2>; /* wan port bitmap */
386 switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
387
388 qcom,port_phyinfo {
389 port@2 {
390 port_id = <2>;
391 phy_address = <1>;
392 };
393 port@3 {
394 port_id = <3>;
395 phy_address = <2>;
396 };
397 port@4 {
398 port_id = <4>;
399 phy_address = <3>;
400 };
401 port@5 {
402 port_id = <5>;
403 phy_address = <4>;
404 };
405 };
406 };
407
408 &edma {
409 status = "okay";
410 };
411
412 &dp2 {
413 status = "okay";
414 phy-handle = <&qca8075_1>;
415 label = "wan";
416 };
417
418 &dp3 {
419 status = "okay";
420 phy-handle = <&qca8075_2>;
421 label = "lan1";
422 };
423
424 &dp4 {
425 status = "okay";
426 phy-handle = <&qca8075_3>;
427 label = "lan2";
428 };
429
430 &dp5 {
431 status = "okay";
432 phy-handle = <&qca8075_4>;
433 label = "lan3";
434 };
435
436 &ssphy_0 {
437 status = "okay";
438 };
439
440 &qusb_phy_0 {
441 status = "okay";
442 };
443
444 &usb_0 {
445 status = "okay";
446 };
447