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[openwrt/staging/jow.git] / target / linux / qualcommax / files / arch / arm64 / boot / dts / qcom / ipq8074-ess.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <dt-bindings/net/qcom-ipq-ess.h>
4
5 &clocks {
6 bias_pll_cc_clk {
7 compatible = "fixed-clock";
8 clock-frequency = <300000000>;
9 #clock-cells = <0>;
10 };
11
12 bias_pll_nss_noc_clk {
13 compatible = "fixed-clock";
14 clock-frequency = <416500000>;
15 #clock-cells = <0>;
16 };
17 };
18
19 &soc {
20 switch: ess-switch@3a000000 {
21 compatible = "qcom,ess-switch-ipq807x";
22 reg = <0x3a000000 0x1000000>;
23 switch_access_mode = "local bus";
24 switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
25 switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
26 /* This is a special binding that controls how the malibu PHY are
27 * init. This value reflect the PHY addr of the first malibu PHY.
28 * Malibu PHY are in a bundle of 5 PHY.
29 * Some device might have some port not connected.
30 * SSDK still needs the addrs of the first PHY (even if not connected)
31 * to correctly setup the malibu PHY.
32 *
33 * This is needed as previously SSDK based this on the port bmp, but
34 * this can be problematic now that we specify correct bmp.
35 *
36 * Most common configuration have the malibu PHY placed at 0.
37 * But some device might have it placed at address 16.
38 * To drive the correct value, check the port id of the malibu PHY
39 * and try to understand what is the first one in devices where some
40 * port are missing. port_phyinfo is normally the way to go to derive
41 * this value in the few special cases.
42 */
43 malibu_first_phy_addr = <0>;
44 clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
45 <&gcc GCC_CMN_12GPLL_SYS_CLK>,
46 <&gcc GCC_UNIPHY0_AHB_CLK>,
47 <&gcc GCC_UNIPHY0_SYS_CLK>,
48 <&gcc GCC_UNIPHY1_AHB_CLK>,
49 <&gcc GCC_UNIPHY1_SYS_CLK>,
50 <&gcc GCC_UNIPHY2_AHB_CLK>,
51 <&gcc GCC_UNIPHY2_SYS_CLK>,
52 <&gcc GCC_PORT1_MAC_CLK>,
53 <&gcc GCC_PORT2_MAC_CLK>,
54 <&gcc GCC_PORT3_MAC_CLK>,
55 <&gcc GCC_PORT4_MAC_CLK>,
56 <&gcc GCC_PORT5_MAC_CLK>,
57 <&gcc GCC_PORT6_MAC_CLK>,
58 <&gcc GCC_NSS_PPE_CLK>,
59 <&gcc GCC_NSS_PPE_CFG_CLK>,
60 <&gcc GCC_NSSNOC_PPE_CLK>,
61 <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
62 <&gcc GCC_NSS_EDMA_CLK>,
63 <&gcc GCC_NSS_EDMA_CFG_CLK>,
64 <&gcc GCC_NSS_PPE_IPE_CLK>,
65 <&gcc GCC_NSS_PPE_BTQ_CLK>,
66 <&gcc GCC_MDIO_AHB_CLK>,
67 <&gcc GCC_NSS_NOC_CLK>,
68 <&gcc GCC_NSSNOC_SNOC_CLK>,
69 <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
70 <&gcc GCC_NSS_CRYPTO_CLK>,
71 <&gcc GCC_NSS_IMEM_CLK>,
72 <&gcc GCC_NSS_PTP_REF_CLK>,
73 <&gcc GCC_NSS_PORT1_RX_CLK>,
74 <&gcc GCC_NSS_PORT1_TX_CLK>,
75 <&gcc GCC_NSS_PORT2_RX_CLK>,
76 <&gcc GCC_NSS_PORT2_TX_CLK>,
77 <&gcc GCC_NSS_PORT3_RX_CLK>,
78 <&gcc GCC_NSS_PORT3_TX_CLK>,
79 <&gcc GCC_NSS_PORT4_RX_CLK>,
80 <&gcc GCC_NSS_PORT4_TX_CLK>,
81 <&gcc GCC_NSS_PORT5_RX_CLK>,
82 <&gcc GCC_NSS_PORT5_TX_CLK>,
83 <&gcc GCC_NSS_PORT6_RX_CLK>,
84 <&gcc GCC_NSS_PORT6_TX_CLK>,
85 <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
86 <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
87 <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
88 <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
89 <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
90 <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
91 <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
92 <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
93 <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
94 <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
95 <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
96 <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
97 <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
98 <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
99 <&gcc NSS_PORT5_RX_CLK_SRC>,
100 <&gcc NSS_PORT5_TX_CLK_SRC>;
101 clock-names = "cmn_ahb_clk", "cmn_sys_clk",
102 "uniphy0_ahb_clk", "uniphy0_sys_clk",
103 "uniphy1_ahb_clk", "uniphy1_sys_clk",
104 "uniphy2_ahb_clk", "uniphy2_sys_clk",
105 "port1_mac_clk", "port2_mac_clk",
106 "port3_mac_clk", "port4_mac_clk",
107 "port5_mac_clk", "port6_mac_clk",
108 "nss_ppe_clk", "nss_ppe_cfg_clk",
109 "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
110 "nss_edma_clk", "nss_edma_cfg_clk",
111 "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
112 "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
113 "gcc_nssnoc_snoc_clk",
114 "gcc_mem_noc_nss_axi_clk",
115 "gcc_nss_crypto_clk",
116 "gcc_nss_imem_clk",
117 "gcc_nss_ptp_ref_clk",
118 "nss_port1_rx_clk", "nss_port1_tx_clk",
119 "nss_port2_rx_clk", "nss_port2_tx_clk",
120 "nss_port3_rx_clk", "nss_port3_tx_clk",
121 "nss_port4_rx_clk", "nss_port4_tx_clk",
122 "nss_port5_rx_clk", "nss_port5_tx_clk",
123 "nss_port6_rx_clk", "nss_port6_tx_clk",
124 "uniphy0_port1_rx_clk",
125 "uniphy0_port1_tx_clk",
126 "uniphy0_port2_rx_clk",
127 "uniphy0_port2_tx_clk",
128 "uniphy0_port3_rx_clk",
129 "uniphy0_port3_tx_clk",
130 "uniphy0_port4_rx_clk",
131 "uniphy0_port4_tx_clk",
132 "uniphy0_port5_rx_clk",
133 "uniphy0_port5_tx_clk",
134 "uniphy1_port5_rx_clk",
135 "uniphy1_port5_tx_clk",
136 "uniphy2_port6_rx_clk",
137 "uniphy2_port6_tx_clk",
138 "nss_port5_rx_clk_src",
139 "nss_port5_tx_clk_src";
140 resets = <&gcc GCC_PPE_FULL_RESET>,
141 <&gcc GCC_UNIPHY0_SOFT_RESET>,
142 <&gcc GCC_UNIPHY0_XPCS_RESET>,
143 <&gcc GCC_UNIPHY1_SOFT_RESET>,
144 <&gcc GCC_UNIPHY1_XPCS_RESET>,
145 <&gcc GCC_UNIPHY2_SOFT_RESET>,
146 <&gcc GCC_UNIPHY2_XPCS_RESET>,
147 <&gcc GCC_NSSPORT1_RESET>,
148 <&gcc GCC_NSSPORT2_RESET>,
149 <&gcc GCC_NSSPORT3_RESET>,
150 <&gcc GCC_NSSPORT4_RESET>,
151 <&gcc GCC_NSSPORT5_RESET>,
152 <&gcc GCC_NSSPORT6_RESET>;
153 reset-names = "ppe_rst", "uniphy0_soft_rst",
154 "uniphy0_xpcs_rst", "uniphy1_soft_rst",
155 "uniphy1_xpcs_rst", "uniphy2_soft_rst",
156 "uniphy2_xpcs_rst", "nss_port1_rst",
157 "nss_port2_rst", "nss_port3_rst",
158 "nss_port4_rst", "nss_port5_rst",
159 "nss_port6_rst";
160 mdio-bus = <&mdio>;
161 status = "disabled";
162
163 port_scheduler_resource {
164 port@0 {
165 port_id = <0>;
166 ucast_queue = <0 143>;
167 mcast_queue = <256 271>;
168 l0sp = <0 35>;
169 l0cdrr = <0 47>;
170 l0edrr = <0 47>;
171 l1cdrr = <0 7>;
172 l1edrr = <0 7>;
173 };
174 port@1 {
175 port_id = <1>;
176 ucast_queue = <144 159>;
177 mcast_queue = <272 275>;
178 l0sp = <36 39>;
179 l0cdrr = <48 63>;
180 l0edrr = <48 63>;
181 l1cdrr = <8 11>;
182 l1edrr = <8 11>;
183 };
184 port@2 {
185 port_id = <2>;
186 ucast_queue = <160 175>;
187 mcast_queue = <276 279>;
188 l0sp = <40 43>;
189 l0cdrr = <64 79>;
190 l0edrr = <64 79>;
191 l1cdrr = <12 15>;
192 l1edrr = <12 15>;
193 };
194 port@3 {
195 port_id = <3>;
196 ucast_queue = <176 191>;
197 mcast_queue = <280 283>;
198 l0sp = <44 47>;
199 l0cdrr = <80 95>;
200 l0edrr = <80 95>;
201 l1cdrr = <16 19>;
202 l1edrr = <16 19>;
203 };
204 port@4 {
205 port_id = <4>;
206 ucast_queue = <192 207>;
207 mcast_queue = <284 287>;
208 l0sp = <48 51>;
209 l0cdrr = <96 111>;
210 l0edrr = <96 111>;
211 l1cdrr = <20 23>;
212 l1edrr = <20 23>;
213 };
214 port@5 {
215 port_id = <5>;
216 ucast_queue = <208 223>;
217 mcast_queue = <288 291>;
218 l0sp = <52 55>;
219 l0cdrr = <112 127>;
220 l0edrr = <112 127>;
221 l1cdrr = <24 27>;
222 l1edrr = <24 27>;
223 };
224 port@6 {
225 port_id = <6>;
226 ucast_queue = <224 239>;
227 mcast_queue = <292 295>;
228 l0sp = <56 59>;
229 l0cdrr = <128 143>;
230 l0edrr = <128 143>;
231 l1cdrr = <28 31>;
232 l1edrr = <28 31>;
233 };
234 port@7 {
235 port_id = <7>;
236 ucast_queue = <240 255>;
237 mcast_queue = <296 299>;
238 l0sp = <60 63>;
239 l0cdrr = <144 159>;
240 l0edrr = <144 159>;
241 l1cdrr = <32 35>;
242 l1edrr = <32 35>;
243 };
244 };
245 port_scheduler_config {
246 port@0 {
247 port_id = <0>;
248 l1scheduler {
249 group@0 {
250 sp = <0 1>; /*L0 SPs*/
251 /*cpri cdrr epri edrr*/
252 cfg = <0 0 0 0>;
253 };
254 };
255 l0scheduler {
256 group@0 {
257 /*unicast queues*/
258 ucast_queue = <0 4 8>;
259 /*multicast queues*/
260 mcast_queue = <256 260>;
261 /*sp cpri cdrr epri edrr*/
262 cfg = <0 0 0 0 0>;
263 };
264 group@1 {
265 ucast_queue = <1 5 9>;
266 mcast_queue = <257 261>;
267 cfg = <0 1 1 1 1>;
268 };
269 group@2 {
270 ucast_queue = <2 6 10>;
271 mcast_queue = <258 262>;
272 cfg = <0 2 2 2 2>;
273 };
274 group@3 {
275 ucast_queue = <3 7 11>;
276 mcast_queue = <259 263>;
277 cfg = <0 3 3 3 3>;
278 };
279 };
280 };
281 port@1 {
282 port_id = <1>;
283 l1scheduler {
284 group@0 {
285 sp = <36>;
286 cfg = <0 8 0 8>;
287 };
288 group@1 {
289 sp = <37>;
290 cfg = <1 9 1 9>;
291 };
292 };
293 l0scheduler {
294 group@0 {
295 ucast_queue = <144>;
296 ucast_loop_pri = <16>;
297 mcast_queue = <272>;
298 mcast_loop_pri = <4>;
299 cfg = <36 0 48 0 48>;
300 };
301 };
302 };
303 port@2 {
304 port_id = <2>;
305 l1scheduler {
306 group@0 {
307 sp = <40>;
308 cfg = <0 12 0 12>;
309 };
310 group@1 {
311 sp = <41>;
312 cfg = <1 13 1 13>;
313 };
314 };
315 l0scheduler {
316 group@0 {
317 ucast_queue = <160>;
318 ucast_loop_pri = <16>;
319 mcast_queue = <276>;
320 mcast_loop_pri = <4>;
321 cfg = <40 0 64 0 64>;
322 };
323 };
324 };
325 port@3 {
326 port_id = <3>;
327 l1scheduler {
328 group@0 {
329 sp = <44>;
330 cfg = <0 16 0 16>;
331 };
332 group@1 {
333 sp = <45>;
334 cfg = <1 17 1 17>;
335 };
336 };
337 l0scheduler {
338 group@0 {
339 ucast_queue = <176>;
340 ucast_loop_pri = <16>;
341 mcast_queue = <280>;
342 mcast_loop_pri = <4>;
343 cfg = <44 0 80 0 80>;
344 };
345 };
346 };
347 port@4 {
348 port_id = <4>;
349 l1scheduler {
350 group@0 {
351 sp = <48>;
352 cfg = <0 20 0 20>;
353 };
354 group@1 {
355 sp = <49>;
356 cfg = <1 21 1 21>;
357 };
358 };
359 l0scheduler {
360 group@0 {
361 ucast_queue = <192>;
362 ucast_loop_pri = <16>;
363 mcast_queue = <284>;
364 mcast_loop_pri = <4>;
365 cfg = <48 0 96 0 96>;
366 };
367 };
368 };
369 port@5 {
370 port_id = <5>;
371 l1scheduler {
372 group@0 {
373 sp = <52>;
374 cfg = <0 24 0 24>;
375 };
376 group@1 {
377 sp = <53>;
378 cfg = <1 25 1 25>;
379 };
380 };
381 l0scheduler {
382 group@0 {
383 ucast_queue = <208>;
384 ucast_loop_pri = <16>;
385 mcast_queue = <288>;
386 mcast_loop_pri = <4>;
387 cfg = <52 0 112 0 112>;
388 };
389 };
390 };
391 port@6 {
392 port_id = <6>;
393 l1scheduler {
394 group@0 {
395 sp = <56>;
396 cfg = <0 28 0 28>;
397 };
398 group@1 {
399 sp = <57>;
400 cfg = <1 29 1 29>;
401 };
402 };
403 l0scheduler {
404 group@0 {
405 ucast_queue = <224>;
406 ucast_loop_pri = <16>;
407 mcast_queue = <292>;
408 mcast_loop_pri = <4>;
409 cfg = <56 0 128 0 128>;
410 };
411 };
412 };
413 port@7 {
414 port_id = <7>;
415 l1scheduler {
416 group@0 {
417 sp = <60>;
418 cfg = <0 32 0 32>;
419 };
420 group@1 {
421 sp = <61>;
422 cfg = <1 33 1 33>;
423 };
424 };
425 l0scheduler {
426 group@0 {
427 ucast_queue = <240>;
428 ucast_loop_pri = <16>;
429 mcast_queue = <296>;
430 cfg = <60 0 144 0 144>;
431 };
432 };
433 };
434 };
435 };
436
437 ess-uniphy@7a00000 {
438 compatible = "qcom,ess-uniphy";
439 reg = <0x7a00000 0x30000>;
440 uniphy_access_mode = "local bus";
441 };
442
443 edma: edma@3ab00000 {
444 compatible = "qcom,edma";
445 reg = <0x3ab00000 0x76900>;
446 reg-names = "edma-reg-base";
447 qcom,txdesc-ring-start = <23>;
448 qcom,txdesc-rings = <1>;
449 qcom,txcmpl-ring-start = <7>;
450 qcom,txcmpl-rings = <1>;
451 qcom,rxfill-ring-start = <7>;
452 qcom,rxfill-rings = <1>;
453 qcom,rxdesc-ring-start = <15>;
454 qcom,rxdesc-rings = <1>;
455 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
459 resets = <&gcc GCC_EDMA_HW_RESET>;
460 reset-names = "edma_rst";
461 status = "disabled";
462 };
463
464 dp1: dp1 {
465 device_type = "network";
466 compatible = "qcom,nss-dp";
467 qcom,id = <1>;
468 reg = <0x3a001000 0x200>;
469 qcom,mactype = <0>;
470 local-mac-address = [000000000000];
471 phy-mode = "sgmii";
472 status = "disabled";
473 };
474
475 dp2: dp2 {
476 device_type = "network";
477 compatible = "qcom,nss-dp";
478 qcom,id = <2>;
479 reg = <0x3a001200 0x200>;
480 qcom,mactype = <0>;
481 local-mac-address = [000000000000];
482 phy-mode = "sgmii";
483 status = "disabled";
484 };
485
486 dp3: dp3 {
487 device_type = "network";
488 compatible = "qcom,nss-dp";
489 qcom,id = <3>;
490 reg = <0x3a001400 0x200>;
491 qcom,mactype = <0>;
492 local-mac-address = [000000000000];
493 phy-mode = "sgmii";
494 status = "disabled";
495 };
496
497 dp4: dp4 {
498 device_type = "network";
499 compatible = "qcom,nss-dp";
500 qcom,id = <4>;
501 reg = <0x3a001600 0x200>;
502 qcom,mactype = <0>;
503 local-mac-address = [000000000000];
504 phy-mode = "sgmii";
505 status = "disabled";
506 };
507
508 dp5: dp5 {
509 device_type = "network";
510 compatible = "qcom,nss-dp";
511 qcom,id = <5>;
512 reg = <0x3a001800 0x200>;
513 qcom,mactype = <0>;
514 local-mac-address = [000000000000];
515 phy-mode = "sgmii";
516 status = "disabled";
517 };
518
519 dp6: dp6 {
520 device_type = "network";
521 compatible = "qcom,nss-dp";
522 qcom,id = <6>;
523 reg = <0x3a001a00 0x200>;
524 qcom,mactype = <0>;
525 local-mac-address = [000000000000];
526 phy-mode = "sgmii";
527 status = "disabled";
528 };
529
530 dp5_syn: dp5-syn {
531 device_type = "network";
532 compatible = "qcom,nss-dp";
533 qcom,id = <5>;
534 reg = <0x3a003000 0x3fff>;
535 qcom,mactype = <1>;
536 local-mac-address = [000000000000];
537 phy-mode = "sgmii";
538 status = "disabled";
539 };
540
541 dp6_syn: dp6-syn {
542 device_type = "network";
543 compatible = "qcom,nss-dp";
544 qcom,id = <6>;
545 reg = <0x3a007000 0x3fff>;
546 qcom,mactype = <1>;
547 local-mac-address = [000000000000];
548 phy-mode = "sgmii";
549 status = "disabled";
550 };
551 };
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