target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include <dt-bindings/net/qcom-ipq-ess.h>
   4
   5 &clocks {
   6         bias_pll_cc_clk {
   7                 compatible = "fixed-clock";
   8                 clock-frequency = <300000000>;
   9                 #clock-cells = <0>;
  10         };
  11
  12         bias_pll_nss_noc_clk {
  13                 compatible = "fixed-clock";
  14                 clock-frequency = <416500000>;
  15                 #clock-cells = <0>;
  16         };
  17 };
  18
  19 &soc {
  20         switch: ess-switch@3a000000 {
  21                 compatible = "qcom,ess-switch-ipq807x";
  22                 reg = <0x3a000000 0x1000000>;
  23                 switch_access_mode = "local bus";
  24                 switch_cpu_bmp = <ESS_PORT0>;  /* cpu port bitmap */
  25                 switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
  26                 clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
  27                          <&gcc GCC_CMN_12GPLL_SYS_CLK>,
  28                          <&gcc GCC_UNIPHY0_AHB_CLK>,
  29                          <&gcc GCC_UNIPHY0_SYS_CLK>,
  30                          <&gcc GCC_UNIPHY1_AHB_CLK>,
  31                          <&gcc GCC_UNIPHY1_SYS_CLK>,
  32                          <&gcc GCC_UNIPHY2_AHB_CLK>,
  33                          <&gcc GCC_UNIPHY2_SYS_CLK>,
  34                          <&gcc GCC_PORT1_MAC_CLK>,
  35                          <&gcc GCC_PORT2_MAC_CLK>,
  36                          <&gcc GCC_PORT3_MAC_CLK>,
  37                          <&gcc GCC_PORT4_MAC_CLK>,
  38                          <&gcc GCC_PORT5_MAC_CLK>,
  39                          <&gcc GCC_PORT6_MAC_CLK>,
  40                          <&gcc GCC_NSS_PPE_CLK>,
  41                          <&gcc GCC_NSS_PPE_CFG_CLK>,
  42                          <&gcc GCC_NSSNOC_PPE_CLK>,
  43                          <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
  44                          <&gcc GCC_NSS_EDMA_CLK>,
  45                          <&gcc GCC_NSS_EDMA_CFG_CLK>,
  46                          <&gcc GCC_NSS_PPE_IPE_CLK>,
  47                          <&gcc GCC_NSS_PPE_BTQ_CLK>,
  48                          <&gcc GCC_MDIO_AHB_CLK>,
  49                          <&gcc GCC_NSS_NOC_CLK>,
  50                          <&gcc GCC_NSSNOC_SNOC_CLK>,
  51                          <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
  52                          <&gcc GCC_NSS_CRYPTO_CLK>,
  53                          <&gcc GCC_NSS_IMEM_CLK>,
  54                          <&gcc GCC_NSS_PTP_REF_CLK>,
  55                          <&gcc GCC_NSS_PORT1_RX_CLK>,
  56                          <&gcc GCC_NSS_PORT1_TX_CLK>,
  57                          <&gcc GCC_NSS_PORT2_RX_CLK>,
  58                          <&gcc GCC_NSS_PORT2_TX_CLK>,
  59                          <&gcc GCC_NSS_PORT3_RX_CLK>,
  60                          <&gcc GCC_NSS_PORT3_TX_CLK>,
  61                          <&gcc GCC_NSS_PORT4_RX_CLK>,
  62                          <&gcc GCC_NSS_PORT4_TX_CLK>,
  63                          <&gcc GCC_NSS_PORT5_RX_CLK>,
  64                          <&gcc GCC_NSS_PORT5_TX_CLK>,
  65                          <&gcc GCC_NSS_PORT6_RX_CLK>,
  66                          <&gcc GCC_NSS_PORT6_TX_CLK>,
  67                          <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
  68                          <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
  69                          <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
  70                          <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
  71                          <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
  72                          <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
  73                          <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
  74                          <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
  75                          <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
  76                          <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
  77                          <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
  78                          <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
  79                          <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
  80                          <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
  81                          <&gcc NSS_PORT5_RX_CLK_SRC>,
  82                          <&gcc NSS_PORT5_TX_CLK_SRC>;
  83                 clock-names = "cmn_ahb_clk", "cmn_sys_clk",
  84                               "uniphy0_ahb_clk", "uniphy0_sys_clk",
  85                               "uniphy1_ahb_clk", "uniphy1_sys_clk",
  86                               "uniphy2_ahb_clk", "uniphy2_sys_clk",
  87                               "port1_mac_clk", "port2_mac_clk",
  88                               "port3_mac_clk", "port4_mac_clk",
  89                               "port5_mac_clk", "port6_mac_clk",
  90                               "nss_ppe_clk", "nss_ppe_cfg_clk",
  91                               "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
  92                               "nss_edma_clk", "nss_edma_cfg_clk",
  93                               "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
  94                               "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
  95                               "gcc_nssnoc_snoc_clk",
  96                               "gcc_mem_noc_nss_axi_clk",
  97                               "gcc_nss_crypto_clk",
  98                               "gcc_nss_imem_clk",
  99                               "gcc_nss_ptp_ref_clk",
 100                               "nss_port1_rx_clk", "nss_port1_tx_clk",
 101                               "nss_port2_rx_clk", "nss_port2_tx_clk",
 102                               "nss_port3_rx_clk", "nss_port3_tx_clk",
 103                               "nss_port4_rx_clk", "nss_port4_tx_clk",
 104                               "nss_port5_rx_clk", "nss_port5_tx_clk",
 105                               "nss_port6_rx_clk", "nss_port6_tx_clk",
 106                               "uniphy0_port1_rx_clk",
 107                               "uniphy0_port1_tx_clk",
 108                               "uniphy0_port2_rx_clk",
 109                               "uniphy0_port2_tx_clk",
 110                               "uniphy0_port3_rx_clk",
 111                               "uniphy0_port3_tx_clk",
 112                               "uniphy0_port4_rx_clk",
 113                               "uniphy0_port4_tx_clk",
 114                               "uniphy0_port5_rx_clk",
 115                               "uniphy0_port5_tx_clk",
 116                               "uniphy1_port5_rx_clk",
 117                               "uniphy1_port5_tx_clk",
 118                               "uniphy2_port6_rx_clk",
 119                               "uniphy2_port6_tx_clk",
 120                               "nss_port5_rx_clk_src",
 121                               "nss_port5_tx_clk_src";
 122                 resets = <&gcc GCC_PPE_FULL_RESET>,
 123                          <&gcc GCC_UNIPHY0_SOFT_RESET>,
 124                          <&gcc GCC_UNIPHY0_XPCS_RESET>,
 125                          <&gcc GCC_UNIPHY1_SOFT_RESET>,
 126                          <&gcc GCC_UNIPHY1_XPCS_RESET>,
 127                          <&gcc GCC_UNIPHY2_SOFT_RESET>,
 128                          <&gcc GCC_UNIPHY2_XPCS_RESET>,
 129                          <&gcc GCC_NSSPORT1_RESET>,
 130                          <&gcc GCC_NSSPORT2_RESET>,
 131                          <&gcc GCC_NSSPORT3_RESET>,
 132                          <&gcc GCC_NSSPORT4_RESET>,
 133                          <&gcc GCC_NSSPORT5_RESET>,
 134                          <&gcc GCC_NSSPORT6_RESET>;
 135                 reset-names = "ppe_rst", "uniphy0_soft_rst",
 136                               "uniphy0_xpcs_rst", "uniphy1_soft_rst",
 137                               "uniphy1_xpcs_rst", "uniphy2_soft_rst",
 138                               "uniphy2_xpcs_rst", "nss_port1_rst",
 139                               "nss_port2_rst", "nss_port3_rst",
 140                               "nss_port4_rst", "nss_port5_rst",
 141                               "nss_port6_rst";
 142                 mdio-bus = <&mdio>;
 143
 144                 switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
 145                 switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
 146                 switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
 147
 148                 bm_tick_mode = <0>; /* bm tick mode */
 149                 tm_tick_mode = <0>; /* tm tick mode */
 150
 151                 status = "disabled";
 152
 153                 port_scheduler_resource {
 154                         port@0 {
 155                                 port_id = <0>;
 156                                 ucast_queue = <0 143>;
 157                                 mcast_queue = <256 271>;
 158                                 l0sp = <0 35>;
 159                                 l0cdrr = <0 47>;
 160                                 l0edrr = <0 47>;
 161                                 l1cdrr = <0 7>;
 162                                 l1edrr = <0 7>;
 163                         };
 164                         port@1 {
 165                                 port_id = <1>;
 166                                 ucast_queue = <144 159>;
 167                                 mcast_queue = <272 275>;
 168                                 l0sp = <36 39>;
 169                                 l0cdrr = <48 63>;
 170                                 l0edrr = <48 63>;
 171                                 l1cdrr = <8 11>;
 172                                 l1edrr = <8 11>;
 173                         };
 174                         port@2 {
 175                                 port_id = <2>;
 176                                 ucast_queue = <160 175>;
 177                                 mcast_queue = <276 279>;
 178                                 l0sp = <40 43>;
 179                                 l0cdrr = <64 79>;
 180                                 l0edrr = <64 79>;
 181                                 l1cdrr = <12 15>;
 182                                 l1edrr = <12 15>;
 183                         };
 184                         port@3 {
 185                                 port_id = <3>;
 186                                 ucast_queue = <176 191>;
 187                                 mcast_queue = <280 283>;
 188                                 l0sp = <44 47>;
 189                                 l0cdrr = <80 95>;
 190                                 l0edrr = <80 95>;
 191                                 l1cdrr = <16 19>;
 192                                 l1edrr = <16 19>;
 193                         };
 194                         port@4 {
 195                                 port_id = <4>;
 196                                 ucast_queue = <192 207>;
 197                                 mcast_queue = <284 287>;
 198                                 l0sp = <48 51>;
 199                                 l0cdrr = <96 111>;
 200                                 l0edrr = <96 111>;
 201                                 l1cdrr = <20 23>;
 202                                 l1edrr = <20 23>;
 203                         };
 204                         port@5 {
 205                                 port_id = <5>;
 206                                 ucast_queue = <208 223>;
 207                                 mcast_queue = <288 291>;
 208                                 l0sp = <52 55>;
 209                                 l0cdrr = <112 127>;
 210                                 l0edrr = <112 127>;
 211                                 l1cdrr = <24 27>;
 212                                 l1edrr = <24 27>;
 213                         };
 214                         port@6 {
 215                                 port_id = <6>;
 216                                 ucast_queue = <224 239>;
 217                                 mcast_queue = <292 295>;
 218                                 l0sp = <56 59>;
 219                                 l0cdrr = <128 143>;
 220                                 l0edrr = <128 143>;
 221                                 l1cdrr = <28 31>;
 222                                 l1edrr = <28 31>;
 223                         };
 224                         port@7 {
 225                                 port_id = <7>;
 226                                 ucast_queue = <240 255>;
 227                                 mcast_queue = <296 299>;
 228                                 l0sp = <60 63>;
 229                                 l0cdrr = <144 159>;
 230                                 l0edrr = <144 159>;
 231                                 l1cdrr = <32 35>;
 232                                 l1edrr = <32 35>;
 233                         };
 234                 };
 235                 port_scheduler_config {
 236                         port@0 {
 237                                 port_id = <0>;
 238                                 l1scheduler {
 239                                         group@0 {
 240                                                 sp = <0 1>; /*L0 SPs*/
 241                                                 /*cpri cdrr epri edrr*/
 242                                                 cfg = <0 0 0 0>;
 243                                         };
 244                                 };
 245                                 l0scheduler {
 246                                         group@0 {
 247                                                 /*unicast queues*/
 248                                                 ucast_queue = <0 4 8>;
 249                                                 /*multicast queues*/
 250                                                 mcast_queue = <256 260>;
 251                                                 /*sp cpri cdrr epri edrr*/
 252                                                 cfg = <0 0 0 0 0>;
 253                                         };
 254                                         group@1 {
 255                                                 ucast_queue = <1 5 9>;
 256                                                 mcast_queue = <257 261>;
 257                                                 cfg = <0 1 1 1 1>;
 258                                         };
 259                                         group@2 {
 260                                                 ucast_queue = <2 6 10>;
 261                                                 mcast_queue = <258 262>;
 262                                                 cfg = <0 2 2 2 2>;
 263                                         };
 264                                         group@3 {
 265                                                 ucast_queue = <3 7 11>;
 266                                                 mcast_queue = <259 263>;
 267                                                 cfg = <0 3 3 3 3>;
 268                                         };
 269                                 };
 270                         };
 271                         port@1 {
 272                                 port_id = <1>;
 273                                 l1scheduler {
 274                                         group@0 {
 275                                                 sp = <36>;
 276                                                 cfg = <0 8 0 8>;
 277                                         };
 278                                         group@1 {
 279                                                 sp = <37>;
 280                                                 cfg = <1 9 1 9>;
 281                                         };
 282                                 };
 283                                 l0scheduler {
 284                                         group@0 {
 285                                                 ucast_queue = <144>;
 286                                                 ucast_loop_pri = <16>;
 287                                                 mcast_queue = <272>;
 288                                                 mcast_loop_pri = <4>;
 289                                                 cfg = <36 0 48 0 48>;
 290                                         };
 291                                 };
 292                         };
 293                         port@2 {
 294                                 port_id = <2>;
 295                                 l1scheduler {
 296                                         group@0 {
 297                                                 sp = <40>;
 298                                                 cfg = <0 12 0 12>;
 299                                         };
 300                                         group@1 {
 301                                                 sp = <41>;
 302                                                 cfg = <1 13 1 13>;
 303                                         };
 304                                 };
 305                                 l0scheduler {
 306                                         group@0 {
 307                                                 ucast_queue = <160>;
 308                                                 ucast_loop_pri = <16>;
 309                                                 mcast_queue = <276>;
 310                                                 mcast_loop_pri = <4>;
 311                                                 cfg = <40 0 64 0 64>;
 312                                         };
 313                                 };
 314                         };
 315                         port@3 {
 316                                 port_id = <3>;
 317                                 l1scheduler {
 318                                         group@0 {
 319                                                 sp = <44>;
 320                                                 cfg = <0 16 0 16>;
 321                                         };
 322                                         group@1 {
 323                                                 sp = <45>;
 324                                                 cfg = <1 17 1 17>;
 325                                         };
 326                                 };
 327                                 l0scheduler {
 328                                         group@0 {
 329                                                 ucast_queue = <176>;
 330                                                 ucast_loop_pri = <16>;
 331                                                 mcast_queue = <280>;
 332                                                 mcast_loop_pri = <4>;
 333                                                 cfg = <44 0 80 0 80>;
 334                                         };
 335                                 };
 336                         };
 337                         port@4 {
 338                                 port_id = <4>;
 339                                 l1scheduler {
 340                                         group@0 {
 341                                                 sp = <48>;
 342                                                 cfg = <0 20 0 20>;
 343                                         };
 344                                         group@1 {
 345                                                 sp = <49>;
 346                                                 cfg = <1 21 1 21>;
 347                                         };
 348                                 };
 349                                 l0scheduler {
 350                                         group@0 {
 351                                                 ucast_queue = <192>;
 352                                                 ucast_loop_pri = <16>;
 353                                                 mcast_queue = <284>;
 354                                                 mcast_loop_pri = <4>;
 355                                                 cfg = <48 0 96 0 96>;
 356                                         };
 357                                 };
 358                         };
 359                         port@5 {
 360                                 port_id = <5>;
 361                                 l1scheduler {
 362                                         group@0 {
 363                                                 sp = <52>;
 364                                                 cfg = <0 24 0 24>;
 365                                         };
 366                                         group@1 {
 367                                                 sp = <53>;
 368                                                 cfg = <1 25 1 25>;
 369                                         };
 370                                 };
 371                                 l0scheduler {
 372                                         group@0 {
 373                                                 ucast_queue = <208>;
 374                                                 ucast_loop_pri = <16>;
 375                                                 mcast_queue = <288>;
 376                                                 mcast_loop_pri = <4>;
 377                                                 cfg = <52 0 112 0 112>;
 378                                         };
 379                                 };
 380                         };
 381                         port@6 {
 382                                 port_id = <6>;
 383                                 l1scheduler {
 384                                         group@0 {
 385                                                 sp = <56>;
 386                                                 cfg = <0 28 0 28>;
 387                                         };
 388                                         group@1 {
 389                                                 sp = <57>;
 390                                                 cfg = <1 29 1 29>;
 391                                         };
 392                                 };
 393                                 l0scheduler {
 394                                         group@0 {
 395                                                 ucast_queue = <224>;
 396                                                 ucast_loop_pri = <16>;
 397                                                 mcast_queue = <292>;
 398                                                 mcast_loop_pri = <4>;
 399                                                 cfg = <56 0 128 0 128>;
 400                                         };
 401                                 };
 402                         };
 403                         port@7 {
 404                                 port_id = <7>;
 405                                 l1scheduler {
 406                                         group@0 {
 407                                                 sp = <60>;
 408                                                 cfg = <0 32 0 32>;
 409                                         };
 410                                         group@1 {
 411                                                 sp = <61>;
 412                                                 cfg = <1 33 1 33>;
 413                                         };
 414                                 };
 415                                 l0scheduler {
 416                                         group@0 {
 417                                                 ucast_queue = <240>;
 418                                                 ucast_loop_pri = <16>;
 419                                                 mcast_queue = <296>;
 420                                                 cfg = <60 0 144 0 144>;
 421                                         };
 422                                 };
 423                         };
 424                 };
 425         };
 426
 427         ess-uniphy@7a00000 {
 428                 compatible = "qcom,ess-uniphy";
 429                 reg = <0x7a00000 0x30000>;
 430                 uniphy_access_mode = "local bus";
 431         };
 432
 433         edma: edma@3ab00000 {
 434                 compatible = "qcom,edma";
 435                 reg = <0x3ab00000 0x76900>;
 436                 reg-names = "edma-reg-base";
 437                 qcom,txdesc-ring-start = <23>;
 438                 qcom,txdesc-rings = <1>;
 439                 qcom,txcmpl-ring-start = <7>;
 440                 qcom,txcmpl-rings = <1>;
 441                 qcom,rxfill-ring-start = <7>;
 442                 qcom,rxfill-rings = <1>;
 443                 qcom,rxdesc-ring-start = <15>;
 444                 qcom,rxdesc-rings = <1>;
 445                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 446                              <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 447                              <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 448                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 449                 resets = <&gcc GCC_EDMA_HW_RESET>;
 450                 reset-names = "edma_rst";
 451                 status = "disabled";
 452         };
 453
 454         dp1: dp1@3a001000 {
 455                 device_type = "network";
 456                 compatible = "qcom,nss-dp";
 457                 qcom,id = <1>;
 458                 reg = <0x3a001000 0x200>;
 459                 qcom,mactype = <0>;
 460                 local-mac-address = [000000000000];
 461                 phy-mode = "psgmii";
 462                 status = "disabled";
 463         };
 464
 465         dp2: dp2@3a001200 {
 466                 device_type = "network";
 467                 compatible = "qcom,nss-dp";
 468                 qcom,id = <2>;
 469                 reg = <0x3a001200 0x200>;
 470                 qcom,mactype = <0>;
 471                 local-mac-address = [000000000000];
 472                 phy-mode = "psgmii";
 473                 status = "disabled";
 474         };
 475
 476         dp3: dp3@3a001400 {
 477                 device_type = "network";
 478                 compatible = "qcom,nss-dp";
 479                 qcom,id = <3>;
 480                 reg = <0x3a001400 0x200>;
 481                 qcom,mactype = <0>;
 482                 local-mac-address = [000000000000];
 483                 phy-mode = "psgmii";
 484                 status = "disabled";
 485         };
 486
 487         dp4: dp4@3a001600 {
 488                 device_type = "network";
 489                 compatible = "qcom,nss-dp";
 490                 qcom,id = <4>;
 491                 reg = <0x3a001600 0x200>;
 492                 qcom,mactype = <0>;
 493                 local-mac-address = [000000000000];
 494                 phy-mode = "psgmii";
 495                 status = "disabled";
 496         };
 497
 498         dp5: dp5@3a001800 {
 499                 device_type = "network";
 500                 compatible = "qcom,nss-dp";
 501                 qcom,id = <5>;
 502                 reg = <0x3a001800 0x200>;
 503                 qcom,mactype = <0>;
 504                 local-mac-address = [000000000000];
 505                 phy-mode = "psgmii";
 506                 status = "disabled";
 507         };
 508
 509         dp6: dp6@3a001a00 {
 510                 device_type = "network";
 511                 compatible = "qcom,nss-dp";
 512                 qcom,id = <6>;
 513                 reg = <0x3a001a00 0x200>;
 514                 qcom,mactype = <0>;
 515                 local-mac-address = [000000000000];
 516                 phy-mode = "sgmii";
 517                 status = "disabled";
 518         };
 519
 520         dp5_syn: dp5-syn@3a003000 {
 521                 device_type = "network";
 522                 compatible = "qcom,nss-dp";
 523                 qcom,id = <5>;
 524                 reg = <0x3a003000 0x3fff>;
 525                 qcom,mactype = <1>;
 526                 local-mac-address = [000000000000];
 527                 phy-mode = "sgmii";
 528                 status = "disabled";
 529         };
 530
 531         dp6_syn: dp6-syn@3a007000 {
 532                 device_type = "network";
 533                 compatible = "qcom,nss-dp";
 534                 qcom,id = <6>;
 535                 reg = <0x3a007000 0x3fff>;
 536                 qcom,mactype = <1>;
 537                 local-mac-address = [000000000000];
 538                 phy-mode = "sgmii";
 539                 status = "disabled";
 540         };
 541 };