target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /* Copyright 2023 Nokia */
   3
   4 /dts-v1/;
   5
   6 #include "ipq8074.dtsi"
   7 #include "ipq8074-hk-cpu.dtsi"
   8 #include "ipq8074-ess.dtsi"
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/leds/common.h>
  12
  13 / {
  14         model = "Compex WPQ873";
  15         compatible = "compex,wpq873", "qcom,ipq8074";
  16
  17         aliases {
  18                 serial0 = &blsp1_uart5;
  19                 led-boot = &led_power_blue;
  20                 led-failsafe = &led_power_red;
  21                 led-running = &led_system_green;
  22                 led-upgrade = &led_system_blue;
  23                 /* Aliases as required by u-boot to patch MAC addresses */
  24                 ethernet0 = &dp6;
  25                 ethernet1 = &dp2;
  26                 ethernet2 = &dp3;
  27                 ethernet3 = &dp4;
  28                 label-mac-device = &dp6;
  29         };
  30
  31         chosen {
  32                 stdout-path = "serial0:115200n8";
  33                 bootargs-append = " root=/dev/ubiblock0_1";
  34         };
  35
  36         keys {
  37                 compatible = "gpio-keys";
  38
  39                 reset {
  40                         label = "reset";
  41                         gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
  42                         linux,code = <KEY_RESTART>;
  43                 };
  44         };
  45
  46         leds {
  47                 compatible = "gpio-leds";
  48
  49                 led_power_red: power-red {
  50                         label = "red:power";
  51                         gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
  52                         color = <LED_COLOR_ID_RED>;
  53                 };
  54
  55                 led_power_blue: power-blue {
  56                         label = "blue:power";
  57                         gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
  58                         color = <LED_COLOR_ID_BLUE>;
  59                 };
  60
  61                 led_system_red: system-red {
  62                         label = "red:system";
  63                         gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
  64                         color = <LED_COLOR_ID_RED>;
  65                 };
  66
  67                 led_system_green: system-green {
  68                         label = "green:system";
  69                         gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
  70                         color = <LED_COLOR_ID_GREEN>;
  71                 };
  72
  73                 led_system_blue: system-blue {
  74                         label = "blue:system";
  75                         gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
  76                         color = <LED_COLOR_ID_BLUE>;
  77                 };
  78         };
  79 };
  80
  81 &tlmm {
  82         mdio_pins: mdio-pins {
  83                 mdc {
  84                         pins = "gpio68";
  85                         function = "mdc";
  86                         drive-strength = <8>;
  87                         bias-pull-up;
  88                 };
  89
  90                 mdio {
  91                         pins = "gpio69";
  92                         function = "mdio";
  93                         drive-strength = <8>;
  94                         bias-pull-up;
  95                 };
  96         };
  97
  98         i2c_pins: i2c-pins {
  99                 pins = "gpio0", "gpio2";
 100                 function = "blsp5_i2c";
 101                 drive-strength = <8>;
 102                 bias-disable;
 103         };
 104 };
 105
 106 &blsp1_uart5 {
 107         status = "okay";
 108 };
 109
 110 &blsp1_i2c6 {
 111         status = "okay";
 112
 113         pinctrl-0 = <&i2c_pins>;
 114         pinctrl-names = "default";
 115 };
 116
 117 &prng {
 118         status = "okay";
 119 };
 120
 121 &cryptobam {
 122         status = "okay";
 123 };
 124
 125 &crypto {
 126         status = "okay";
 127 };
 128
 129 &qpic_bam {
 130         status = "okay";
 131 };
 132
 133 &blsp1_spi1 {
 134         status = "okay";
 135 };
 136
 137 &tlmm {
 138         mdio_pins: mdio-pins {
 139                 mdc {
 140                         pins = "gpio68";
 141                         function = "mdc";
 142                         drive-strength = <8>;
 143                         bias-pull-up;
 144                 };
 145
 146                 mdio {
 147                         pins = "gpio69";
 148                         function = "mdio";
 149                         drive-strength = <8>;
 150                         bias-pull-up;
 151                 };
 152         };
 153
 154         button_pins: button_pins {
 155                 reset_button {
 156                         pins = "gpio66";
 157                         function = "gpio";
 158                         drive-strength = <8>;
 159                         bias-pull-up;
 160                 };
 161         };
 162 };
 163
 164 &blsp1_spi1 {
 165         status = "okay";
 166
 167         flash@0 {
 168                 #address-cells = <1>;
 169                 #size-cells = <1>;
 170                 reg = <0>;
 171                 compatible = "jedec,spi-nor";
 172                 spi-max-frequency = <50000000>;
 173
 174                 partitions {
 175                         compatible = "fixed-partitions";
 176                         #address-cells = <1>;
 177                         #size-cells = <1>;
 178
 179                         partition@0 {
 180                                 label = "0:sbl1";
 181                                 reg = <0x0 0x50000>;
 182                                 read-only;
 183                         };
 184
 185                         partition@50000 {
 186                                 label = "0:mibib";
 187                                 reg = <0x50000 0x10000>;
 188                                 read-only;
 189                         };
 190
 191                         partition@60000 {
 192                                 label = "0:bootconfig";
 193                                 reg = <0x60000 0x20000>;
 194                                 read-only;
 195                         };
 196
 197                         partition@80000 {
 198                                 label = "0:bootconfig1";
 199                                 reg = <0x80000 0x20000>;
 200                                 read-only;
 201                         };
 202
 203                         partition@a0000 {
 204                                 label = "0:qsee";
 205                                 reg = <0xa0000 0x180000>;
 206                                 read-only;
 207                         };
 208
 209                         partition@220000 {
 210                                 label = "0:qsee_1";
 211                                 reg = <0x220000 0x180000>;
 212                                 read-only;
 213                         };
 214
 215                         partition@3a0000 {
 216                                 label = "0:devcfg";
 217                                 reg = <0x3a0000 0x10000>;
 218                                 read-only;
 219                         };
 220
 221                         partition@3b0000 {
 222                                 label = "0:devcfg_1";
 223                                 reg = <0x3b0000 0x10000>;
 224                                 read-only;
 225                         };
 226
 227                         partition@3c0000 {
 228                                 label = "0:apdp";
 229                                 reg = <0x3c0000 0x10000>;
 230                                 read-only;
 231                         };
 232
 233                         partition@3d0000 {
 234                                 label = "0:apdp_1";
 235                                 reg = <0x3d0000 0x10000>;
 236                                 read-only;
 237                         };
 238
 239                         partition@3e0000 {
 240                                 label = "0:rpm";
 241                                 reg = <0x3e0000 0x40000>;
 242                                 read-only;
 243                         };
 244
 245                         partition@420000 {
 246                                 label = "0:rpm_1";
 247                                 reg = <0x420000 0x40000>;
 248                                 read-only;
 249                         };
 250
 251                         partition@460000 {
 252                                 label = "0:cdt";
 253                                 reg = <0x460000 0x10000>;
 254                                 read-only;
 255                         };
 256
 257                         partition@470000 {
 258                                 label = "0:cdt_1";
 259                                 reg = <0x470000 0x10000>;
 260                                 read-only;
 261                         };
 262
 263                         partition@480000 {
 264                                 label = "0:appsblenv";
 265                                 reg = <0x480000 0x10000>;
 266                         };
 267
 268                         partition@490000 {
 269                                 label = "0:appsbl";
 270                                 reg = <0x490000 0xa0000>;
 271                                 read-only;
 272                         };
 273
 274                         partition@550000 {
 275                                 label = "0:appsbl_1";
 276                                 reg = <0x530000 0xa0000>;
 277                                 read-only;
 278                         };
 279
 280                         partition@610000 {
 281                                 label = "0:art";
 282                                 reg = <0x5d0000 0x40000>;
 283                                 read-only;
 284                         };
 285
 286                         partition@650000 {
 287                                 label = "0:ethphyfw";
 288                                 reg = <0x610000 0x80000>;
 289                                 read-only;
 290                         };
 291                 };
 292         };
 293 };
 294
 295 &qpic_nand {
 296         status = "okay";
 297
 298         nand@0 {
 299                 reg = <0>;
 300                 nand-ecc-strength = <8>;
 301                 nand-ecc-step-size = <512>;
 302                 nand-bus-width = <8>;
 303
 304                 partitions {
 305                         compatible = "fixed-partitions";
 306                         #address-cells = <1>;
 307                         #size-cells = <1>;
 308
 309                         partition@0 {
 310                                 label = "rootfs";
 311                                 reg = <0x0000000 0x3400000>;
 312                         };
 313
 314                         partition@3400000 {
 315                                 label = "0:wififw";
 316                                 reg = <0x3400000 0x800000>;
 317                                 read-only;
 318                         };
 319
 320                         partition@3c00000 {
 321                                 label = "rootfs_1";
 322                                 reg = <0x3c00000 0x3400000>;
 323                         };
 324
 325                         partition@7000000 {
 326                                 label = "0:wififw_1";
 327                                 reg = <0x7000000 0x800000>;
 328                                 read-only;
 329                         };
 330                 };
 331         };
 332 };
 333
 334 &qusb_phy_0 {
 335         status = "okay";
 336 };
 337
 338 &qusb_phy_1 {
 339         status = "okay";
 340 };
 341
 342 &ssphy_0 {
 343         status = "okay";
 344 };
 345
 346 &ssphy_1 {
 347         status = "okay";
 348 };
 349
 350 &usb_0 {
 351         status = "okay";
 352 };
 353
 354 &usb_1 {
 355         status = "okay";
 356 };
 357
 358
 359 &mdio {
 360         status = "okay";
 361         pinctrl-0 = <&mdio_pins>;
 362         pinctrl-names = "default";
 363         reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 364
 365         qca8075_1: ethernet-phy@1 {
 366                 compatible = "ethernet-phy-ieee802.3-c22";
 367                 reg = <1>;
 368         };
 369
 370         qca8075_2: ethernet-phy@2 {
 371                 compatible = "ethernet-phy-ieee802.3-c22";
 372                 reg = <2>;
 373         };
 374
 375         qca8075_3: ethernet-phy@3 {
 376                 compatible = "ethernet-phy-ieee802.3-c22";
 377                 reg = <3>;
 378         };
 379
 380         qca8081: ethernet-phy@28 {
 381                 compatible = "ethernet-phy-ieee802.3-c22";
 382                 reg = <28>;
 383                 reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
 384         };
 385
 386 };
 387
 388 &switch {
 389         status = "okay";
 390
 391         switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
 392         switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
 393         switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
 394         switch_mac_mode1 = <0x0f>; /* mac mode for uniphy instance1*/
 395         switch_mac_mode2 = <0x0f>; /* mac mode for uniphy instance2*/
 396         bm_tick_mode = <0>; /* bm tick mode */
 397         tm_tick_mode = <0>; /* tm tick mode */
 398
 399         qcom,port_phyinfo {
 400                 port@2 {
 401                         port_id = <2>;
 402                         phy_address = <1>;
 403                 };
 404                 port@3 {
 405                         port_id = <3>;
 406                         phy_address = <2>;
 407                 };
 408                 port@4 {
 409                         port_id = <4>;
 410                         phy_address = <3>;
 411                 };
 412                 port@5 {
 413                         port_id = <6>;
 414                         phy_address = <28>;
 415                         port_mac_sel = "QGMAC_PORT";
 416                 };
 417         };
 418 };
 419
 420 &edma {
 421         status = "okay";
 422 };
 423
 424 &dp2 {
 425         status = "okay";
 426         phy-handle = <&qca8075_1>;
 427         label = "lan1";
 428 };
 429
 430 &dp3 {
 431         status = "okay";
 432         phy-handle = <&qca8075_2>;
 433         label = "lan2";
 434 };
 435
 436 &dp4 {
 437         status = "okay";
 438         phy-handle = <&qca8075_3>;
 439         label = "lan3";
 440 };
 441
 442 &dp6 {
 443         status = "okay";
 444         phy-handle = <&qca8081>;
 445         label = "wan";
 446 };
 447
 448 &pcie_qmp0 {
 449         status = "okay";
 450 };
 451
 452 &pcie0 {
 453         status = "okay";
 454
 455         perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
 456
 457         bridge@0,0 {
 458                 reg = <0x00020000 0 0 0 0>;
 459                 #address-cells = <3>;
 460                 #size-cells = <2>;
 461                 ranges;
 462         };
 463 };
 464
 465 &pcie_qmp1 {
 466         status = "okay";
 467 };
 468
 469 &pcie1 {
 470         status = "okay";
 471
 472         perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
 473
 474         bridge@1,0 {
 475                 reg = <0x00010000 0 0 0 0>;
 476                 #address-cells = <3>;
 477                 #size-cells = <2>;
 478                 ranges;
 479         };
 480 };
 481
 482 &wifi {
 483         status = "okay";
 484
 485         qcom,ath11k-calibration-variant = "Compex-WPQ873";
 486 };