target/linux/mvebu/patches-5.15/100-aardvark-workaround-PCIe.patch

   1 Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout
   2 Date:   Tue,  2 Aug 2022 14:38:16 +0200
   3 Message-Id: <20220802123816.21817-1-pali@kernel.org>
   4 X-Mailer: git-send-email 2.20.1
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8 Precedence: bulk
   9 List-ID: <linux-pci.vger.kernel.org>
  10 X-Mailing-List: linux-pci@vger.kernel.org
  11
  12 Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
  13 document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251),
  14 that PCIe IP does not support a strong-ordered model for inbound posted vs.
  15 outbound completion.
  16
  17 As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control
  18 register must be set. It disables the ordering check in the core between
  19 Completions and Posted requests received from the link.
  20
  21 Marvell also suggests to do full memory barrier at the beginning of
  22 aardvark summary interrupt handler before calling interrupt handlers of
  23 endpoint drivers in order to minimize the risk for the race condition
  24 documented in the Erratum between the DMA done status reading and the
  25 completion of writing to the host memory.
  26
  27 More details about this issue and suggested workarounds are in discussion:
  28 https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u
  29
  30 It was reported that enabling this workaround fixes instability issues and
  31 "Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm
  32 QCA6335 chip under significant load which were caused by interrupt status
  33 stuck in the outbound CMPLT queue traced back to this erratum.
  34
  35 This workaround fixes also kernel panic triggered after some minutes of
  36 usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip:
  37
  38     Internal error: synchronous external abort: 96000210 [#1] SMP
  39     Kernel panic - not syncing: Fatal exception in interrupt
  40
  41 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  42 Signed-off-by: Pali Rohár <pali@kernel.org>
  43 Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
  44 Cc: stable@vger.kernel.org
  45 ---
  46  drivers/pci/controller/pci-aardvark.c | 10 ++++++++++
  47  1 file changed, 10 insertions(+)
  48
  49 --- a/drivers/pci/controller/pci-aardvark.c
  50 +++ b/drivers/pci/controller/pci-aardvark.c
  51 @@ -210,6 +210,8 @@ enum {
  52  };
  53
  54  #define VENDOR_ID_REG                          (LMI_BASE_ADDR + 0x44)
  55 +#define DEBUG_MUX_CTRL_REG                     (LMI_BASE_ADDR + 0x208)
  56 +#define     DIS_ORD_CHK                                BIT(30)
  57
  58  /* PCIe core controller registers */
  59  #define CTRL_CORE_BASE_ADDR                    0x18000
  60 @@ -558,6 +560,11 @@ static void advk_pcie_setup_hw(struct ad
  61                 PCIE_CORE_CTRL2_TD_ENABLE;
  62         advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  63
  64 +       /* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */
  65 +       reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG);
  66 +       reg |= DIS_ORD_CHK;
  67 +       advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG);
  68 +
  69         /* Set lane X1 */
  70         reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  71         reg &= ~LANE_CNT_MSK;
  72 @@ -1580,6 +1587,9 @@ static irqreturn_t advk_pcie_irq_handler
  73         struct advk_pcie *pcie = arg;
  74         u32 status;
  75
  76 +       /* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */
  77 +       mb();
  78 +
  79         status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
  80         if (!(status & PCIE_IRQ_CORE_INT))
  81                 return IRQ_NONE;