f7d7b4cf08c12150ae700d63b4db2ba4167f8247
[openwrt/staging/jow.git] / target / linux / mpc85xx / files / arch / powerpc / boot / dts / br200-wp.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Aerohive BR200-WP Device Tree Source
4 *
5 * Based on: Aerohive HiveAP-330 Device Tree Source
6 *
7 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
8 * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
9 */
10
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/gpio/gpio.h>
14
15 /include/ "fsl/p1020si-pre.dtsi"
16
17 / {
18 model = "Aerohive BR200-WP";
19 compatible = "aerohive,br200-wp";
20
21 chosen {
22 bootargs = "console=ttyS0,9600";
23 bootargs-override = "console=ttyS0,9600 noinitrd";
24 };
25
26 aliases {
27 led-boot = &led_attention;
28 led-failsafe = &led_attention;
29 led-running = &led_status;
30 led-upgrade = &led_status;
31 label-mac-device = &enet0;
32 };
33
34 memory {
35 device_type = "memory";
36 };
37
38 cpus {
39 /delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
40 };
41
42 board_lbc: lbc: localbus@ffe05000 {
43 reg = <0 0xffe05000 0 0x1000>;
44 ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
45
46 nor@0,0 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "cfi-flash";
50 reg = <0x0 0x0 0x4000000>;
51 bank-width = <2>;
52 device-width = <1>;
53
54 partitions {
55 compatible = "fixed-partitions";
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 partition@0 {
60 reg = <0x0 0x40000>;
61 label = "dtb";
62 };
63
64 partition@40000 {
65 reg = <0x40000 0x40000>;
66 label = "initramfs";
67 };
68
69 partition@80000 {
70 reg = <0x80000 0x27c0000>;
71 label = "rootfs";
72 };
73
74 partition@2840000 {
75 reg = <0x2840000 0x800000>;
76 label = "kernel";
77 };
78
79 partition@3040000 {
80 reg = <0x3040000 0xec0000>;
81 label = "stock-jffs2";
82 read-only;
83 };
84
85 partition@3f00000 {
86 reg = <0x3f00000 0x20000>;
87 label = "hw-info";
88 read-only;
89
90 nvmem-layout {
91 compatible = "fixed-layout";
92 #address-cells = <1>;
93 #size-cells = <1>;
94
95 macaddr_hwinfo_0: macaddr@0 {
96 compatible = "mac-base";
97 reg = <0x0 0x6>;
98 #nvmem-cell-cells = <1>;
99 };
100 };
101 };
102
103 partition@3f20000 {
104 reg = <0x3f20000 0x20000>;
105 label = "boot-info";
106 read-only;
107 };
108
109 partition@3f40000 {
110 reg = <0x3f40000 0x20000>;
111 label = "boot-info-backup";
112 read-only;
113 };
114
115 partition@3f60000 {
116 reg = <0x3f60000 0x20000>;
117 label = "u-boot-env";
118 };
119
120 partition@3f80000 {
121 reg = <0x3f80000 0x80000>;
122 label = "u-boot";
123 read-only;
124 };
125
126 firmware@0 {
127 reg = <0x0 0x3040000>;
128 label = "firmware";
129 };
130 };
131 };
132 };
133
134 board_soc: soc: soc@ffe00000 {
135 ranges = <0x0 0x0 0xffe00000 0x100000>;
136
137 mdio@24000 {
138
139 phy_port1: phy@0 {
140 reg = <0>;
141 };
142
143 phy_port2: phy@1 {
144 reg = <1>;
145 };
146
147 phy_port3: phy@2 {
148 reg = <2>;
149 };
150
151 phy_port4: phy@3 {
152 reg = <3>;
153 };
154
155 phy_port5: phy@4 {
156 reg = <4>;
157 };
158
159 switch@10 {
160 compatible = "qca,qca8327";
161 #address-cells = <1>;
162 #size-cells = <0>;
163 reg = <0x10>;
164 reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
165
166 ports {
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 port@1 {
171 reg = <1>;
172 label = "lan1";
173 phy-handle = <&phy_port1>;
174 nvmem-cells = <&macaddr_hwinfo_0 2>;
175 nvmem-cell-names = "mac-address";
176 };
177
178 port@2 {
179 reg = <2>;
180 label = "lan2";
181 phy-handle = <&phy_port2>;
182 nvmem-cells = <&macaddr_hwinfo_0 3>;
183 nvmem-cell-names = "mac-address";
184 };
185
186 port@3 {
187 reg = <3>;
188 label = "lan3";
189 phy-handle = <&phy_port3>;
190 nvmem-cells = <&macaddr_hwinfo_0 4>;
191 nvmem-cell-names = "mac-address";
192 };
193
194 port@4 {
195 reg = <4>;
196 label = "lan4";
197 phy-handle = <&phy_port4>;
198 nvmem-cells = <&macaddr_hwinfo_0 5>;
199 nvmem-cell-names = "mac-address";
200 };
201
202 port@5 {
203 reg = <5>;
204 label = "wan";
205 phy-handle = <&phy_port5>;
206 nvmem-cells = <&macaddr_hwinfo_0 0>;
207 nvmem-cell-names = "mac-address";
208 };
209
210 port@6 {
211 reg = <6>;
212 ethernet = <&enet0>;
213 phy-mode = "rgmii-id";
214
215 fixed-link {
216 speed = <1000>;
217 full-duplex;
218 };
219 };
220 };
221 };
222 };
223
224 mdio@25000 {
225 status = "disabled";
226 };
227
228 mdio@26000 {
229 status = "disabled";
230 };
231
232 enet0: ethernet@b0000 {
233 status = "okay";
234 phy-connection-type = "rgmii-id";
235 nvmem-cells = <&macaddr_hwinfo_0 0>;
236 nvmem-cell-names = "mac-address";
237
238 fixed-link {
239 speed = <1000>;
240 full-duplex;
241 };
242 };
243
244 enet1: ethernet@b1000 {
245 status = "disabled";
246 };
247
248 enet2: ethernet@b2000 {
249 status = "disabled";
250 };
251
252 gpio0: gpio-controller@fc00 {
253 };
254
255 usb@22000 {
256 phy_type = "ulpi";
257 dr_mode = "host";
258 };
259
260 usb@23000 {
261 status = "disabled";
262 };
263 };
264
265 pci0: pcie@ffe09000 {
266 status = "disabled";
267 };
268
269 pci1: pcie@ffe0a000 {
270 reg = <0x0 0xffe0a000 0x0 0x1000>;
271 ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
272 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
273
274 reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
275
276 pcie@0 {
277 ranges = <0x2000000 0x0 0xc0000000
278 0x2000000 0x0 0xc0000000
279 0x0 0x20000000
280
281 0x1000000 0x0 0x0
282 0x1000000 0x0 0x0
283 0x0 0x100000>;
284
285 ath9k: wifi@0,0 {
286 reg = <0x0000 0 0 0 0>;
287 #gpio-cells = <2>;
288 gpio-controller;
289 nvmem-cells = <&macaddr_hwinfo_0 16>;
290 nvmem-cell-names = "mac-address";
291 };
292 };
293 };
294
295 leds {
296 compatible = "gpio-leds";
297
298 led_attention: led-0 {
299 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
300 label = "amber:status";
301 color = <LED_COLOR_ID_AMBER>;
302 function = LED_FUNCTION_STATUS;
303 };
304
305 led_status: led-1 {
306 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
307 label = "white:status";
308 color = <LED_COLOR_ID_WHITE>;
309 function = LED_FUNCTION_STATUS;
310 };
311 };
312
313 buttons {
314 compatible = "gpio-keys";
315
316 reset {
317 label = "Reset button";
318 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
319 linux,code = <KEY_RESTART>;
320 };
321 };
322 };
323
324 /include/ "fsl/p1020si-post.dtsi"
325
326 / {
327 chosen {
328 stdout-path = "/soc@ffe00000/serial@4500";
329 };
330
331 cpus {
332 PowerPC,P1020@0 {
333 i-cache-sets = <0x80>;
334 i-cache-size = <0x8000>;
335 i-cache-block-size = <0x20>;
336 d-cache-sets = <0x80>;
337 d-cache-size = <0x8000>;
338 d-cache-block-size = <0x20>;
339 clock-frequency = <0x2756cd00>;
340 bus-frequency = <0x13ab6680>;
341 timebase-frequency = <0x2756cd0>;
342 };
343 };
344
345 memory {
346 reg = <0x00 0x00 0x00 0x10000000>;
347 };
348
349 localbus@ffe05000 {
350 bus-frequency = <0x13ab668>;
351 };
352
353 soc@ffe00000 {
354 bus-frequency = <0x13ab6680>;
355
356 serial@4500 {
357 clock-frequency = <0x13ab6680>;
358 };
359
360 serial@4600 {
361 clock-frequency = <0x13ab6680>;
362 };
363 };
364
365 pcie@ffe09000 {
366 clock-frequency = <0x1fca055>;
367 };
368
369 pcie@ffe0a000 {
370 clock-frequency = <0x1fca055>;
371 };
372 };