target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch

   1 From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
   2 From: Sam Shih <sam.shih@mediatek.com>
   3 Date: Sun, 17 Dec 2023 21:49:33 +0000
   4 Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
   5
   6 Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
   7 ethernet and xfipll subsystem clocks.
   8
   9 Signed-off-by: Sam Shih <sam.shih@mediatek.com>
  10 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  11 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  13 Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
  14 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  15 ---
  16  .../dt-bindings/clock/mediatek,mt7988-clk.h   | 280 ++++++++++++++++++
  17  1 file changed, 280 insertions(+)
  18  create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
  19
  20 --- /dev/null
  21 +++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
  22 @@ -0,0 +1,280 @@
  23 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  24 +/*
  25 + * Copyright (c) 2023 MediaTek Inc.
  26 + * Author: Sam Shih <sam.shih@mediatek.com>
  27 + * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
  28 + */
  29 +
  30 +#ifndef _DT_BINDINGS_CLK_MT7988_H
  31 +#define _DT_BINDINGS_CLK_MT7988_H
  32 +
  33 +/* APMIXEDSYS */
  34 +
  35 +#define CLK_APMIXED_NETSYSPLL                  0
  36 +#define CLK_APMIXED_MPLL                       1
  37 +#define CLK_APMIXED_MMPLL                      2
  38 +#define CLK_APMIXED_APLL2                      3
  39 +#define CLK_APMIXED_NET1PLL                    4
  40 +#define CLK_APMIXED_NET2PLL                    5
  41 +#define CLK_APMIXED_WEDMCUPLL                  6
  42 +#define CLK_APMIXED_SGMPLL                     7
  43 +#define CLK_APMIXED_ARM_B                      8
  44 +#define CLK_APMIXED_CCIPLL2_B                  9
  45 +#define CLK_APMIXED_USXGMIIPLL                 10
  46 +#define CLK_APMIXED_MSDCPLL                    11
  47 +
  48 +/* TOPCKGEN */
  49 +
  50 +#define CLK_TOP_XTAL                           0
  51 +#define CLK_TOP_XTAL_D2                                1
  52 +#define CLK_TOP_RTC_32K                                2
  53 +#define CLK_TOP_RTC_32P7K                      3
  54 +#define CLK_TOP_MPLL_D2                                4
  55 +#define CLK_TOP_MPLL_D3_D2                     5
  56 +#define CLK_TOP_MPLL_D4                                6
  57 +#define CLK_TOP_MPLL_D8                                7
  58 +#define CLK_TOP_MPLL_D8_D2                     8
  59 +#define CLK_TOP_MMPLL_D2                       9
  60 +#define CLK_TOP_MMPLL_D3_D5                    10
  61 +#define CLK_TOP_MMPLL_D4                       11
  62 +#define CLK_TOP_MMPLL_D6_D2                    12
  63 +#define CLK_TOP_MMPLL_D8                       13
  64 +#define CLK_TOP_APLL2_D4                       14
  65 +#define CLK_TOP_NET1PLL_D4                     15
  66 +#define CLK_TOP_NET1PLL_D5                     16
  67 +#define CLK_TOP_NET1PLL_D5_D2                  17
  68 +#define CLK_TOP_NET1PLL_D5_D4                  18
  69 +#define CLK_TOP_NET1PLL_D8                     19
  70 +#define CLK_TOP_NET1PLL_D8_D2                  20
  71 +#define CLK_TOP_NET1PLL_D8_D4                  21
  72 +#define CLK_TOP_NET1PLL_D8_D8                  22
  73 +#define CLK_TOP_NET1PLL_D8_D16                 23
  74 +#define CLK_TOP_NET2PLL_D2                     24
  75 +#define CLK_TOP_NET2PLL_D4                     25
  76 +#define CLK_TOP_NET2PLL_D4_D4                  26
  77 +#define CLK_TOP_NET2PLL_D4_D8                  27
  78 +#define CLK_TOP_NET2PLL_D6                     28
  79 +#define CLK_TOP_NET2PLL_D8                     29
  80 +#define CLK_TOP_NETSYS_SEL                     30
  81 +#define CLK_TOP_NETSYS_500M_SEL                        31
  82 +#define CLK_TOP_NETSYS_2X_SEL                  32
  83 +#define CLK_TOP_NETSYS_GSW_SEL                 33
  84 +#define CLK_TOP_ETH_GMII_SEL                   34
  85 +#define CLK_TOP_NETSYS_MCU_SEL                 35
  86 +#define CLK_TOP_NETSYS_PAO_2X_SEL              36
  87 +#define CLK_TOP_EIP197_SEL                     37
  88 +#define CLK_TOP_AXI_INFRA_SEL                  38
  89 +#define CLK_TOP_UART_SEL                       39
  90 +#define CLK_TOP_EMMC_250M_SEL                  40
  91 +#define CLK_TOP_EMMC_400M_SEL                  41
  92 +#define CLK_TOP_SPI_SEL                                42
  93 +#define CLK_TOP_SPIM_MST_SEL                   43
  94 +#define CLK_TOP_NFI1X_SEL                      44
  95 +#define CLK_TOP_SPINFI_SEL                     45
  96 +#define CLK_TOP_PWM_SEL                                46
  97 +#define CLK_TOP_I2C_SEL                                47
  98 +#define CLK_TOP_PCIE_MBIST_250M_SEL            48
  99 +#define CLK_TOP_PEXTP_TL_SEL                   49
 100 +#define CLK_TOP_PEXTP_TL_P1_SEL                        50
 101 +#define CLK_TOP_PEXTP_TL_P2_SEL                        51
 102 +#define CLK_TOP_PEXTP_TL_P3_SEL                        52
 103 +#define CLK_TOP_USB_SYS_SEL                    53
 104 +#define CLK_TOP_USB_SYS_P1_SEL                 54
 105 +#define CLK_TOP_USB_XHCI_SEL                   55
 106 +#define CLK_TOP_USB_XHCI_P1_SEL                        56
 107 +#define CLK_TOP_USB_FRMCNT_SEL                 57
 108 +#define CLK_TOP_USB_FRMCNT_P1_SEL              58
 109 +#define CLK_TOP_AUD_SEL                                59
 110 +#define CLK_TOP_A1SYS_SEL                      60
 111 +#define CLK_TOP_AUD_L_SEL                      61
 112 +#define CLK_TOP_A_TUNER_SEL                    62
 113 +#define CLK_TOP_SSPXTP_SEL                     63
 114 +#define CLK_TOP_USB_PHY_SEL                    64
 115 +#define CLK_TOP_USXGMII_SBUS_0_SEL             65
 116 +#define CLK_TOP_USXGMII_SBUS_1_SEL             66
 117 +#define CLK_TOP_SGM_0_SEL                      67
 118 +#define CLK_TOP_SGM_SBUS_0_SEL                 68
 119 +#define CLK_TOP_SGM_1_SEL                      69
 120 +#define CLK_TOP_SGM_SBUS_1_SEL                 70
 121 +#define CLK_TOP_XFI_PHY_0_XTAL_SEL             71
 122 +#define CLK_TOP_XFI_PHY_1_XTAL_SEL             72
 123 +#define CLK_TOP_SYSAXI_SEL                     73
 124 +#define CLK_TOP_SYSAPB_SEL                     74
 125 +#define CLK_TOP_ETH_REFCK_50M_SEL              75
 126 +#define CLK_TOP_ETH_SYS_200M_SEL               76
 127 +#define CLK_TOP_ETH_SYS_SEL                    77
 128 +#define CLK_TOP_ETH_XGMII_SEL                  78
 129 +#define CLK_TOP_BUS_TOPS_SEL                   79
 130 +#define CLK_TOP_NPU_TOPS_SEL                   80
 131 +#define CLK_TOP_DRAMC_SEL                      81
 132 +#define CLK_TOP_DRAMC_MD32_SEL                 82
 133 +#define CLK_TOP_INFRA_F26M_SEL                 83
 134 +#define CLK_TOP_PEXTP_P0_SEL                   84
 135 +#define CLK_TOP_PEXTP_P1_SEL                   85
 136 +#define CLK_TOP_PEXTP_P2_SEL                   86
 137 +#define CLK_TOP_PEXTP_P3_SEL                   87
 138 +#define CLK_TOP_DA_XTP_GLB_P0_SEL              88
 139 +#define CLK_TOP_DA_XTP_GLB_P1_SEL              89
 140 +#define CLK_TOP_DA_XTP_GLB_P2_SEL              90
 141 +#define CLK_TOP_DA_XTP_GLB_P3_SEL              91
 142 +#define CLK_TOP_CKM_SEL                                92
 143 +#define CLK_TOP_DA_SEL                         93
 144 +#define CLK_TOP_PEXTP_SEL                      94
 145 +#define CLK_TOP_TOPS_P2_26M_SEL                        95
 146 +#define CLK_TOP_MCUSYS_BACKUP_625M_SEL         96
 147 +#define CLK_TOP_NETSYS_SYNC_250M_SEL           97
 148 +#define CLK_TOP_MACSEC_SEL                     98
 149 +#define CLK_TOP_NETSYS_TOPS_400M_SEL           99
 150 +#define CLK_TOP_NETSYS_PPEFB_250M_SEL          100
 151 +#define CLK_TOP_NETSYS_WARP_SEL                        101
 152 +#define CLK_TOP_ETH_MII_SEL                    102
 153 +#define CLK_TOP_NPU_SEL                                103
 154 +#define CLK_TOP_AUD_I2S_M                      104
 155 +
 156 +/* MCUSYS */
 157 +
 158 +#define CLK_MCU_BUS_DIV_SEL                    0
 159 +#define CLK_MCU_ARM_DIV_SEL                    1
 160 +
 161 +/* INFRACFG_AO */
 162 +
 163 +#define CLK_INFRA_MUX_UART0_SEL                        0
 164 +#define CLK_INFRA_MUX_UART1_SEL                        1
 165 +#define CLK_INFRA_MUX_UART2_SEL                        2
 166 +#define CLK_INFRA_MUX_SPI0_SEL                 3
 167 +#define CLK_INFRA_MUX_SPI1_SEL                 4
 168 +#define CLK_INFRA_MUX_SPI2_SEL                 5
 169 +#define CLK_INFRA_PWM_SEL                      6
 170 +#define CLK_INFRA_PWM_CK1_SEL                  7
 171 +#define CLK_INFRA_PWM_CK2_SEL                  8
 172 +#define CLK_INFRA_PWM_CK3_SEL                  9
 173 +#define CLK_INFRA_PWM_CK4_SEL                  10
 174 +#define CLK_INFRA_PWM_CK5_SEL                  11
 175 +#define CLK_INFRA_PWM_CK6_SEL                  12
 176 +#define CLK_INFRA_PWM_CK7_SEL                  13
 177 +#define CLK_INFRA_PWM_CK8_SEL                  14
 178 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL       15
 179 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL       16
 180 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL       17
 181 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL       18
 182 +
 183 +/* INFRACFG */
 184 +
 185 +#define CLK_INFRA_PCIE_PERI_26M_CK_P0          19
 186 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1          20
 187 +#define CLK_INFRA_PCIE_PERI_26M_CK_P2          21
 188 +#define CLK_INFRA_PCIE_PERI_26M_CK_P3          22
 189 +#define CLK_INFRA_66M_GPT_BCK                  23
 190 +#define CLK_INFRA_66M_PWM_HCK                  24
 191 +#define CLK_INFRA_66M_PWM_BCK                  25
 192 +#define CLK_INFRA_66M_PWM_CK1                  26
 193 +#define CLK_INFRA_66M_PWM_CK2                  27
 194 +#define CLK_INFRA_66M_PWM_CK3                  28
 195 +#define CLK_INFRA_66M_PWM_CK4                  29
 196 +#define CLK_INFRA_66M_PWM_CK5                  30
 197 +#define CLK_INFRA_66M_PWM_CK6                  31
 198 +#define CLK_INFRA_66M_PWM_CK7                  32
 199 +#define CLK_INFRA_66M_PWM_CK8                  33
 200 +#define CLK_INFRA_133M_CQDMA_BCK               34
 201 +#define CLK_INFRA_66M_AUD_SLV_BCK              35
 202 +#define CLK_INFRA_AUD_26M                      36
 203 +#define CLK_INFRA_AUD_L                                37
 204 +#define CLK_INFRA_AUD_AUD                      38
 205 +#define CLK_INFRA_AUD_EG2                      39
 206 +#define CLK_INFRA_DRAMC_F26M                   40
 207 +#define CLK_INFRA_133M_DBG_ACKM                        41
 208 +#define CLK_INFRA_66M_AP_DMA_BCK               42
 209 +#define CLK_INFRA_66M_SEJ_BCK                  43
 210 +#define CLK_INFRA_PRE_CK_SEJ_F13M              44
 211 +#define CLK_INFRA_26M_THERM_SYSTEM             45
 212 +#define CLK_INFRA_I2C_BCK                      46
 213 +#define CLK_INFRA_52M_UART0_CK                 47
 214 +#define CLK_INFRA_52M_UART1_CK                 48
 215 +#define CLK_INFRA_52M_UART2_CK                 49
 216 +#define CLK_INFRA_NFI                          50
 217 +#define CLK_INFRA_SPINFI                       51
 218 +#define CLK_INFRA_66M_NFI_HCK                  52
 219 +#define CLK_INFRA_104M_SPI0                    53
 220 +#define CLK_INFRA_104M_SPI1                    54
 221 +#define CLK_INFRA_104M_SPI2_BCK                        55
 222 +#define CLK_INFRA_66M_SPI0_HCK                 56
 223 +#define CLK_INFRA_66M_SPI1_HCK                 57
 224 +#define CLK_INFRA_66M_SPI2_HCK                 58
 225 +#define CLK_INFRA_66M_FLASHIF_AXI              59
 226 +#define CLK_INFRA_RTC                          60
 227 +#define CLK_INFRA_26M_ADC_BCK                  61
 228 +#define CLK_INFRA_RC_ADC                       62
 229 +#define CLK_INFRA_MSDC400                      63
 230 +#define CLK_INFRA_MSDC2_HCK                    64
 231 +#define CLK_INFRA_133M_MSDC_0_HCK              65
 232 +#define CLK_INFRA_66M_MSDC_0_HCK               66
 233 +#define CLK_INFRA_133M_CPUM_BCK                        67
 234 +#define CLK_INFRA_BIST2FPC                     68
 235 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1           69
 236 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1           70
 237 +#define CLK_INFRA_133M_USB_HCK                 71
 238 +#define CLK_INFRA_133M_USB_HCK_CK_P1           72
 239 +#define CLK_INFRA_66M_USB_HCK                  73
 240 +#define CLK_INFRA_66M_USB_HCK_CK_P1            74
 241 +#define CLK_INFRA_USB_SYS                      75
 242 +#define CLK_INFRA_USB_SYS_CK_P1                        76
 243 +#define CLK_INFRA_USB_REF                      77
 244 +#define CLK_INFRA_USB_CK_P1                    78
 245 +#define CLK_INFRA_USB_FRMCNT                   79
 246 +#define CLK_INFRA_USB_FRMCNT_CK_P1             80
 247 +#define CLK_INFRA_USB_PIPE                     81
 248 +#define CLK_INFRA_USB_PIPE_CK_P1               82
 249 +#define CLK_INFRA_USB_UTMI                     83
 250 +#define CLK_INFRA_USB_UTMI_CK_P1               84
 251 +#define CLK_INFRA_USB_XHCI                     85
 252 +#define CLK_INFRA_USB_XHCI_CK_P1               86
 253 +#define CLK_INFRA_PCIE_GFMUX_TL_P0             87
 254 +#define CLK_INFRA_PCIE_GFMUX_TL_P1             88
 255 +#define CLK_INFRA_PCIE_GFMUX_TL_P2             89
 256 +#define CLK_INFRA_PCIE_GFMUX_TL_P3             90
 257 +#define CLK_INFRA_PCIE_PIPE_P0                 91
 258 +#define CLK_INFRA_PCIE_PIPE_P1                 92
 259 +#define CLK_INFRA_PCIE_PIPE_P2                 93
 260 +#define CLK_INFRA_PCIE_PIPE_P3                 94
 261 +#define CLK_INFRA_133M_PCIE_CK_P0              95
 262 +#define CLK_INFRA_133M_PCIE_CK_P1              96
 263 +#define CLK_INFRA_133M_PCIE_CK_P2              97
 264 +#define CLK_INFRA_133M_PCIE_CK_P3              98
 265 +
 266 +/* ETHDMA */
 267 +
 268 +#define CLK_ETHDMA_XGP1_EN                     0
 269 +#define CLK_ETHDMA_XGP2_EN                     1
 270 +#define CLK_ETHDMA_XGP3_EN                     2
 271 +#define CLK_ETHDMA_FE_EN                       3
 272 +#define CLK_ETHDMA_GP2_EN                      4
 273 +#define CLK_ETHDMA_GP1_EN                      5
 274 +#define CLK_ETHDMA_GP3_EN                      6
 275 +#define CLK_ETHDMA_ESW_EN                      7
 276 +#define CLK_ETHDMA_CRYPT0_EN                   8
 277 +#define CLK_ETHDMA_NR_CLK                      9
 278 +
 279 +/* SGMIISYS_0 */
 280 +
 281 +#define CLK_SGM0_TX_EN                         0
 282 +#define CLK_SGM0_RX_EN                         1
 283 +#define CLK_SGMII0_NR_CLK                      2
 284 +
 285 +/* SGMIISYS_1 */
 286 +
 287 +#define CLK_SGM1_TX_EN                         0
 288 +#define CLK_SGM1_RX_EN                         1
 289 +#define CLK_SGMII1_NR_CLK                      2
 290 +
 291 +/* ETHWARP */
 292 +
 293 +#define CLK_ETHWARP_WOCPU2_EN                  0
 294 +#define CLK_ETHWARP_WOCPU1_EN                  1
 295 +#define CLK_ETHWARP_WOCPU0_EN                  2
 296 +#define CLK_ETHWARP_NR_CLK                     3
 297 +
 298 +/* XFIPLL */
 299 +#define CLK_XFIPLL_PLL                         0
 300 +#define CLK_XFIPLL_PLL_EN                      1
 301 +
 302 +#endif /* _DT_BINDINGS_CLK_MT7988_H */