target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch

   1 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
   2 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
   3 @@ -1,7 +1,6 @@
   4  /*
   5 - * Copyright (c) 2017 MediaTek Inc.
   6 - * Author: Ming Huang <ming.huang@mediatek.com>
   7 - *        Sean Wang <sean.wang@mediatek.com>
   8 + * Copyright (c) 2018 MediaTek Inc.
   9 + * Author: Ryder Lee <ryder.lee@mediatek.com>
  10   *
  11   * SPDX-License-Identifier: (GPL-2.0 OR MIT)
  12   */
  13 @@ -24,7 +23,7 @@
  14
  15         chosen {
  16                 stdout-path = "serial0:115200n8";
  17 -               bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  18 +               bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
  19         };
  20
  21         cpus {
  22 @@ -45,18 +44,18 @@
  23                 key-factory {
  24                         label = "factory";
  25                         linux,code = <BTN_0>;
  26 -                       gpios = <&pio 0 0>;
  27 +                       gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  28                 };
  29
  30                 key-wps {
  31                         label = "wps";
  32                         linux,code = <KEY_WPS_BUTTON>;
  33 -                       gpios = <&pio 102 0>;
  34 +                       gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  35                 };
  36         };
  37
  38         memory {
  39 -               reg = <0 0x40000000 0 0x20000000>;
  40 +               reg = <0 0x40000000 0 0x40000000>;
  41         };
  42
  43         reg_1p8v: regulator-1p8v {
  44 @@ -132,22 +131,22 @@
  45
  46                                 port@0 {
  47                                         reg = <0>;
  48 -                                       label = "lan0";
  49 +                                       label = "lan1";
  50                                 };
  51
  52                                 port@1 {
  53                                         reg = <1>;
  54 -                                       label = "lan1";
  55 +                                       label = "lan2";
  56                                 };
  57
  58                                 port@2 {
  59                                         reg = <2>;
  60 -                                       label = "lan2";
  61 +                                       label = "lan3";
  62                                 };
  63
  64                                 port@3 {
  65                                         reg = <3>;
  66 -                                       label = "lan3";
  67 +                                       label = "lan4";
  68                                 };
  69
  70                                 port@4 {
  71 @@ -240,7 +239,22 @@
  72         status = "okay";
  73  };
  74
  75 +&pcie1 {
  76 +       pinctrl-names = "default";
  77 +       pinctrl-0 = <&pcie1_pins>;
  78 +       status = "okay";
  79 +};
  80 +
  81  &pio {
  82 +       /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
  83 +        * SATA functions. i.e. output-high: PCIe, output-low: SATA
  84 +        */
  85 +       asm_sel {
  86 +               gpio-hog;
  87 +               gpios = <90 GPIO_ACTIVE_HIGH>;
  88 +               output-high;
  89 +       };
  90 +
  91         /* eMMC is shared pin with parallel NAND */
  92         emmc_pins_default: emmc-pins-default {
  93                 mux {
  94 @@ -517,11 +531,11 @@
  95  };
  96
  97  &sata {
  98 -       status = "okay";
  99 +       status = "disabled";
 100  };
 101
 102  &sata_phy {
 103 -       status = "okay";
 104 +       status = "disabled";
 105  };
 106
 107  &spi0 {