target/linux/mediatek/patches-5.4/1000-eth-gdm-config-backport.patch

   1 diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
   2 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c       2020-04-21 14:33:05.702816632 +0800
   3 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c       2020-04-21 14:33:19.590328084 +0800
   4 @@ -2191,6 +2191,31 @@
   5         return 0;
   6  }
   7
   8 +static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
   9 +{
  10 +       int i;
  11 +
  12 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  13 +               return;
  14 +
  15 +       for (i = 0; i < MTK_MAC_COUNT; i++) {
  16 +               u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
  17 +
  18 +               /* default setup the forward port to send frame to PDMA */
  19 +               val &= ~0xffff;
  20 +
  21 +               /* Enable RX checksum */
  22 +               val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
  23 +
  24 +               val |= config;
  25 +
  26 +               mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
  27 +       }
  28 +       /* Reset and enable PSE */
  29 +       mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
  30 +       mtk_w32(eth, 0, MTK_RST_GL);
  31 +}
  32 +
  33  static int mtk_open(struct net_device *dev)
  34  {
  35         struct mtk_mac *mac = netdev_priv(dev);
  36 @@ -2211,6 +2236,8 @@
  37                 if (err)
  38                         return err;
  39
  40 +               mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
  41 +
  42                 napi_enable(&eth->tx_napi);
  43                 napi_enable(&eth->rx_napi);
  44                 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
  45 @@ -2266,6 +2293,8 @@
  46         if (!refcount_dec_and_test(&eth->dma_refcnt))
  47                 return 0;
  48
  49 +       mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
  50 +
  51         mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
  52         mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
  53         napi_disable(&eth->tx_napi);
  54 @@ -2392,8 +2421,6 @@
  55         mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
  56         mtk_tx_irq_disable(eth, ~0);
  57         mtk_rx_irq_disable(eth, ~0);
  58 -       mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
  59 -       mtk_w32(eth, 0, MTK_RST_GL);
  60
  61         /* FE int grouping */
  62         mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
  63 @@ -2402,19 +2429,6 @@
  64         mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
  65         mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  66
  67 -       for (i = 0; i < MTK_MAC_COUNT; i++) {
  68 -               u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
  69 -
  70 -               /* setup the forward port to send frame to PDMA */
  71 -               val &= ~0xffff;
  72 -
  73 -               /* Enable RX checksum */
  74 -               val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
  75 -
  76 -               /* setup the mac dma */
  77 -               mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
  78 -       }
  79 -
  80         return 0;
  81
  82  err_disable_pm:
  83 diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  84 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h       2020-04-21 14:33:10.702640743 +0800
  85 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h       2020-04-21 14:33:24.902141220 +0800
  86 @@ -84,6 +84,8 @@
  87  #define MTK_GDMA_ICS_EN                BIT(22)
  88  #define MTK_GDMA_TCS_EN                BIT(21)
  89  #define MTK_GDMA_UCS_EN                BIT(20)
  90 +#define MTK_GDMA_TO_PDMA       0x0
  91 +#define MTK_GDMA_DROP_ALL      0x7777
  92
  93  /* Unicast Filter MAC Address Register - Low */
  94  #define MTK_GDMA_MAC_ADRL(x)   (0x508 + (x * 0x1000))