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mediatek: add hw flow table offloading
[openwrt/staging/jow.git] / target / linux / mediatek / patches-5.4 / 0999-hnat.patch
1 Index: linux-5.4.28/drivers/net/ethernet/mediatek/Kconfig
2 ===================================================================
3 --- linux-5.4.28.orig/drivers/net/ethernet/mediatek/Kconfig
4 +++ linux-5.4.28/drivers/net/ethernet/mediatek/Kconfig
5 @@ -14,4 +14,8 @@ config NET_MEDIATEK_SOC
6 This driver supports the gigabit ethernet MACs in the
7 MediaTek SoC family.
8
9 +config NET_MEDIATEK_OFFLOAD
10 + def_bool NET_MEDIATEK_SOC
11 + depends on NET_MEDIATEK_SOC
12 +
13 endif #NET_VENDOR_MEDIATEK
14 Index: linux-5.4.28/drivers/net/ethernet/mediatek/Makefile
15 ===================================================================
16 --- linux-5.4.28.orig/drivers/net/ethernet/mediatek/Makefile
17 +++ linux-5.4.28/drivers/net/ethernet/mediatek/Makefile
18 @@ -5,3 +5,4 @@
19
20 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
21 mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
22 +mtk_eth-$(CONFIG_NET_MEDIATEK_OFFLOAD) += mtk_offload.o mtk_debugfs.o
23 Index: linux-5.4.28/drivers/net/ethernet/mediatek/mtk_debugfs.c
24 ===================================================================
25 --- /dev/null
26 +++ linux-5.4.28/drivers/net/ethernet/mediatek/mtk_debugfs.c
27 @@ -0,0 +1,117 @@
28 +/* This program is free software; you can redistribute it and/or modify
29 + * it under the terms of the GNU General Public License as published by
30 + * the Free Software Foundation; version 2 of the License
31 + *
32 + * This program is distributed in the hope that it will be useful,
33 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 + * GNU General Public License for more details.
36 + *
37 + * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
38 + * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
39 + */
40 +
41 +#include "mtk_offload.h"
42 +
43 +static const char *mtk_foe_entry_state_str[] = {
44 + "INVALID",
45 + "UNBIND",
46 + "BIND",
47 + "FIN"
48 +};
49 +
50 +static const char *mtk_foe_packet_type_str[] = {
51 + "IPV4_HNAPT",
52 + "IPV4_HNAT",
53 + "IPV6_1T_ROUTE",
54 + "IPV4_DSLITE",
55 + "IPV6_3T_ROUTE",
56 + "IPV6_5T_ROUTE",
57 + "IPV6_6RD",
58 +};
59 +
60 +#define IPV4_HNAPT 0
61 +#define IPV4_HNAT 1
62 +#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1: 0)
63 +struct mtk_eth *_eth;
64 +#define es(entry) (mtk_foe_entry_state_str[entry->bfib1.state])
65 +//#define ei(entry, end) (MTK_PPE_TBL_SZ - (int)(end - entry))
66 +#define ei(entry, end) (MTK_PPE_ENTRY_CNT - (int)(end - entry))
67 +#define pt(entry) (mtk_foe_packet_type_str[entry->ipv4_hnapt.bfib1.pkt_type])
68 +
69 +static int mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private)
70 +{
71 + struct mtk_eth *eth = _eth;
72 + struct mtk_foe_entry *entry, *end;
73 + int i = 0;
74 +
75 + entry = eth->foe_table;
76 + end = eth->foe_table + MTK_PPE_ENTRY_CNT;
77 +
78 + while (entry < end) {
79 + if (!entry->bfib1.state) {
80 +
81 + } else if (IS_IPV4_HNAPT(entry)) {
82 + __be32 saddr = htonl(entry->ipv4_hnapt.sip);
83 + __be32 daddr = htonl(entry->ipv4_hnapt.dip);
84 + __be32 nsaddr = htonl(entry->ipv4_hnapt.new_sip);
85 + __be32 ndaddr = htonl(entry->ipv4_hnapt.new_dip);
86 + unsigned char h_dest[ETH_ALEN];
87 + unsigned char h_source[ETH_ALEN];
88 +
89 + *((u32*) h_source) = swab32(entry->ipv4_hnapt.smac_hi);
90 + *((u16*) &h_source[4]) = swab16(entry->ipv4_hnapt.smac_lo);
91 + *((u32*) h_dest) = swab32(entry->ipv4_hnapt.dmac_hi);
92 + *((u16*) &h_dest[4]) = swab16(entry->ipv4_hnapt.dmac_lo);
93 + seq_printf(m,
94 + "(%x)0x%05x|state=%s|type=%s|"
95 + "%pI4:%d->%pI4:%d=>%pI4:%d->%pI4:%d|%pM=>%pM|"
96 + "etype=0x%04x|info1=0x%x|info2=0x%x|"
97 + "vlan1=%d|vlan2=%d\n",
98 + i,
99 + ei(entry, end), es(entry), pt(entry),
100 + &saddr, entry->ipv4_hnapt.sport,
101 + &daddr, entry->ipv4_hnapt.dport,
102 + &nsaddr, entry->ipv4_hnapt.new_sport,
103 + &ndaddr, entry->ipv4_hnapt.new_dport, h_source,
104 + h_dest, ntohs(entry->ipv4_hnapt.etype),
105 + entry->ipv4_hnapt.info_blk1,
106 + entry->ipv4_hnapt.info_blk2,
107 + entry->ipv4_hnapt.vlan1,
108 + entry->ipv4_hnapt.vlan2);
109 + } else
110 + seq_printf(m, "0x%05x state=%s\n",
111 + ei(entry, end), es(entry));
112 + entry++;
113 + i++;
114 + }
115 +
116 + return 0;
117 +}
118 +
119 +static int mtk_ppe_debugfs_foe_open(struct inode *inode, struct file *file)
120 +{
121 + return single_open(file, mtk_ppe_debugfs_foe_show, file->private_data);
122 +}
123 +
124 +static const struct file_operations mtk_ppe_debugfs_foe_fops = {
125 + .open = mtk_ppe_debugfs_foe_open,
126 + .read = seq_read,
127 + .llseek = seq_lseek,
128 + .release = single_release,
129 +};
130 +
131 +int mtk_ppe_debugfs_init(struct mtk_eth *eth)
132 +{
133 + struct dentry *root;
134 +
135 + _eth = eth;
136 +
137 + root = debugfs_create_dir("mtk_ppe", NULL);
138 + if (!root)
139 + return -ENOMEM;
140 +
141 + debugfs_create_file("all_entry", S_IRUGO, root, eth, &mtk_ppe_debugfs_foe_fops);
142 +
143 + return 0;
144 +}
145 Index: linux-5.4.28/drivers/net/ethernet/mediatek/mtk_eth_soc.c
146 ===================================================================
147 --- linux-5.4.28.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.c
148 +++ linux-5.4.28/drivers/net/ethernet/mediatek/mtk_eth_soc.c
149 @@ -19,6 +19,8 @@
150 #include <linux/interrupt.h>
151 #include <linux/pinctrl/devinfo.h>
152 #include <linux/phylink.h>
153 +#include <linux/netfilter.h>
154 +#include <net/netfilter/nf_flow_table.h>
155
156 #include "mtk_eth_soc.h"
157
158 @@ -65,6 +67,18 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
159 return __raw_readl(eth->base + reg);
160 }
161
162 +void mtk_m32(struct mtk_eth *eth, u32 clear, u32 set, unsigned reg)
163 +{
164 + u32 val;
165 +
166 + spin_lock(&eth->page_lock);
167 + val = __raw_readl(eth->base + reg);
168 + val &= ~clear;
169 + val |= set;
170 + __raw_writel(val, eth->base + reg);
171 + spin_unlock(&eth->page_lock);
172 +}
173 +
174 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
175 {
176 unsigned long t_start = jiffies;
177 @@ -1276,8 +1290,16 @@ static int mtk_poll_rx(struct napi_struc
178 (trxd.rxd2 & RX_DMA_VTAG))
179 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
180 RX_DMA_VID(trxd.rxd3));
181 - skb_record_rx_queue(skb, 0);
182 - napi_gro_receive(napi, skb);
183 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
184 + if (mtk_offload_check_rx(eth, skb, trxd.rxd4) == 0) {
185 +#endif
186 + skb_record_rx_queue(skb, 0);
187 + napi_gro_receive(napi, skb);
188 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
189 + } else {
190 + dev_kfree_skb(skb);
191 + }
192 +#endif
193
194 ring->data[idx] = new_data;
195 rxd->rxd1 = (unsigned int)dma_addr;
196 @@ -2194,6 +2216,9 @@ static int mtk_open(struct net_device *d
197 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
198 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
199 refcount_set(&eth->dma_refcnt, 1);
200 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
201 + mtk_ppe_probe(eth);
202 +#endif
203 }
204 else
205 refcount_inc(&eth->dma_refcnt);
206 @@ -2252,6 +2277,9 @@ static int mtk_stop(struct net_device *d
207
208 mtk_dma_free(eth);
209
210 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
211 + mtk_ppe_remove(eth);
212 +#endif
213 return 0;
214 }
215
216 @@ -2711,6 +2739,27 @@ static int mtk_set_rxnfc(struct net_devi
217 return ret;
218 }
219
220 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
221 +static int
222 +mtk_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
223 + struct flow_offload_hw_path *src,
224 + struct flow_offload_hw_path *dest)
225 +{
226 + struct mtk_mac *mac = netdev_priv(src->dev);
227 + struct mtk_eth *eth = mac->hw;
228 +
229 + if (!eth->soc->offload_version)
230 + return -EINVAL;
231 +
232 + if (src->dev->base_addr != dest->dev->base_addr)
233 + return -EINVAL;
234 +
235 + mac = netdev_priv(src->dev);
236 +
237 + return mtk_flow_offload_add(eth, type, flow, src, dest);
238 +}
239 +#endif
240 +
241 static const struct ethtool_ops mtk_ethtool_ops = {
242 .get_link_ksettings = mtk_get_link_ksettings,
243 .set_link_ksettings = mtk_set_link_ksettings,
244 @@ -2742,6 +2791,9 @@ static const struct net_device_ops mtk_n
245 #ifdef CONFIG_NET_POLL_CONTROLLER
246 .ndo_poll_controller = mtk_poll_controller,
247 #endif
248 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
249 + .ndo_flow_offload = mtk_flow_offload,
250 +#endif
251 };
252
253 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
254 @@ -3075,6 +3127,7 @@ static const struct mtk_soc_data mt7622_
255 .hw_features = MTK_HW_FEATURES,
256 .required_clks = MT7622_CLKS_BITMAP,
257 .required_pctl = false,
258 + .offload_version = MTK_OFFLOAD_V2,
259 };
260
261 static const struct mtk_soc_data mt7623_data = {
262 Index: linux-5.4.28/drivers/net/ethernet/mediatek/mtk_eth_soc.h
263 ===================================================================
264 --- linux-5.4.28.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.h
265 +++ linux-5.4.28/drivers/net/ethernet/mediatek/mtk_eth_soc.h
266 @@ -771,6 +771,13 @@ enum mkt_eth_capabilities {
267 MTK_MUX_U3_GMAC2_TO_QPHY | \
268 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
269
270 +enum mtk_flow_offload_version {
271 + MTK_OFFLOAD_NONE = 0,
272 + MTK_OFFLOAD_V1,
273 + MTK_OFFLOAD_V2,
274 + MTK_OFFLOAD_V3,
275 +};
276 +
277 /* struct mtk_eth_data - This is the structure holding all differences
278 * among various plaforms
279 * @ana_rgc3: The offset for register ANA_RGC3 related to
280 @@ -788,6 +795,7 @@ struct mtk_soc_data {
281 u32 required_clks;
282 bool required_pctl;
283 netdev_features_t hw_features;
284 + enum mtk_flow_offload_version offload_version;
285 };
286
287 /* currently no SoC has more than 2 macs */
288 @@ -813,6 +821,23 @@ struct mtk_sgmii {
289 u32 ana_rgc3;
290 };
291
292 +
293 +struct mib_entry {
294 + u32 byt_cnt_l;
295 + u16 byt_cnt_h;
296 + u32 pkt_cnt_l;
297 + u8 pkt_cnt_h;
298 + u8 resv0;
299 + u32 resv1;
300 +} __packed __aligned(4);
301 +
302 +struct hnat_accounting {
303 + u64 bytes;
304 + u64 packets;
305 +};
306 +
307 +
308 +
309 /* struct mtk_eth - This is the main datasructure for holding the state
310 * of the driver
311 * @dev: The device pointer
312 @@ -886,6 +911,16 @@ struct mtk_eth {
313 u32 tx_int_status_reg;
314 u32 rx_dma_l4_valid;
315 int ip_align;
316 +
317 + struct reset_control *rst_ppe;
318 + struct mtk_foe_entry *foe_table;
319 + dma_addr_t foe_table_phys;
320 + struct flow_offload __rcu **foe_flow_table;
321 +
322 + struct mib_entry *foe_mib_cpu;
323 + dma_addr_t foe_mib_dev;
324 + struct hnat_accounting *acct;
325 + bool per_flow_accounting;
326 };
327
328 /* struct mtk_mac - the structure that holds the info about the MACs of the
329 @@ -918,6 +953,7 @@ void mtk_stats_update_mac(struct mtk_mac
330
331 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
332 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
333 +void mtk_m32(struct mtk_eth *eth, u32 clear, u32 set, unsigned reg);
334
335 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
336 u32 ana_rgc3);
337 @@ -930,4 +966,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk
338 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
339 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
340
341 +int mtk_ppe_probe(struct mtk_eth *eth);
342 +void mtk_ppe_remove(struct mtk_eth *eth);
343 +int mtk_flow_offload_add(struct mtk_eth *eth,
344 + enum flow_offload_type type,
345 + struct flow_offload *flow,
346 + struct flow_offload_hw_path *src,
347 + struct flow_offload_hw_path *dest);
348 +int mtk_offload_check_rx(struct mtk_eth *eth, struct sk_buff *skb, u32 rxd4);
349 +
350 #endif /* MTK_ETH_H */
351 Index: linux-5.4.28/drivers/net/ethernet/mediatek/mtk_offload.c
352 ===================================================================
353 --- /dev/null
354 +++ linux-5.4.28/drivers/net/ethernet/mediatek/mtk_offload.c
355 @@ -0,0 +1,593 @@
356 +/* This program is free software; you can redistribute it and/or modify
357 + * it under the terms of the GNU General Public License as published by
358 + * the Free Software Foundation; version 2 of the License
359 + *
360 + * This program is distributed in the hope that it will be useful,
361 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
362 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
363 + * GNU General Public License for more details.
364 + *
365 + * Copyright (C) 2018 John Crispin <john@phrozen.org>
366 + */
367 +
368 +#include "mtk_offload.h"
369 +
370 +#define INVALID 0
371 +#define UNBIND 1
372 +#define BIND 2
373 +#define FIN 3
374 +
375 +#define IPV4_HNAPT 0
376 +#define IPV4_HNAT 1
377 +
378 +static u32
379 +mtk_flow_hash_v4(struct flow_offload_tuple *tuple)
380 +{
381 + u32 ports = ntohs(tuple->src_port) << 16 | ntohs(tuple->dst_port);
382 + u32 src = ntohl(tuple->dst_v4.s_addr);
383 + u32 dst = ntohl(tuple->src_v4.s_addr);
384 + u32 hash = (ports & src) | ((~ports) & dst);
385 + u32 hash_23_0 = hash & 0xffffff;
386 + u32 hash_31_24 = hash & 0xff000000;
387 +
388 + hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24));
389 + hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff);
390 + hash &= 0x7ff;
391 + hash *= 2;;
392 +
393 + return hash;
394 +}
395 +
396 +static int
397 +mtk_foe_prepare_v4(struct mtk_foe_entry *entry,
398 + struct flow_offload_tuple *tuple,
399 + struct flow_offload_tuple *dest_tuple,
400 + struct flow_offload_hw_path *src,
401 + struct flow_offload_hw_path *dest)
402 +{
403 + int is_mcast = !!is_multicast_ether_addr(dest->eth_dest);
404 +
405 + if (tuple->l4proto == IPPROTO_UDP)
406 + entry->ipv4_hnapt.bfib1.udp = 1;
407 +
408 + entry->ipv4_hnapt.etype = htons(ETH_P_IP);
409 + entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT;
410 + entry->ipv4_hnapt.iblk2.fqos = 0;
411 + entry->ipv4_hnapt.bfib1.ttl = 1;
412 + entry->ipv4_hnapt.bfib1.cah = 1;
413 + entry->ipv4_hnapt.bfib1.ka = 1;
414 + entry->ipv4_hnapt.iblk2.mcast = is_mcast;
415 + entry->ipv4_hnapt.iblk2.dscp = 0;
416 + entry->ipv4_hnapt.iblk2.port_mg = 0x3f;
417 + entry->ipv4_hnapt.iblk2.port_ag = 0x1f;
418 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
419 + entry->ipv4_hnapt.iblk2.qid = 1;
420 + entry->ipv4_hnapt.iblk2.fqos = 1;
421 +#endif
422 +#ifdef CONFIG_RALINK
423 + entry->ipv4_hnapt.iblk2.dp = 1;
424 + if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1))
425 + entry->ipv4_hnapt.iblk2.qid += 8;
426 +#else
427 + entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1;
428 +#endif
429 +
430 + entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr);
431 + entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr);
432 + entry->ipv4_hnapt.sport = ntohs(tuple->src_port);
433 + entry->ipv4_hnapt.dport = ntohs(tuple->dst_port);
434 +
435 + entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr);
436 + entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr);
437 + entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port);
438 + entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port);
439 +
440 + entry->bfib1.state = BIND;
441 +
442 + if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) {
443 + entry->bfib1.psn = 1;
444 + entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES);
445 + entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid;
446 + }
447 +
448 + if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) {
449 + entry->ipv4_hnapt.vlan1 = dest->vlan_id;
450 + entry->bfib1.vlan_layer = 1;
451 +
452 + switch (dest->vlan_proto) {
453 + case htons(ETH_P_8021Q):
454 + entry->ipv4_hnapt.bfib1.vpm = 1;
455 + break;
456 + case htons(ETH_P_8021AD):
457 + entry->ipv4_hnapt.bfib1.vpm = 2;
458 + break;
459 + default:
460 + return -EINVAL;
461 + }
462 + }
463 +
464 + return 0;
465 +}
466 +
467 +static void
468 +mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac)
469 +{
470 + entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac));
471 + entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4]));
472 + entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac));
473 + entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4]));
474 +}
475 +
476 +static int
477 +mtk_check_entry_available(struct mtk_eth *eth, u32 hash)
478 +{
479 + struct mtk_foe_entry entry = ((struct mtk_foe_entry *)eth->foe_table)[hash];
480 +
481 + return (entry.bfib1.state == BIND)? 0:1;
482 +}
483 +
484 +static void
485 +mtk_foe_write(struct mtk_eth *eth, u32 hash,
486 + struct mtk_foe_entry *entry)
487 +{
488 + struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table;
489 +
490 + memcpy(&table[hash], entry, sizeof(*entry));
491 +}
492 +
493 +int mtk_flow_offload_add(struct mtk_eth *eth,
494 + enum flow_offload_type type,
495 + struct flow_offload *flow,
496 + struct flow_offload_hw_path *src,
497 + struct flow_offload_hw_path *dest)
498 +{
499 + struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple;
500 + struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple;
501 + u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff);
502 + u32 ohash, rhash;
503 + struct mtk_foe_entry orig = {
504 + .bfib1.time_stamp = time_stamp,
505 + .bfib1.psn = 0,
506 + };
507 + struct mtk_foe_entry reply = {
508 + .bfib1.time_stamp = time_stamp,
509 + .bfib1.psn = 0,
510 + };
511 +
512 + if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP)
513 + return -EINVAL;
514 +
515 + if (type == FLOW_OFFLOAD_DEL) {
516 + flow = NULL;
517 + synchronize_rcu();
518 + return 0;
519 + }
520 +
521 + switch (otuple->l3proto) {
522 + case AF_INET:
523 + if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) ||
524 + mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src))
525 + return -EINVAL;
526 +
527 + ohash = mtk_flow_hash_v4(otuple);
528 + rhash = mtk_flow_hash_v4(rtuple);
529 + break;
530 +
531 + case AF_INET6:
532 + return -EINVAL;
533 +
534 + default:
535 + return -EINVAL;
536 + }
537 +
538 + /* Two-way hash: when hash collision occurs, the hash value will be shifted to the next position. */
539 + if (!mtk_check_entry_available(eth, ohash)){
540 + if (!mtk_check_entry_available(eth, ohash + 1))
541 + return -EINVAL;
542 + ohash += 1;
543 + }
544 + if (!mtk_check_entry_available(eth, rhash)){
545 + if (!mtk_check_entry_available(eth, rhash + 1))
546 + return -EINVAL;
547 + rhash += 1;
548 + }
549 +
550 + mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest);
551 + mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest);
552 + mtk_foe_write(eth, ohash, &orig);
553 + mtk_foe_write(eth, rhash, &reply);
554 + rcu_assign_pointer(eth->foe_flow_table[ohash], flow);
555 + rcu_assign_pointer(eth->foe_flow_table[rhash], flow);
556 +
557 + return 0;
558 +}
559 +
560 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
561 +
562 +#define QDMA_TX_SCH_TX 0x1a14
563 +
564 +static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate)
565 +{
566 + int exp = 0, shift = 0;
567 + u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX);
568 + u32 val = 0;
569 +
570 + if (rate)
571 + val = BIT(11);
572 +
573 + while (rate > 127) {
574 + rate /= 10;
575 + exp++;
576 + }
577 +
578 + val |= (rate & 0x7f) << 4;
579 + val |= exp & 0xf;
580 + if (id)
581 + shift = 16;
582 + reg &= ~(0xffff << shift);
583 + reg |= val << shift;
584 + mtk_w32(eth, val, QDMA_TX_SCH_TX);
585 +}
586 +
587 +#define QTX_CFG(x) (0x1800 + (x * 0x10))
588 +#define QTX_SCH(x) (0x1804 + (x * 0x10))
589 +
590 +static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate)
591 +{
592 + int max_exp = 0, min_exp = 0;
593 + u32 reg;
594 +
595 + if (id >= 16)
596 + return;
597 +
598 + reg = mtk_r32(eth, QTX_SCH(id));
599 + reg &= 0x70000000;
600 +
601 + if (sched)
602 + reg |= BIT(31);
603 +
604 + if (min_rate)
605 + reg |= BIT(27);
606 +
607 + if (max_rate)
608 + reg |= BIT(11);
609 +
610 + while (max_rate > 127) {
611 + max_rate /= 10;
612 + max_exp++;
613 + }
614 +
615 + while (min_rate > 127) {
616 + min_rate /= 10;
617 + min_exp++;
618 + }
619 +
620 + reg |= (min_rate & 0x7f) << 20;
621 + reg |= (min_exp & 0xf) << 16;
622 + reg |= (weight & 0xf) << 12;
623 + reg |= (max_rate & 0x7f) << 4;
624 + reg |= max_exp & 0xf;
625 + mtk_w32(eth, reg, QTX_SCH(id));
626 +
627 + resv &= 0xff;
628 + reg = mtk_r32(eth, QTX_CFG(id));
629 + reg &= 0xffff0000;
630 + reg |= (resv << 8) | resv;
631 + mtk_w32(eth, reg, QTX_CFG(id));
632 +}
633 +#endif
634 +
635 +static int mtk_init_foe_table(struct mtk_eth *eth)
636 +{
637 + if (eth->foe_table)
638 + return 0;
639 +
640 + eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT,
641 + sizeof(*eth->foe_flow_table),
642 + GFP_KERNEL);
643 + if (!eth->foe_flow_table)
644 + return -EINVAL;
645 +
646 + /* map the FOE table */
647 + eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ,
648 + &eth->foe_table_phys, GFP_KERNEL);
649 + if (!eth->foe_table) {
650 + dev_err(eth->dev, "failed to allocate foe table\n");
651 + kfree(eth->foe_flow_table);
652 + return -ENOMEM;
653 + }
654 +
655 +
656 + return 0;
657 +}
658 +
659 +static int mtk_ppe_start(struct mtk_eth *eth)
660 +{
661 + u32 foe_mib_tb_sz;
662 + u32 foe_etry_num = MTK_PPE_ENTRY_CNT;
663 +
664 + int ret;
665 +
666 + ret = mtk_init_foe_table(eth);
667 + if (ret)
668 + return ret;
669 +
670 + /* tell the PPE about the tables base address */
671 + mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE);
672 +
673 + /* flush the table */
674 + memset(eth->foe_table, 0, MTK_PPE_TBL_SZ);
675 +
676 + eth->per_flow_accounting = false; //true;
677 +
678 + if (eth->per_flow_accounting) {
679 + foe_mib_tb_sz = foe_etry_num * sizeof(struct mib_entry);
680 + eth->foe_mib_cpu = dma_alloc_coherent(eth->dev, foe_mib_tb_sz,
681 + &eth->foe_mib_dev, GFP_KERNEL);
682 + if (!eth->foe_mib_cpu)
683 + return -1;
684 + mtk_w32(eth, eth->foe_mib_dev, MTK_REG_PPE_MIB_TB_BASE);
685 + memset(eth->foe_mib_cpu, 0, foe_mib_tb_sz);
686 +
687 + eth->acct =
688 + kzalloc(foe_etry_num * sizeof(struct hnat_accounting),
689 + GFP_KERNEL);
690 + if (!eth->acct)
691 + return -1;
692 + }
693 +
694 + /* setup hashing */
695 + mtk_m32(eth,
696 + MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK,
697 + MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K,
698 + MTK_REG_PPE_TB_CFG);
699 +
700 + /* set the default hashing seed */
701 + mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED);
702 +
703 + /* each foe entry is 80bytes and is setup by cpu forwarding*/
704 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK |
705 + MTK_PPE_TB_CFG_SMA_MASK,
706 + MTK_PPE_TB_CFG_ENTRY_SZ_64B | MTK_PPE_TB_CFG_SMA_FWD_CPU,
707 + MTK_REG_PPE_TB_CFG);
708 +
709 + /* set ip proto */
710 + //writel(0xFFFFFFFF, host->ppe_base + PPE_IP_PROT_CHK);
711 + mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK);
712 +
713 + /* setup caching */
714 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_X_MODE, 1);
715 + mtk_m32(eth, 1, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
716 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_X_MODE, 0);
717 + mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
718 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_EN, 1);
719 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN,
720 + MTK_REG_PPE_CAH_CTRL);
721 +
722 + /* enable FOE */
723 + /* cr_set_bits(host->ppe_base + PPE_FLOW_CFG,
724 + BIT_UDP_IP4F_NAT_EN | BIT_IPV4_NAT_EN | BIT_IPV4_NAPT_EN |
725 + BIT_IPV4_NAT_FRAG_EN | BIT_IPV4_HASH_GREK |
726 + BIT_IPV4_DSL_EN | BIT_IPV6_6RD_EN |
727 + BIT_IPV6_3T_ROUTE_EN | BIT_IPV6_5T_ROUTE_EN); */
728 + mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
729 + MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
730 + MTK_PPE_FLOW_CFG_IPV4_GREK_EN,
731 + MTK_REG_PPE_FLOW_CFG);
732 +
733 + mtk_w32(eth, 0x000a7780, MTK_REG_PPE_FLOW_CFG);
734 +
735 + /* setup flow entry un/bind aging */
736 + // cr_set_field(host->ppe_base + PPE_TB_CFG, NTU_AGE, 1);
737 + // cr_set_field(host->ppe_base + PPE_TB_CFG, UNBD_AGE, 1);
738 + // cr_set_field(host->ppe_base + PPE_TB_CFG, TCP_AGE, 1);
739 + // cr_set_field(host->ppe_base + PPE_TB_CFG, UDP_AGE, 1);
740 + // cr_set_field(host->ppe_base + PPE_TB_CFG, FIN_AGE, 1);
741 + mtk_m32(eth, 0,
742 + MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE |
743 + MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
744 + MTK_PPE_TB_CFG_TCP_AGE,
745 + MTK_REG_PPE_TB_CFG);
746 +
747 + // cr_set_field(host->ppe_base + PPE_UNB_AGE, UNB_MNP, 1000);
748 + // cr_set_field(host->ppe_base + PPE_UNB_AGE, UNB_DLTA, 3);
749 + mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK,
750 + MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA,
751 + MTK_REG_PPE_UNB_AGE);
752 +
753 + // cr_set_field(host->ppe_base + PPE_BND_AGE_0, UDP_DLTA, 12);
754 + // cr_set_field(host->ppe_base + PPE_BND_AGE_0, NTU_DLTA, 1);
755 + mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK |
756 + MTK_PPE_BND_AGE0_UDP_DLTA_MASK,
757 + MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA,
758 + MTK_REG_PPE_BND_AGE0);
759 + mtk_w32(eth, 0x0001000c, MTK_REG_PPE_BND_AGE0);
760 +
761 + // cr_set_field(host->ppe_base + PPE_BND_AGE_1, FIN_DLTA, 1);
762 + // cr_set_field(host->ppe_base + PPE_BND_AGE_1, TCP_DLTA, 7);
763 + mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK |
764 + MTK_PPE_BND_AGE1_TCP_DLTA_MASK,
765 + MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA,
766 + MTK_REG_PPE_BND_AGE1);
767 + mtk_w32(eth, 0x00010007, MTK_REG_PPE_BND_AGE1);
768 +
769 + /* setup flow entry keep alive */
770 + // cr_set_field(host->ppe_base + PPE_TB_CFG, SCAN_MODE, 2);
771 + // cr_set_field(host->ppe_base + PPE_TB_CFG, KA_CFG, 3);
772 + mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK | MTK_PPE_TB_CFG_SCAN_MODE_MASK,
773 + MTK_PPE_TB_CFG_KA | MTK_PPE_TB_CFG_SCAN_MODE,
774 + MTK_REG_PPE_TB_CFG);
775 + // cr_set_field(host->ppe_base + PPE_KA, KA_T, 1);
776 + // cr_set_field(host->ppe_base + PPE_KA, TCP_KA, 1);
777 + // cr_set_field(host->ppe_base + PPE_KA, UDP_KA, 1);
778 + mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA);
779 +
780 + /* setup flow entry rate limit */
781 + mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0);
782 + mtk_w32(eth, 0x2000000 | MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1);
783 + /* 30 packets per second */
784 + mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 0x1e, MTK_REG_PPE_BNDR);
785 +
786 + /* enable the PPE */
787 + mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG);
788 +
789 + /* set the default forwarding port to PDMA */
790 + mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT);
791 +
792 + /* disallow packets with TTL=0 */
793 + mtk_m32(eth, 0, MTK_PPE_GLO_CFG_TTL0_DROP, MTK_REG_PPE_GLO_CFG);
794 +
795 + /*enable ppe mib counter*/
796 + if (eth->per_flow_accounting) {
797 + mtk_w32(eth, 0x3, MTK_REG_PPE_MIB_CFG);
798 + mtk_w32(eth, 0x3, MTK_REG_PPE_MIB_CAH_CTRL);
799 + }
800 +
801 + /* send all traffic from gmac to the ppe */
802 + mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0));
803 + mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1));
804 +
805 + mtk_w32(eth, 0x00027fb4, MTK_REG_PPE_TB_CFG);
806 +
807 + dev_info(eth->dev, "PPE started\n");
808 +
809 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
810 + mtk_ppe_scheduler(eth, 0, 500000);
811 + mtk_ppe_scheduler(eth, 1, 500000);
812 + mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0);
813 + mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0);
814 + mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0);
815 + mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0);
816 +#endif
817 +
818 + return 0;
819 +}
820 +
821 +static int mtk_ppe_busy_wait(struct mtk_eth *eth)
822 +{
823 + unsigned long t_start = jiffies;
824 + u32 r = 0;
825 +
826 + while (1) {
827 + r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG);
828 + if (!(r & MTK_PPE_GLO_CFG_BUSY))
829 + return 0;
830 + if (time_after(jiffies, t_start + HZ))
831 + break;
832 + usleep_range(10, 20);
833 + }
834 +
835 + dev_err(eth->dev, "ppe: table busy timeout - resetting\n");
836 + reset_control_reset(eth->rst_ppe);
837 +
838 + return -ETIMEDOUT;
839 +}
840 +
841 +static int mtk_ppe_stop(struct mtk_eth *eth)
842 +{
843 + u32 r1 = 0, r2 = 0;
844 + int i;
845 +
846 + /* discard all traffic while we disable the PPE */
847 + mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0));
848 + mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1));
849 +
850 + if (mtk_ppe_busy_wait(eth))
851 + return -ETIMEDOUT;
852 +
853 + /* invalidate all flow table entries */
854 + for (i = 0; i < MTK_PPE_ENTRY_CNT; i++)
855 + eth->foe_table[i].bfib1.state = FOE_STATE_INVALID;
856 +
857 + /* disable caching */
858 + mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
859 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0,
860 + MTK_REG_PPE_CAH_CTRL);
861 +
862 + /* flush cache has to be ahead of hnat diable --*/
863 + mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG);
864 +
865 + /* disable FOE */
866 + mtk_m32(eth,
867 + MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
868 + MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
869 + MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE,
870 + 0, MTK_REG_PPE_FLOW_CFG);
871 +
872 + /* disable FOE aging */
873 + mtk_m32(eth, 0,
874 + MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
875 + MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE |
876 + MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG);
877 +
878 + r1 = mtk_r32(eth, 0x100);
879 + r2 = mtk_r32(eth, 0x10c);
880 +
881 + dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2);
882 +
883 + if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) ||
884 + ((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) {
885 + dev_info(eth->dev, "reset pse\n");
886 + mtk_w32(eth, 0x1, 0x4);
887 + }
888 +
889 + /* set the foe entry base address to 0 */
890 + mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE);
891 +
892 + if (mtk_ppe_busy_wait(eth))
893 + return -ETIMEDOUT;
894 +
895 + /* send all traffic back to the DMA engine */
896 + mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0));
897 + mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1));
898 + return 0;
899 +}
900 +
901 +static void mtk_offload_keepalive(struct mtk_eth *eth, unsigned int hash)
902 +{
903 + struct flow_offload *flow;
904 +
905 + rcu_read_lock();
906 + flow = rcu_dereference(eth->foe_flow_table[hash]);
907 + if (flow)
908 + flow->timeout = jiffies + 30 * HZ;
909 + rcu_read_unlock();
910 +}
911 +
912 +int mtk_offload_check_rx(struct mtk_eth *eth, struct sk_buff *skb, u32 rxd4)
913 +{
914 + unsigned int hash;
915 +
916 + switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) {
917 + case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR:
918 + case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR:
919 + case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR:
920 + hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4);
921 + mtk_offload_keepalive(eth, hash);
922 + return -1;
923 + case MTK_CPU_REASON_PACKET_SAMPLING:
924 + return -1;
925 + default:
926 + return 0;
927 + }
928 +}
929 +
930 +int mtk_ppe_probe(struct mtk_eth *eth)
931 +{
932 + int err;
933 +
934 + err = mtk_ppe_start(eth);
935 + if (err)
936 + return err;
937 +
938 + err = mtk_ppe_debugfs_init(eth);
939 + if (err)
940 + return err;
941 +
942 + return 0;
943 +}
944 +
945 +void mtk_ppe_remove(struct mtk_eth *eth)
946 +{
947 + mtk_ppe_stop(eth);
948 +}
949 Index: linux-5.4.28/drivers/net/ethernet/mediatek/mtk_offload.h
950 ===================================================================
951 --- /dev/null
952 +++ linux-5.4.28/drivers/net/ethernet/mediatek/mtk_offload.h
953 @@ -0,0 +1,298 @@
954 +/* This program is free software; you can redistribute it and/or modify
955 + * it under the terms of the GNU General Public License as published by
956 + * the Free Software Foundation; version 2 of the License
957 + *
958 + * This program is distributed in the hope that it will be useful,
959 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
960 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
961 + * GNU General Public License for more details.
962 + *
963 + * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
964 + * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
965 + */
966 +
967 +#include <linux/dma-mapping.h>
968 +#include <linux/delay.h>
969 +#include <linux/if.h>
970 +#include <linux/io.h>
971 +#include <linux/module.h>
972 +#include <linux/of_device.h>
973 +#include <linux/platform_device.h>
974 +#include <linux/reset.h>
975 +#include <linux/netfilter.h>
976 +#include <linux/netdevice.h>
977 +#include <net/netfilter/nf_flow_table.h>
978 +#include <linux/debugfs.h>
979 +#include <linux/etherdevice.h>
980 +#include <linux/bitfield.h>
981 +
982 +#include "mtk_eth_soc.h"
983 +
984 +#ifdef CONFIG_RALINK
985 +/* ramips compat */
986 +#define mtk_eth fe_priv
987 +#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
988 +#define mtk_m32 fe_m32
989 +
990 +static inline u32
991 +mtk_r32(struct mtk_eth *eth, u32 reg)
992 +{
993 + return fe_r32(reg);
994 +}
995 +
996 +static inline void
997 +mtk_w32(struct mtk_eth *eth, u32 val, u32 reg)
998 +{
999 + fe_w32(val, reg);
1000 +}
1001 +#endif
1002 +
1003 +#define MTK_REG_PPE_GLO_CFG 0xe00
1004 +#define MTK_PPE_GLO_CFG_BUSY BIT(31)
1005 +#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
1006 +#define MTK_PPE_GLO_CFG_EN BIT(0)
1007 +
1008 +#define MTK_REG_PPE_FLOW_CFG 0xe04
1009 +#define MTK_PPE_FLOW_CFG_IPV4_GREK_EN BIT(19)
1010 +#define MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN BIT(17)
1011 +#define MTK_PPE_FLOW_CFG_IPV4_NAPT_EN BIT(13)
1012 +#define MTK_PPE_FLOW_CFG_IPV4_NAT_EN BIT(12)
1013 +#define MTK_PPE_FLOW_CFG_FUC_FOE BIT(2)
1014 +#define MTK_PPE_FLOW_CFG_FMC_FOE BIT(1)
1015 +
1016 +#define MTK_REG_PPE_IP_PROT_CHK 0xe08
1017 +
1018 +#define MTK_REG_PPE_TB_BASE 0xe20
1019 +
1020 +#define MTK_REG_PPE_BNDR 0xe28
1021 +#define MTK_PPE_BNDR_RATE_MASK 0xffff
1022 +
1023 +#define MTK_REG_PPE_BIND_LMT_0 0xe2C
1024 +
1025 +#define MTK_REG_PPE_BIND_LMT_1 0xe30
1026 +#define MTK_PPE_NTU_KA BIT(16)
1027 +
1028 +#define MTK_REG_PPE_KA 0xe34
1029 +#define MTK_PPE_KA_T BIT(0)
1030 +#define MTK_PPE_KA_TCP BIT(16)
1031 +#define MTK_PPE_KA_UDP BIT(24)
1032 +
1033 +#define MTK_REG_PPE_UNB_AGE 0xe38
1034 +#define MTK_PPE_UNB_AGE_MNP_MASK (0xffff << 16)
1035 +#define MTK_PPE_UNB_AGE_MNP (1000 << 16)
1036 +#define MTK_PPE_UNB_AGE_DLTA_MASK 0xff
1037 +#define MTK_PPE_UNB_AGE_DLTA 3
1038 +
1039 +#define MTK_REG_PPE_BND_AGE0 0xe3c
1040 +#define MTK_PPE_BND_AGE0_NTU_DLTA_MASK (0xffff << 16)
1041 +#define MTK_PPE_BND_AGE0_NTU_DLTA (5 << 16)
1042 +#define MTK_PPE_BND_AGE0_UDP_DLTA_MASK 0xffff
1043 +#define MTK_PPE_BND_AGE0_UDP_DLTA 5
1044 +
1045 +#define MTK_REG_PPE_BND_AGE1 0xe40
1046 +#define MTK_PPE_BND_AGE1_FIN_DLTA_MASK (0xffff << 16)
1047 +#define MTK_PPE_BND_AGE1_FIN_DLTA (5 << 16)
1048 +#define MTK_PPE_BND_AGE1_TCP_DLTA_MASK 0xffff
1049 +#define MTK_PPE_BND_AGE1_TCP_DLTA 5
1050 +
1051 +#define MTK_REG_PPE_DFT_CPORT 0xe48
1052 +
1053 +#define MTK_REG_PPE_TB_CFG 0xe1c
1054 +#define MTK_PPE_TB_CFG_X_MODE_MASK (3 << 18)
1055 +#define MTK_PPE_TB_CFG_HASH_MODE1 BIT(14)
1056 +#define MTK_PPE_TB_CFG_HASH_MODE_MASK (0x3 << 14)
1057 +#define MTK_PPE_TB_CFG_KA (3 << 12)
1058 +#define MTK_PPE_TB_CFG_KA_MASK (0x3 << 12)
1059 +#define MTK_PPE_TB_CFG_SCAN_MODE (2 << 16)
1060 +#define MTK_PPE_TB_CFG_SCAN_MODE_MASK (0x3 << 16)
1061 +#define MTK_PPE_TB_CFG_FIN_AGE BIT(11)
1062 +#define MTK_PPE_TB_CFG_UDP_AGE BIT(10)
1063 +#define MTK_PPE_TB_CFG_TCP_AGE BIT(9)
1064 +#define MTK_PPE_TB_CFG_UNBD_AGE BIT(8)
1065 +#define MTK_PPE_TB_CFG_NTU_AGE BIT(7)
1066 +#define MTK_PPE_TB_CFG_SMA_FWD_CPU (0x3 << 4)
1067 +#define MTK_PPE_TB_CFG_SMA_MASK (0x3 << 4)
1068 +#define MTK_PPE_TB_CFG_ENTRY_SZ_64B 0
1069 +#define MTK_PPE_TB_CFG_ENTRY_SZ_80B 1
1070 +#define MTK_PPE_TB_CFG_ENTRY_SZ_MASK BIT(3)
1071 +#define MTK_PPE_TB_CFG_TBL_SZ_4K 4
1072 +#define MTK_PPE_TB_CFG_TBL_SZ_MASK 0x7
1073 +
1074 +#define MTK_REG_PPE_HASH_SEED 0xe44
1075 +#define MTK_PPE_HASH_SEED 0x12345678
1076 +
1077 +
1078 +#define MTK_REG_PPE_CAH_CTRL 0xf20
1079 +#define MTK_PPE_CAH_CTRL_X_MODE BIT(9)
1080 +#define MTK_PPE_CAH_CTRL_EN BIT(0)
1081 +
1082 +#define MTK_REG_PPE_MIB_CFG 0xf34
1083 +#define MTK_REG_PPE_MIB_TB_BASE 0xf38
1084 +#define MTK_REG_PPE_MIB_CAH_CTRL 0Xf50
1085 +
1086 +
1087 +struct mtk_foe_unbind_info_blk {
1088 + u32 time_stamp:8;
1089 + u32 pcnt:16; /* packet count */
1090 + u32 preb:1;
1091 + u32 pkt_type:3;
1092 + u32 state:2;
1093 + u32 udp:1;
1094 + u32 sta:1; /* static entry */
1095 +} __attribute__ ((packed));
1096 +
1097 +struct mtk_foe_bind_info_blk {
1098 + u32 time_stamp:15;
1099 + u32 ka:1; /* keep alive */
1100 + u32 vlan_layer:3;
1101 + u32 psn:1; /* egress packet has PPPoE session */
1102 +#ifdef CONFIG_RALINK
1103 + u32 vpm:2; /* 0:ethertype remark, 1:0x8100(CR default) */
1104 +#else
1105 + u32 vpm:1; /* 0:ethertype remark, 1:0x8100(CR default) */
1106 + u32 ps:1; /* packet sampling */
1107 +#endif
1108 + u32 cah:1; /* cacheable flag */
1109 + u32 rmt:1; /* remove tunnel ip header (6rd/dslite only) */
1110 + u32 ttl:1;
1111 + u32 pkt_type:3;
1112 + u32 state:2;
1113 + u32 udp:1;
1114 + u32 sta:1; /* static entry */
1115 +} __attribute__ ((packed));
1116 +
1117 +struct mtk_foe_info_blk2 {
1118 + u32 qid:4; /* QID in Qos Port */
1119 + u32 fqos:1; /* force to PSE QoS port */
1120 + u32 dp:3; /* force to PSE port x
1121 + 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */
1122 + u32 mcast:1; /* multicast this packet to CPU */
1123 + u32 pcpl:1; /* OSBN */
1124 + u32 mlen:1; /* 0:post 1:pre packet length in meter */
1125 + u32 alen:1; /* 0:post 1:pre packet length in accounting */
1126 + u32 port_mg:6; /* port meter group */
1127 + u32 port_ag:6; /* port account group */
1128 + u32 dscp:8; /* DSCP value */
1129 +} __attribute__ ((packed));
1130 +
1131 +/* info blk2 for WHNAT */
1132 +struct hnat_info_blk2_whnat {
1133 + u32 qid : 4; /* QID[3:0] in Qos Port */
1134 + u32 fqos : 1; /* force to PSE QoS port */
1135 + u32 dp : 3; /* force to PSE port x
1136 + * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
1137 + */
1138 + u32 mcast : 1; /* multicast this packet to CPU */
1139 + u32 pcpl : 1; /* OSBN */
1140 + u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
1141 + u32 alen : 1; /* 0:post 1:pre packet length in accounting */
1142 + u32 qid2 : 2; /* QID[5:4] in Qos Port */
1143 + u32 resv : 2;
1144 + u32 wdmaid : 1; /* 0:to pcie0 dev 1:to pcie1 dev */
1145 + u32 winfoi : 1; /* 0:off 1:on Wi-Fi hwnat support */
1146 + u32 port_ag : 6; /* port account group */
1147 + u32 dscp : 8; /* DSCP value */
1148 +} __attribute__ ((packed));
1149 +
1150 +struct hnat_winfo {
1151 + u32 bssid : 6; /* WiFi Bssidx */
1152 + u32 wcid : 8; /* WiFi wtable Idx */
1153 + u32 rxid : 2; /* WiFi Ring idx */
1154 +} __attribute__ ((packed));
1155 +
1156 +struct mtk_foe_ipv4_hnapt {
1157 + union {
1158 + struct mtk_foe_bind_info_blk bfib1;
1159 + struct mtk_foe_unbind_info_blk udib1;
1160 + u32 info_blk1;
1161 + };
1162 + u32 sip;
1163 + u32 dip;
1164 + u16 dport;
1165 + u16 sport;
1166 + union {
1167 + struct mtk_foe_info_blk2 iblk2;
1168 + struct hnat_info_blk2_whnat iblk2w;
1169 + u32 info_blk2;
1170 + };
1171 + u32 new_sip;
1172 + u32 new_dip;
1173 + u16 new_dport;
1174 + u16 new_sport;
1175 + u32 resv1;
1176 + u32 resv2;
1177 + u32 resv3:26;
1178 + u32 act_dp:6; /* UDF */
1179 + u16 vlan1;
1180 + u16 etype;
1181 + u32 dmac_hi;
1182 + union {
1183 + struct hnat_winfo winfo;
1184 + u16 vlan2;
1185 + };
1186 + u16 dmac_lo;
1187 + u32 smac_hi;
1188 + u16 pppoe_id;
1189 + u16 smac_lo;
1190 +} __attribute__ ((packed));
1191 +
1192 +struct mtk_foe_entry {
1193 + union {
1194 + struct mtk_foe_unbind_info_blk udib1;
1195 + struct mtk_foe_bind_info_blk bfib1;
1196 + struct mtk_foe_ipv4_hnapt ipv4_hnapt;
1197 + };
1198 +};
1199 +
1200 +enum mtk_foe_entry_state {
1201 + FOE_STATE_INVALID = 0,
1202 + FOE_STATE_UNBIND = 1,
1203 + FOE_STATE_BIND = 2,
1204 + FOE_STATE_FIN = 3
1205 +};
1206 +
1207 +
1208 +#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
1209 +#define MTK_RXD4_CPU_REASON GENMASK(18, 14)
1210 +#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
1211 +#define MTK_RXD4_ALG GENMASK(31, 22)
1212 +
1213 +enum mtk_foe_cpu_reason {
1214 + MTK_CPU_REASON_TTL_EXCEEDED = 0x02,
1215 + MTK_CPU_REASON_OPTION_HEADER = 0x03,
1216 + MTK_CPU_REASON_NO_FLOW = 0x07,
1217 + MTK_CPU_REASON_IPV4_FRAG = 0x08,
1218 + MTK_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
1219 + MTK_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
1220 + MTK_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
1221 + MTK_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
1222 + MTK_CPU_REASON_UN_HIT = 0x0d,
1223 + MTK_CPU_REASON_HIT_UNBIND = 0x0e,
1224 + MTK_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
1225 + MTK_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
1226 + MTK_CPU_REASON_HIT_TTL_1 = 0x11,
1227 + MTK_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
1228 + MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
1229 + MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
1230 + MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
1231 + MTK_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
1232 + MTK_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
1233 + MTK_CPU_REASON_MULTICAST_TO_CPU = 0x18,
1234 + MTK_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
1235 + MTK_CPU_REASON_HIT_PRE_BIND = 0x1a,
1236 + MTK_CPU_REASON_PACKET_SAMPLING = 0x1b,
1237 + MTK_CPU_REASON_EXCEED_MTU = 0x1c,
1238 + MTK_CPU_REASON_PPE_BYPASS = 0x1e,
1239 + MTK_CPU_REASON_INVALID = 0x1f,
1240 +};
1241 +
1242 +
1243 +/* our table size is 4K */
1244 +#define MTK_PPE_ENTRY_CNT 0x4000
1245 +#define MTK_PPE_TBL_SZ \
1246 + (MTK_PPE_ENTRY_CNT * sizeof(struct mtk_foe_entry))
1247 +
1248 +int mtk_ppe_debugfs_init(struct mtk_eth *eth);
1249 +
1250 +
1251 +
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