mediatek: backport latest pci/e driver from upstream
[openwrt/staging/jow.git] / target / linux / mediatek / patches-5.4 / 0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
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71 From: <chuanjia.liu@mediatek.com>
72 To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
73 Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for
74 MT2712/MT7622
75 Date: Thu, 28 May 2020 14:16:47 +0800
76 Message-ID: <20200528061648.32078-4-chuanjia.liu@mediatek.com>
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116 Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
117 srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
118 linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
119 jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
120 yong.wu@mediatek.com, bhelgaas@google.com,
121 linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk
122 Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
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124 linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
125
126 From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
127
128 There are two independent PCIe controllers in MT2712/MT7622 platform,
129 and each of them should contain an independent MSI domain.
130
131 In current architecture, MSI domain will be inherited from the root
132 bridge, and all of the devices will share the same MSI domain.
133 Hence that, the PCIe devices will not work properly if the irq number
134 which required is more than 32.
135
136 Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
137 comply with the hardware design.
138
139 Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
140 ---
141 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++++++++--------
142 .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 ++--
143 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +-
144 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 +++++++++++------
145 4 files changed, 96 insertions(+), 69 deletions(-)
146
147 diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
148 index 2cd8b33886e5..ab27ff4a869e 100644
149 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
150 +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
151 @@ -797,60 +797,73 @@
152 };
153 };
154
155 - pcie: pcie@11700000 {
156 + pcie1: pcie@112ff000 {
157 compatible = "mediatek,mt2712-pcie";
158 device_type = "pci";
159 - reg = <0 0x11700000 0 0x1000>,
160 - <0 0x112ff000 0 0x1000>;
161 - reg-names = "port0", "port1";
162 + reg = <0 0x112ff000 0 0x1000>;
163 + reg-names = "port1";
164 #address-cells = <3>;
165 #size-cells = <2>;
166 - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
167 - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
168 - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
169 - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
170 - <&pericfg CLK_PERI_PCIE0>,
171 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
172 + interrupt-names = "pcie_irq";
173 + clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
174 <&pericfg CLK_PERI_PCIE1>;
175 - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
176 - phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
177 - phy-names = "pcie-phy0", "pcie-phy1";
178 + clock-names = "sys_ck1", "ahb_ck1";
179 + phys = <&u3port1 PHY_TYPE_PCIE>;
180 + phy-names = "pcie-phy1";
181 bus-range = <0x00 0xff>;
182 - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
183 + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
184 + status = "disabled";
185
186 - pcie0: pcie@0,0 {
187 - device_type = "pci";
188 - status = "disabled";
189 - reg = <0x0000 0 0 0 0>;
190 + slot1: pcie@1,0 {
191 + reg = <0x0800 0 0 0 0>;
192 #address-cells = <3>;
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 ranges;
196 interrupt-map-mask = <0 0 0 7>;
197 - interrupt-map = <0 0 0 1 &pcie_intc0 0>,
198 - <0 0 0 2 &pcie_intc0 1>,
199 - <0 0 0 3 &pcie_intc0 2>,
200 - <0 0 0 4 &pcie_intc0 3>;
201 - pcie_intc0: interrupt-controller {
202 + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
203 + <0 0 0 2 &pcie_intc1 1>,
204 + <0 0 0 3 &pcie_intc1 2>,
205 + <0 0 0 4 &pcie_intc1 3>;
206 + pcie_intc1: interrupt-controller {
207 interrupt-controller;
208 #address-cells = <0>;
209 #interrupt-cells = <1>;
210 };
211 };
212 + };
213
214 - pcie1: pcie@1,0 {
215 - device_type = "pci";
216 - status = "disabled";
217 - reg = <0x0800 0 0 0 0>;
218 + pcie0: pcie@11700000 {
219 + compatible = "mediatek,mt2712-pcie";
220 + device_type = "pci";
221 + reg = <0 0x11700000 0 0x1000>;
222 + reg-names = "port0";
223 + #address-cells = <3>;
224 + #size-cells = <2>;
225 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
226 + interrupt-names = "pcie_irq";
227 + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
228 + <&pericfg CLK_PERI_PCIE0>;
229 + clock-names = "sys_ck0", "ahb_ck0";
230 + phys = <&u3port0 PHY_TYPE_PCIE>;
231 + phy-names = "pcie-phy0";
232 + bus-range = <0x00 0xff>;
233 + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
234 + status = "disabled";
235 +
236 + slot0: pcie@0,0 {
237 + reg = <0x0000 0 0 0 0>;
238 #address-cells = <3>;
239 #size-cells = <2>;
240 #interrupt-cells = <1>;
241 ranges;
242 interrupt-map-mask = <0 0 0 7>;
243 - interrupt-map = <0 0 0 1 &pcie_intc1 0>,
244 - <0 0 0 2 &pcie_intc1 1>,
245 - <0 0 0 3 &pcie_intc1 2>,
246 - <0 0 0 4 &pcie_intc1 3>;
247 - pcie_intc1: interrupt-controller {
248 + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
249 + <0 0 0 2 &pcie_intc0 1>,
250 + <0 0 0 3 &pcie_intc0 2>,
251 + <0 0 0 4 &pcie_intc0 3>;
252 + pcie_intc0: interrupt-controller {
253 interrupt-controller;
254 #address-cells = <0>;
255 #interrupt-cells = <1>;
256 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
257 index 83e10591e0e5..7574d88cc46a 100644
258 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
259 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
260 @@ -207,18 +207,16 @@
261 };
262 };
263
264 -&pcie {
265 +&pcie0 {
266 pinctrl-names = "default";
267 - pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
268 + pinctrl-0 = <&pcie0_pins>;
269 status = "okay";
270 +};
271
272 - pcie@0,0 {
273 - status = "okay";
274 - };
275 -
276 - pcie@1,0 {
277 - status = "okay";
278 - };
279 +&pcie1 {
280 + pinctrl-names = "default";
281 + pinctrl-0 = <&pcie1_pins>;
282 + status = "okay";
283 };
284
285 &pio {
286 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
287 index 339dc9f88f43..d5131c8b6a79 100644
288 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
289 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
290 @@ -766,45 +766,41 @@
291 #reset-cells = <1>;
292 };
293
294 - pcie: pcie@1a140000 {
295 + pciecfg: pciecfg@1a140000 {
296 + compatible = "mediatek,mt7622-pciecfg", "syscon";
297 + reg = <0 0x1a140000 0 0x1000>;
298 + };
299 +
300 + pcie0: pcie@1a143000 {
301 compatible = "mediatek,mt7622-pcie";
302 device_type = "pci";
303 - reg = <0 0x1a140000 0 0x1000>,
304 - <0 0x1a143000 0 0x1000>,
305 - <0 0x1a145000 0 0x1000>;
306 - reg-names = "subsys", "port0", "port1";
307 + reg = <0 0x1a143000 0 0x1000>;
308 + reg-names = "port0";
309 + mediatek,pcie-cfg = <&pciecfg>;
310 #address-cells = <3>;
311 #size-cells = <2>;
312 - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
313 - <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
314 + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
315 + interrupt-names = "pcie_irq";
316 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
317 - <&pciesys CLK_PCIE_P1_MAC_EN>,
318 - <&pciesys CLK_PCIE_P0_AHB_EN>,
319 <&pciesys CLK_PCIE_P0_AHB_EN>,
320 <&pciesys CLK_PCIE_P0_AUX_EN>,
321 - <&pciesys CLK_PCIE_P1_AUX_EN>,
322 <&pciesys CLK_PCIE_P0_AXI_EN>,
323 - <&pciesys CLK_PCIE_P1_AXI_EN>,
324 <&pciesys CLK_PCIE_P0_OBFF_EN>,
325 - <&pciesys CLK_PCIE_P1_OBFF_EN>,
326 - <&pciesys CLK_PCIE_P0_PIPE_EN>,
327 - <&pciesys CLK_PCIE_P1_PIPE_EN>;
328 - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
329 - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
330 - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
331 + <&pciesys CLK_PCIE_P0_PIPE_EN>;
332 + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
333 + "axi_ck0", "obff_ck0", "pipe_ck0";
334 +
335 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
336 bus-range = <0x00 0xff>;
337 - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
338 + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
339 status = "disabled";
340
341 - pcie0: pcie@0,0 {
342 + slot0: pcie@0,0 {
343 reg = <0x0000 0 0 0 0>;
344 #address-cells = <3>;
345 #size-cells = <2>;
346 #interrupt-cells = <1>;
347 ranges;
348 - status = "disabled";
349 -
350 interrupt-map-mask = <0 0 0 7>;
351 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
352 <0 0 0 2 &pcie_intc0 1>,
353 @@ -816,15 +812,39 @@
354 #interrupt-cells = <1>;
355 };
356 };
357 + };
358
359 - pcie1: pcie@1,0 {
360 + pcie1: pcie@1a145000 {
361 + compatible = "mediatek,mt7622-pcie";
362 + device_type = "pci";
363 + reg = <0 0x1a145000 0 0x1000>;
364 + reg-names = "port1";
365 + mediatek,pcie-cfg = <&pciecfg>;
366 + #address-cells = <3>;
367 + #size-cells = <2>;
368 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
369 + interrupt-names = "pcie_irq";
370 + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
371 + /* designer has connect RC1 with p0_ahb clock */
372 + <&pciesys CLK_PCIE_P0_AHB_EN>,
373 + <&pciesys CLK_PCIE_P1_AUX_EN>,
374 + <&pciesys CLK_PCIE_P1_AXI_EN>,
375 + <&pciesys CLK_PCIE_P1_OBFF_EN>,
376 + <&pciesys CLK_PCIE_P1_PIPE_EN>;
377 + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
378 + "axi_ck1", "obff_ck1", "pipe_ck1";
379 +
380 + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
381 + bus-range = <0x00 0xff>;
382 + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
383 + status = "disabled";
384 +
385 + slot1: pcie@1,0 {
386 reg = <0x0800 0 0 0 0>;
387 #address-cells = <3>;
388 #size-cells = <2>;
389 #interrupt-cells = <1>;
390 ranges;
391 - status = "disabled";
392 -
393 interrupt-map-mask = <0 0 0 7>;
394 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
395 <0 0 0 2 &pcie_intc1 1>,
396 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-06-15 18:52:25.092948824 +0800
397 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-06-15 18:52:15.909094229 +0800
398 @@ -244,18 +244,16 @@
399 };
400 };
401
402 -&pcie {
403 +&pcie0 {
404 pinctrl-names = "default";
405 - pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
406 + pinctrl-0 = <&pcie0_pins>;
407 status = "okay";
408 +};
409
410 - pcie@0,0 {
411 - status = "okay";
412 - };
413 -
414 - pcie@1,0 {
415 - status = "okay";
416 - };
417 +&pcie1 {
418 + pinctrl-names = "default";
419 + pinctrl-0 = <&pcie1_pins>;
420 + status = "okay";
421 };
422
423 &pio {