target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch

   1 From 94c7f8af2c0a399c8aa66f2522b60c5784b5be6c Mon Sep 17 00:00:00 2001
   2 From: Kewei Xu <kewei.xu@mediatek.com>
   3 Date: Sat, 6 Aug 2022 18:02:49 +0800
   4 Subject: [PATCH 10/16] i2c: mediatek: add i2c compatible for MT8188
   5
   6 Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since
   7 MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94.
   8
   9 Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
  10 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  11 Reviewed-by: Qii Wang <qii.wang@mediatek.com>
  12 Signed-off-by: Wolfram Sang <wsa@kernel.org>
  13 ---
  14  drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++
  15  1 file changed, 43 insertions(+)
  16
  17 --- a/drivers/i2c/busses/i2c-mt65xx.c
  18 +++ b/drivers/i2c/busses/i2c-mt65xx.c
  19 @@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = {
  20         [OFFSET_DCM_EN] = 0xf88,
  21  };
  22
  23 +static const u16 mt_i2c_regs_v3[] = {
  24 +       [OFFSET_DATA_PORT] = 0x0,
  25 +       [OFFSET_INTR_MASK] = 0x8,
  26 +       [OFFSET_INTR_STAT] = 0xc,
  27 +       [OFFSET_CONTROL] = 0x10,
  28 +       [OFFSET_TRANSFER_LEN] = 0x14,
  29 +       [OFFSET_TRANSAC_LEN] = 0x18,
  30 +       [OFFSET_DELAY_LEN] = 0x1c,
  31 +       [OFFSET_TIMING] = 0x20,
  32 +       [OFFSET_START] = 0x24,
  33 +       [OFFSET_EXT_CONF] = 0x28,
  34 +       [OFFSET_LTIMING] = 0x2c,
  35 +       [OFFSET_HS] = 0x30,
  36 +       [OFFSET_IO_CONFIG] = 0x34,
  37 +       [OFFSET_FIFO_ADDR_CLR] = 0x38,
  38 +       [OFFSET_SDA_TIMING] = 0x3c,
  39 +       [OFFSET_TRANSFER_LEN_AUX] = 0x44,
  40 +       [OFFSET_CLOCK_DIV] = 0x48,
  41 +       [OFFSET_SOFTRESET] = 0x50,
  42 +       [OFFSET_MULTI_DMA] = 0x8c,
  43 +       [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
  44 +       [OFFSET_SLAVE_ADDR] = 0x94,
  45 +       [OFFSET_DEBUGSTAT] = 0xe4,
  46 +       [OFFSET_DEBUGCTRL] = 0xe8,
  47 +       [OFFSET_FIFO_STAT] = 0xf4,
  48 +       [OFFSET_FIFO_THRESH] = 0xf8,
  49 +       [OFFSET_DCM_EN] = 0xf88,
  50 +};
  51 +
  52  struct mtk_i2c_compatible {
  53         const struct i2c_adapter_quirks *quirks;
  54         const u16 *regs;
  55 @@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible m
  56         .max_dma_support = 36,
  57  };
  58
  59 +static const struct mtk_i2c_compatible mt8188_compat = {
  60 +       .regs = mt_i2c_regs_v3,
  61 +       .pmic_i2c = 0,
  62 +       .dcm = 0,
  63 +       .auto_restart = 1,
  64 +       .aux_len_reg = 1,
  65 +       .timing_adjust = 1,
  66 +       .dma_sync = 0,
  67 +       .ltiming_adjust = 1,
  68 +       .apdma_sync = 1,
  69 +       .max_dma_support = 36,
  70 +};
  71 +
  72  static const struct mtk_i2c_compatible mt8192_compat = {
  73         .quirks = &mt8183_i2c_quirks,
  74         .regs = mt_i2c_regs_v2,
  75 @@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c
  76         { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
  77         { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
  78         { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
  79 +       { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
  80         { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
  81         {}
  82  };