target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch

   1 From 5b8e29e566e086ef9b5b9ea0d054370a295e1d05 Mon Sep 17 00:00:00 2001
   2 From: Kewei Xu <kewei.xu@mediatek.com>
   3 Date: Sun, 10 Oct 2021 15:05:13 +0800
   4 Subject: [PATCH 02/16] i2c: mediatek: Dump i2c/dma register when a timeout
   5  occurs
   6
   7 When a timeout error occurs in i2c transter, it is usually related
   8 to the i2c/dma IP hardware configuration. Therefore, the purpose of
   9 this patch is to dump the key register values of i2c/dma when a
  10 timeout occurs in i2c for debugging.
  11
  12 Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
  13 Reviewed-by: Qii Wang <qii.wang@mediatek.com>
  14 Signed-off-by: Wolfram Sang <wsa@kernel.org>
  15 ---
  16  drivers/i2c/busses/i2c-mt65xx.c | 54 +++++++++++++++++++++++++++++++++
  17  1 file changed, 54 insertions(+)
  18
  19 --- a/drivers/i2c/busses/i2c-mt65xx.c
  20 +++ b/drivers/i2c/busses/i2c-mt65xx.c
  21 @@ -130,6 +130,7 @@ enum I2C_REGS_OFFSET {
  22         OFFSET_HS,
  23         OFFSET_SOFTRESET,
  24         OFFSET_DCM_EN,
  25 +       OFFSET_MULTI_DMA,
  26         OFFSET_PATH_DIR,
  27         OFFSET_DEBUGSTAT,
  28         OFFSET_DEBUGCTRL,
  29 @@ -197,6 +198,7 @@ static const u16 mt_i2c_regs_v2[] = {
  30         [OFFSET_TRANSFER_LEN_AUX] = 0x44,
  31         [OFFSET_CLOCK_DIV] = 0x48,
  32         [OFFSET_SOFTRESET] = 0x50,
  33 +       [OFFSET_MULTI_DMA] = 0x8c,
  34         [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
  35         [OFFSET_DEBUGSTAT] = 0xe4,
  36         [OFFSET_DEBUGCTRL] = 0xe8,
  37 @@ -845,6 +847,57 @@ static int mtk_i2c_set_speed(struct mtk_
  38         return 0;
  39  }
  40
  41 +static void i2c_dump_register(struct mtk_i2c *i2c)
  42 +{
  43 +       dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
  44 +               mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
  45 +               mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
  46 +       dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
  47 +               mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
  48 +               mtk_i2c_readw(i2c, OFFSET_CONTROL));
  49 +       dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
  50 +               mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
  51 +               mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
  52 +       dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
  53 +               mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
  54 +               mtk_i2c_readw(i2c, OFFSET_TIMING));
  55 +       dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
  56 +               mtk_i2c_readw(i2c, OFFSET_START),
  57 +               mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
  58 +       dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
  59 +               mtk_i2c_readw(i2c, OFFSET_HS),
  60 +               mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
  61 +       dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
  62 +               mtk_i2c_readw(i2c, OFFSET_DCM_EN),
  63 +               mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
  64 +       dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
  65 +               mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
  66 +               mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
  67 +       dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
  68 +               mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
  69 +               mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
  70 +       if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
  71 +               dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
  72 +                       mtk_i2c_readw(i2c, OFFSET_LTIMING),
  73 +                       mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
  74 +       }
  75 +       dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
  76 +               readl(i2c->pdmabase + OFFSET_INT_FLAG),
  77 +               readl(i2c->pdmabase + OFFSET_INT_EN));
  78 +       dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
  79 +               readl(i2c->pdmabase + OFFSET_EN),
  80 +               readl(i2c->pdmabase + OFFSET_CON));
  81 +       dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
  82 +               readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
  83 +               readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
  84 +       dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
  85 +               readl(i2c->pdmabase + OFFSET_TX_LEN),
  86 +               readl(i2c->pdmabase + OFFSET_RX_LEN));
  87 +       dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
  88 +               readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
  89 +               readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
  90 +}
  91 +
  92  static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
  93                                int num, int left_num)
  94  {
  95 @@ -1075,6 +1128,7 @@ static int mtk_i2c_do_transfer(struct mt
  96
  97         if (ret == 0) {
  98                 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
  99 +               i2c_dump_register(i2c);
 100                 mtk_i2c_init_hw(i2c);
 101                 return -ETIMEDOUT;
 102         }