projects / openwrt / staging / jow.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
mediatek: update the mt7531 switch driver
[openwrt/staging/jow.git] / target / linux / mediatek / patches-4.19 / 0003-mt7531-gsw-internal_phy_calibration.patch
1 --- a/drivers/net/phy/mtk/mt753x/Makefile
2 +++ b/drivers/net/phy/mtk/mt753x/Makefile
3 @@ -5,6 +5,6 @@
4 obj-$(CONFIG_MT753X_GSW) += mt753x.o
5
6 mt753x-y += mt753x_mdio.o mt7530.o mt7531.o \
7 - mt753x_common.o mt753x_nl.o
8 + mt753x_common.o mt753x_nl.o mt753x_phy.o
9
10
11 --- a/drivers/net/phy/mtk/mt753x/mt7531.c
12 +++ b/drivers/net/phy/mtk/mt753x/mt7531.c
13 @@ -454,6 +454,18 @@ static void mt7531_core_pll_setup(struct gsw_mt753x *gsw)
14
15 static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw)
16 {
17 + u32 i, val;
18 + int ret;
19 + val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);
20 + val |= GBE_EFUSE_SETTING;
21 + gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);
22 + for (i = 0; i < 5; i++) {
23 + ret = mt753x_phy_calibration(gsw, i);
24 + /* set Auto-negotiation with giga extension. */
25 + gsw->mii_write(gsw, i, 0, 0x1340);
26 + if (ret)
27 + return ret;
28 + }
29 return 0;
30 }
31
32 --- a/drivers/net/phy/mtk/mt753x/mt753x.h
33 +++ b/drivers/net/phy/mtk/mt753x/mt753x.h
34 @@ -141,6 +141,8 @@ void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
35 void mt753x_irq_worker(struct work_struct *work);
36 void mt753x_irq_enable(struct gsw_mt753x *gsw);
37
38 +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr);
39 +
40 /* MDIO Indirect Access Registers */
41 #define MII_MMD_ACC_CTL_REG 0x0d
42 #define MMD_CMD_S 14
43 --- /dev/null
44 +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
45 @@ -0,0 +1,947 @@
46 +// SPDX-License-Identifier: GPL-2.0+
47 +/*
48 + * Common part for MediaTek MT753x gigabit switch
49 + *
50 + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
51 + *
52 + * Author: Weijie Gao <weijie.gao@mediatek.com>
53 + */
54 +
55 +#include <linux/kernel.h>
56 +#include <linux/delay.h>
57 +
58 +#include "mt753x.h"
59 +#include "mt753x_regs.h"
60 +#include "mt753x_phy.h"
61 +
62 +u32 tc_phy_read_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr)
63 +{
64 + u32 phy_val;
65 + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
66 + return phy_val;
67 +}
68 +
69 +void tc_phy_write_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
70 +{
71 + u32 phy_val;
72 + gsw->mmd_write(gsw, port_num, dev_addr, reg_addr, write_data);
73 + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
74 +}
75 +
76 +void switch_phy_write(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr, u32 write_data){
77 + gsw->mii_write(gsw, port_num, reg_addr, write_data);
78 +}
79 +
80 +u32 switch_phy_read(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr){
81 + return gsw->mii_read(gsw, port_num, reg_addr);
82 +}
83 +
84 +const u8 MT753x_ZCAL_TO_R50ohm_GE_TBL_100[64] = {
85 + 127, 127, 127, 127, 127, 127, 127, 127,
86 + 127, 127, 127, 127, 127, 123, 122, 117,
87 + 115, 112, 103, 100, 98, 87, 85, 83,
88 + 81, 72, 70, 68, 66, 64, 55, 53,
89 + 52, 50, 49, 48, 38, 36, 35, 34,
90 + 33, 32, 22, 21, 20, 19, 18, 17,
91 + 16, 7, 6, 5, 4, 3, 2, 1,
92 + 0, 0, 0, 0, 0, 0, 0, 0
93 +};
94 +
95 +const u8 MT753x_TX_OFFSET_TBL[64] = {
96 + 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
97 + 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
98 + 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8,
99 + 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, 0x0,
100 + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
101 + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
102 + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
103 + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f
104 +};
105 +
106 +u8 ge_cal_flag;
107 +
108 +u8 all_ge_ana_cal_wait(struct gsw_mt753x *gsw, u32 delay, u32 phyaddr) // for EN7512
109 +{
110 + u8 all_ana_cal_status;
111 + u32 cnt, tmp_1e_17c;
112 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
113 + cnt = 10000;
114 + do {
115 + udelay(delay);
116 + cnt--;
117 + all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1;
118 +
119 + } while ((all_ana_cal_status == 0) && (cnt != 0));
120 +
121 +
122 + if(all_ana_cal_status == 1) {
123 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
124 + return all_ana_cal_status;
125 + } else {
126 + pr_info("MDC/MDIO error\n");
127 + return 0;
128 + }
129 +
130 + return all_ana_cal_status;
131 +}
132 +
133 +
134 +
135 +
136 +int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
137 +{
138 + u8 rg_zcal_ctrl, all_ana_cal_status;
139 + u16 ad_cal_comp_out_init;
140 + u16 dev1e_e0_ana_cal_r5;
141 + int calibration_polarity;
142 + u8 cnt = 0;
143 + u16 dev1e_17a_tmp, dev1e_e0_tmp;
144 +
145 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00db, 0x1110)
146 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1110);
147 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00dc, 0x0000);
148 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0);
149 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00e1, 0x0000);
150 + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
151 +
152 + rg_zcal_ctrl = 0x20;
153 + dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
154 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, rg_zcal_ctrl);
155 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr);/* delay 20 usec */
156 + if (all_ana_cal_status == 0) {
157 + all_ana_cal_status = ANACAL_ERROR;
158 + printk(" GE Rext AnaCal ERROR init! \r\n");
159 + return -1;
160 + }
161 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a) >> 8) & 0x1;
162 + if (ad_cal_comp_out_init == 1)
163 + calibration_polarity = -1;
164 + else /* ad_cal_comp_out_init == 0 */
165 + calibration_polarity = 1;
166 + cnt = 0;
167 + while (all_ana_cal_status < ANACAL_ERROR) {
168 + cnt++;
169 + rg_zcal_ctrl += calibration_polarity;
170 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, (rg_zcal_ctrl));
171 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); /* delay 20 usec */
172 + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
173 + if (all_ana_cal_status == 0) {
174 + all_ana_cal_status = ANACAL_ERROR;
175 + printk(" GE Rext AnaCal ERROR 2! \r\n");
176 + return -1;
177 + } else if (((dev1e_17a_tmp >> 8) & 0x1) != ad_cal_comp_out_init) {
178 + all_ana_cal_status = ANACAL_FINISH;
179 + //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
180 + } else {
181 + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
182 + dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
183 + if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
184 + all_ana_cal_status = ANACAL_SATURATION;
185 + printk(" GE Rext AnaCal Saturation! \r\n");
186 + rg_zcal_ctrl = 0x20; /* 0 dB */
187 + }
188 + }
189 + }
190 +
191 + if (all_ana_cal_status == ANACAL_ERROR) {
192 + rg_zcal_ctrl = 0x20;
193 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
194 + } else if(all_ana_cal_status == ANACAL_FINISH){
195 + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
196 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, ((rg_zcal_ctrl << 8) | rg_zcal_ctrl));
197 + printk("0x1e-e0 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0));
198 + tc_phy_write_dev_reg(gsw, PHY0, 0x1f, 0x0115, ((rg_zcal_ctrl & 0x3f) >> 3));
199 + printk("0x1f-115 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x115));
200 + printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
201 + ge_cal_flag = 1;
202 + } else {
203 + printk("GE Rxet cal something wrong2\n");
204 + }
205 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
206 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
207 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
208 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
209 +}
210 +
211 +//-----------------------------------------------------------------
212 +int ge_cal_r50(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
213 +{
214 + u8 rg_zcal_ctrl, all_ana_cal_status, calibration_pair;
215 + u16 ad_cal_comp_out_init;
216 + u16 dev1e_e0_ana_cal_r5;
217 + int calibration_polarity;
218 + u8 cnt = 0;
219 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100);
220 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
221 +
222 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
223 + rg_zcal_ctrl = 0x20;
224 + dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0) & (~0x003f));
225 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
226 + if(calibration_pair == ANACAL_PAIR_A)
227 + {
228 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1101);
229 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
230 + //printk("R50 pair A 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
231 +
232 + }
233 + else if(calibration_pair == ANACAL_PAIR_B)
234 + {
235 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
236 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x1000);
237 + //printk("R50 pair B 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db),tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
238 +
239 + }
240 + else if(calibration_pair == ANACAL_PAIR_C)
241 + {
242 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
243 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0100);
244 + //printk("R50 pair C 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
245 +
246 + }
247 + else // if(calibration_pair == ANACAL_PAIR_D)
248 + {
249 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
250 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0010);
251 + //printk("R50 pair D 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
252 +
253 + }
254 +
255 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
256 + if(all_ana_cal_status == 0)
257 + {
258 + all_ana_cal_status = ANACAL_ERROR;
259 + printk( "GE R50 AnaCal ERROR init! \r\n");
260 + return -1;
261 + }
262 +
263 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1;
264 + if(ad_cal_comp_out_init == 1)
265 + calibration_polarity = -1;
266 + else
267 + calibration_polarity = 1;
268 +
269 + cnt = 0;
270 + while(all_ana_cal_status < ANACAL_ERROR)
271 + {
272 + cnt ++;
273 + rg_zcal_ctrl += calibration_polarity;
274 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
275 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
276 +
277 + if(all_ana_cal_status == 0)
278 + {
279 + all_ana_cal_status = ANACAL_ERROR;
280 + printk( " GE R50 AnaCal ERROR 2! \r\n");
281 + return -1;
282 + }
283 + else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init)
284 + {
285 + all_ana_cal_status = ANACAL_FINISH;
286 + }
287 + else {
288 + if((rg_zcal_ctrl == 0x3F)||(rg_zcal_ctrl == 0x00))
289 + {
290 + all_ana_cal_status = ANACAL_SATURATION; // need to FT
291 + printk( " GE R50 AnaCal Saturation! \r\n");
292 + }
293 + }
294 + }
295 +
296 + if(all_ana_cal_status == ANACAL_ERROR) {
297 + rg_zcal_ctrl = 0x20;
298 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
299 + }
300 + else {
301 + rg_zcal_ctrl = MT753x_ZCAL_TO_R50ohm_GE_TBL_100[rg_zcal_ctrl - 9];
302 + printk( " GE R50 AnaCal Done! (%d) (0x%x)(0x%x) \r\n", cnt, rg_zcal_ctrl, (rg_zcal_ctrl|0x80));
303 + }
304 +
305 + if(calibration_pair == ANACAL_PAIR_A) {
306 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x7f00);
307 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
308 + //printk( " GE-a 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
309 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000)));
310 + //printk( " GE-a 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
311 + }
312 + else if(calibration_pair == ANACAL_PAIR_B) {
313 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x007f);
314 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
315 + //printk( " GE-b 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
316 +
317 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080)));
318 + //printk( " GE-b 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
319 + }
320 + else if(calibration_pair == ANACAL_PAIR_C) {
321 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x7f00);
322 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
323 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000)));
324 + //printk( " GE-c 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
325 + } else {// if(calibration_pair == ANACAL_PAIR_D)
326 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x007f);
327 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
328 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080)));
329 + //printk( " GE-d 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
330 + }
331 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, ((rg_zcal_ctrl<<8)|rg_zcal_ctrl));
332 + }
333 +
334 + printk( " GE 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
335 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
336 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
337 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
338 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
339 +}
340 +
341 +int ge_cal_tx_offset(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
342 +{
343 + u8 all_ana_cal_status, calibration_pair;
344 + u16 ad_cal_comp_out_init;
345 + int calibration_polarity, tx_offset_temp;
346 + u8 tx_offset_reg_shift, tabl_idx, i;
347 + u8 cnt = 0;
348 + u16 tx_offset_reg, reg_temp, cal_temp;
349 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0100);
350 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001);
351 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0096, 0x8000);
352 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808);
353 + for(i = 0; i <= 4; i++)
354 + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
355 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++)
356 + {
357 + tabl_idx = 31;
358 + tx_offset_temp = MT753x_TX_OFFSET_TBL[tabl_idx];
359 +
360 + if(calibration_pair == ANACAL_PAIR_A) {
361 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5010);
362 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000);
363 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_0V));
364 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_0V));
365 + //printk("tx offset pairA 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
366 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x3f00));
367 + tx_offset_reg_shift = 8;
368 + tx_offset_reg = 0x0172;
369 +
370 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
371 + } else if(calibration_pair == ANACAL_PAIR_B) {
372 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5018);
373 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100);
374 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_0V));
375 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_0V));
376 + //printk("tx offset pairB 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
377 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x003f));
378 + tx_offset_reg_shift = 0;
379 + tx_offset_reg = 0x0172;
380 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
381 + } else if(calibration_pair == ANACAL_PAIR_C) {
382 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010);
383 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_0V));
384 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_0V));
385 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x3f00));
386 + //printk("tx offset pairC 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
387 + tx_offset_reg_shift = 8;
388 + tx_offset_reg = 0x0173;
389 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
390 + } else {// if(calibration_pair == ANACAL_PAIR_D)
391 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001);
392 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_0V));
393 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_0V));
394 + //printk("tx offset pairD 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
395 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x003f));
396 + tx_offset_reg_shift = 0;
397 + tx_offset_reg = 0x0173;
398 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
399 + }
400 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
401 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
402 + if(all_ana_cal_status == 0) {
403 + all_ana_cal_status = ANACAL_ERROR;
404 + printk( " GE Tx offset AnaCal ERROR init! \r\n");
405 + return -1;
406 + }
407 +
408 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1;
409 + if(ad_cal_comp_out_init == 1)
410 + calibration_polarity = 1;
411 + else
412 + calibration_polarity = -1;
413 +
414 + cnt = 0;
415 + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]);
416 + while(all_ana_cal_status < ANACAL_ERROR) {
417 +
418 + cnt ++;
419 + tabl_idx += calibration_polarity;
420 + //tx_offset_temp += calibration_polarity;
421 + //cal_temp = tx_offset_temp;
422 + cal_temp = MT753x_TX_OFFSET_TBL[tabl_idx];
423 + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]);
424 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(cal_temp<<tx_offset_reg_shift)));
425 +
426 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
427 + if(all_ana_cal_status == 0) {
428 + all_ana_cal_status = ANACAL_ERROR;
429 + printk( " GE Tx offset AnaCal ERROR init 2! \r\n");
430 + return -1;
431 + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) {
432 + all_ana_cal_status = ANACAL_FINISH;
433 + } else {
434 + if((tabl_idx == 0)||(tabl_idx == 0x3f)) {
435 + all_ana_cal_status = ANACAL_SATURATION;
436 + printk( " GE Tx offset AnaCal Saturation! \r\n");
437 + }
438 + }
439 + }
440 +
441 + if(all_ana_cal_status == ANACAL_ERROR) {
442 + tx_offset_temp = TX_AMP_OFFSET_0MV;
443 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
444 + } else {
445 + printk( " GE Tx offset AnaCal Done! (pair-%d)(%d)(0x%x) 0x1e_%x=0x%x\n", calibration_pair, cnt, MT753x_TX_OFFSET_TBL[tabl_idx], tx_offset_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg));
446 + }
447 + }
448 +
449 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000);
450 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000);
451 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000);
452 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000);
453 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000);
454 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000);
455 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
456 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
457 +
458 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
459 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
460 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
461 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
462 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000);
463 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000);
464 +}
465 +
466 +int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
467 +{
468 + u8 all_ana_cal_status, calibration_pair, i;
469 + u16 ad_cal_comp_out_init;
470 + int calibration_polarity;
471 + u32 tx_amp_reg_shift;
472 + u16 reg_temp;
473 + u32 tx_amp_temp, tx_amp_reg, cnt=0, tx_amp_reg_100;
474 + u32 reg_backup, reg_tmp;
475 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100);
476 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001);
477 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x0010);
478 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808);
479 +
480 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, 0xff00);
481 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27a, 0x33);
482 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0xffff);
483 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x300, 0x4);
484 + for(i = 0; i <= 4; i++)
485 + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
486 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
487 + tx_amp_temp = 0x20;
488 +
489 + if(calibration_pair == ANACAL_PAIR_A) {
490 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]
491 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_2V)); // 1e_17d
492 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_2V)); // 1e_181
493 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x012) & (~0xfc00));
494 + tx_amp_reg_shift = 10; // 1e_12[15:10]
495 + tx_amp_reg = 0x12;
496 + tx_amp_reg_100 = 0x16;
497 + } else if(calibration_pair == ANACAL_PAIR_B) {
498 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]
499 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_2V)); // 1e_17e
500 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_2V)); // 1e_182
501 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x017) & (~0x3f00));
502 + tx_amp_reg_shift = 8; // 1e_17[13:8]
503 + tx_amp_reg = 0x17;
504 + tx_amp_reg_100 = 0x18;
505 + } else if(calibration_pair == ANACAL_PAIR_C) {
506 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]
507 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_2V)); // 1e_17f
508 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_2V)); // 1e_183
509 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x019) & (~0x3f00));
510 + tx_amp_reg_shift = 8; // 1e_19[13:8]
511 + tx_amp_reg = 0x19;
512 + tx_amp_reg_100 = 0x20;
513 + } else { //if(calibration_pair == ANACAL_PAIR_D)
514 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]
515 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_2V)); // 1e_180
516 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_2V)); // 1e_184
517 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x021) & (~0x3f00));
518 + tx_amp_reg_shift = 8; // 1e_21[13:8]
519 + tx_amp_reg = 0x21;
520 + tx_amp_reg_100 = 0x22;
521 + }
522 + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift))); // 1e_12, 1e_17, 1e_19, 1e_21
523 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
524 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
525 + if(all_ana_cal_status == 0) {
526 + all_ana_cal_status = ANACAL_ERROR;
527 + printk( " GE Tx amp AnaCal ERROR init init! \r\n");
528 + return -1;
529 + }
530 +
531 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]
532 + if(ad_cal_comp_out_init == 1)
533 + calibration_polarity = -1;
534 + else
535 + calibration_polarity = 1;
536 +
537 + cnt =0;
538 + while(all_ana_cal_status < ANACAL_ERROR) {
539 + cnt ++;
540 + tx_amp_temp += calibration_polarity;
541 + //printk("tx_amp : %x, 1e %x = %x\n", tx_amp_temp, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift)));
542 + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
543 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
544 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
545 + if(all_ana_cal_status == 0) {
546 + all_ana_cal_status = ANACAL_ERROR;
547 + printk( " GE Tx amp AnaCal ERROR 2! \r\n");
548 + return -1;
549 + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) {
550 + //printk("TX AMP ANACAL_FINISH\n");
551 + all_ana_cal_status = ANACAL_FINISH;
552 + if (phyaddr == 0) {
553 + if (calibration_pair == ANACAL_PAIR_A)
554 + tx_amp_temp = tx_amp_temp - 2;
555 + else if(calibration_pair == ANACAL_PAIR_B)
556 + tx_amp_temp = tx_amp_temp - 1;
557 + else if(calibration_pair == ANACAL_PAIR_C)
558 + tx_amp_temp = tx_amp_temp - 2;
559 + else if(calibration_pair == ANACAL_PAIR_D)
560 + tx_amp_temp = tx_amp_temp - 1;
561 + } else if (phyaddr == 1) {
562 + if (calibration_pair == ANACAL_PAIR_A)
563 + tx_amp_temp = tx_amp_temp - 1;
564 + else if(calibration_pair == ANACAL_PAIR_B)
565 + tx_amp_temp = tx_amp_temp ;
566 + else if(calibration_pair == ANACAL_PAIR_C)
567 + tx_amp_temp = tx_amp_temp - 1;
568 + else if(calibration_pair == ANACAL_PAIR_D)
569 + tx_amp_temp = tx_amp_temp - 1;
570 + } else if (phyaddr == 2) {
571 + if (calibration_pair == ANACAL_PAIR_A)
572 + tx_amp_temp = tx_amp_temp;
573 + else if(calibration_pair == ANACAL_PAIR_B)
574 + tx_amp_temp = tx_amp_temp - 1;
575 + else if(calibration_pair == ANACAL_PAIR_C)
576 + tx_amp_temp = tx_amp_temp;
577 + else if(calibration_pair == ANACAL_PAIR_D)
578 + tx_amp_temp = tx_amp_temp - 1;
579 + } else if (phyaddr == 3) {
580 + tx_amp_temp = tx_amp_temp;
581 + } else if (phyaddr == 4) {
582 + if (calibration_pair == ANACAL_PAIR_A)
583 + tx_amp_temp = tx_amp_temp;
584 + else if(calibration_pair == ANACAL_PAIR_B)
585 + tx_amp_temp = tx_amp_temp - 1;
586 + else if(calibration_pair == ANACAL_PAIR_C)
587 + tx_amp_temp = tx_amp_temp;
588 + else if(calibration_pair == ANACAL_PAIR_D)
589 + tx_amp_temp = tx_amp_temp;
590 + }
591 + reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
592 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
593 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
594 + if (phyaddr == 0) {
595 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
596 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
597 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
598 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
599 + }
600 + if (tx_amp_reg_100 == 0x16) {
601 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
602 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+1+4)<<tx_amp_reg_shift)));
603 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
604 + }
605 + if (tx_amp_reg_100 == 0x18) {
606 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
607 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift)));
608 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
609 + }
610 + } else if (phyaddr == 1) {
611 + if (tx_amp_reg == 0x12) {
612 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
613 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 9));
614 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
615 + }
616 + if (tx_amp_reg == 0x17){
617 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
618 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
619 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
620 + }
621 + if (tx_amp_reg_100 == 0x16) {
622 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
623 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift)));
624 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
625 + }
626 + if (tx_amp_reg_100 == 0x18) {
627 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
628 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
629 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
630 + }
631 + } else if (phyaddr == 2) {
632 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
633 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
634 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 6));
635 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
636 + }
637 + if ((tx_amp_reg_100 == 0x16) || (tx_amp_reg_100 == 0x18)) {
638 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
639 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
640 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
641 + }
642 + } else if (phyaddr == 3) {
643 + if (tx_amp_reg == 0x12) {
644 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
645 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 4));
646 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
647 + }
648 + if (tx_amp_reg == 0x17) {
649 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
650 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
651 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
652 + }
653 + if (tx_amp_reg_100 == 0x16) {
654 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
655 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift)));
656 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
657 + }
658 + if (tx_amp_reg_100 == 0x18) {
659 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
660 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+3)<<tx_amp_reg_shift)));
661 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
662 + }
663 + } else if (phyaddr == 4) {
664 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
665 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
666 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 5));
667 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
668 + }
669 + if (tx_amp_reg_100 == 0x16) {
670 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
671 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift)));
672 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
673 + }
674 + if (tx_amp_reg_100 == 0x18) {
675 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
676 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
677 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
678 + }
679 + }
680 +
681 + if (calibration_pair == ANACAL_PAIR_A){
682 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
683 + reg_tmp = ((reg_backup & 0xfc00) >> 10);
684 + reg_tmp -= 8;
685 + reg_backup = 0x0000;
686 + reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
687 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
688 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
689 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
690 + reg_tmp = ((reg_backup & 0x3f) >> 0);
691 + reg_tmp -= 8;
692 + reg_backup = (reg_backup & (~0x3f));
693 + reg_backup |= (reg_tmp << 0);
694 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
695 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
696 + }
697 + else if(calibration_pair == ANACAL_PAIR_B){
698 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
699 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
700 + reg_tmp -= 8;
701 + reg_backup = 0x0000;
702 + reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
703 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
704 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
705 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
706 + reg_tmp = ((reg_backup & 0x3f) >> 0);
707 + reg_tmp -= 8;
708 + reg_backup = (reg_backup & (~0x3f));
709 + reg_backup |= (reg_tmp << 0);
710 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
711 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
712 + }
713 + else if(calibration_pair == ANACAL_PAIR_C){
714 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
715 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
716 + reg_tmp -= 8;
717 + reg_backup = (reg_backup & (~0x3f00));
718 + reg_backup |= (reg_tmp << 8);
719 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
720 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
721 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
722 + reg_tmp = ((reg_backup & 0x3f) >> 0);
723 + reg_tmp -= 8;
724 + reg_backup = (reg_backup & (~0x3f));
725 + reg_backup |= (reg_tmp << 0);
726 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
727 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
728 + }
729 + else if(calibration_pair == ANACAL_PAIR_D){
730 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
731 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
732 + reg_tmp -= 8;
733 + reg_backup = (reg_backup & (~0x3f00));
734 + reg_backup |= (reg_tmp << 8);
735 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
736 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
737 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
738 + reg_tmp = ((reg_backup & 0x3f) >> 0);
739 + reg_tmp -= 8;
740 + reg_backup = (reg_backup & (~0x3f));
741 + reg_backup |= (reg_tmp << 0);
742 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
743 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
744 + }
745 + printk( " GE Tx amp AnaCal Done! (pair-%d)(1e_%x = 0x%x)\n", calibration_pair, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
746 +
747 + } else {
748 + if((tx_amp_temp == 0x3f)||(tx_amp_temp == 0x00)) {
749 + all_ana_cal_status = ANACAL_SATURATION;
750 + printk( " GE Tx amp AnaCal Saturation! \r\n");
751 + }
752 + }
753 + }
754 +
755 + if(all_ana_cal_status == ANACAL_ERROR) {
756 + tx_amp_temp = 0x20;
757 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift)));
758 + }
759 + }
760 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000);
761 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000);
762 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000);
763 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000);
764 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000);
765 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000);
766 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
767 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
768 +
769 + /* disable analog calibration circuit */
770 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
771 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
772 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
773 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
774 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000);
775 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000);
776 +
777 +
778 +
779 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000);
780 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0x0fff);
781 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1000);
782 +
783 +}
784 +
785 +//-----------------------------------------------------------------
786 +
787 +int phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr)
788 +{
789 + u32 reg_tmp,reg_tmp0, reg_tmp1, i;
790 + u32 CALDLY = 40;
791 + int ret;
792 + switch_phy_write(gsw, phyaddr, R0, 0x140);
793 +
794 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1010);
795 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, RG_185, 0);
796 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x100, 0xc000);
797 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x403, 0x1099);
798 +
799 +#if (1)
800 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1f1f);
801 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x3300);
802 +
803 + reg_tmp1 = tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x27c);
804 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x11);
805 + reg_tmp = reg_tmp | (0xf << 12);
806 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, reg_tmp);
807 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
808 + /* calibration start ============ */
809 + printk("CALDLY = %d\n", CALDLY);
810 + if(ge_cal_flag == 0){
811 + ret = ge_cal_rext(gsw, 0, CALDLY);
812 + if (ret == -1){
813 + printk("ge_cal_rext error K port =%d\n", phyaddr);
814 + return ret;
815 + }
816 + ge_cal_flag = 1;
817 + }
818 +
819 + /* *** R50 Cal start ***************************** */
820 + /*phyaddress = 0*/
821 + ret = ge_cal_r50(gsw, phyaddr, CALDLY);
822 + if (ret == -1){
823 + printk("R50 error K port =%d\n", phyaddr);
824 + return ret;
825 + }
826 + /* *** R50 Cal end *** */
827 + /* *** Tx offset Cal start *********************** */
828 + ret = ge_cal_tx_offset(gsw, phyaddr, CALDLY);
829 + if (ret == -1){
830 + printk("ge_cal_tx_offset error K port =%d\n", phyaddr);
831 + return ret;
832 + }
833 + /* *** Tx offset Cal end *** */
834 +
835 + /* *** Tx Amp Cal start *** */
836 + ret = ge_cal_tx_amp(gsw, phyaddr, CALDLY);
837 + if (ret == -1){
838 + printk("ge_cal_tx_amp error K port =%d\n", phyaddr);
839 + return ret;
840 + }
841 + /* *** Tx Amp Cal end *** */
842 + /*tmp maybe changed*/
843 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1111);
844 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27b, 0x47);
845 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000);
846 +
847 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a8, 0x0810);
848 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, 0x0008);
849 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ab, 0x0810);
850 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ad, 0x0008);
851 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ae, 0x0106);
852 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b0, 0x0001);
853 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b1, 0x0106);
854 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b3, 0x0001);
855 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18c, 0x0001);
856 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18d, 0x0001);
857 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18e, 0x0001);
858 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18f, 0x0001);
859 +
860 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3aa);
861 + reg_tmp = reg_tmp & ~(0x1f00);
862 + reg_tmp = reg_tmp | 0x2 << 8;
863 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, reg_tmp);
864 +
865 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3a9);
866 + reg_tmp = reg_tmp & ~(0x1f);
867 + reg_tmp = reg_tmp | 0x2;
868 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a9, reg_tmp);
869 +#endif
870 +}
871 +
872 +void rx_dc_offset(struct gsw_mt753x *gsw, u8 phyaddr)
873 +{
874 + u32 reg_tmp1;
875 +
876 + //pr_info("PORT %d RX_DC_OFFSET\n", phyaddr);
877 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x96, 0x8000);
878 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x37, 0x3);
879 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x107, 0x4000);
880 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x1e5);
881 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x200f);
882 + udelay(40);
883 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x000f);
884 + udelay(40);
885 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x65);
886 +}
887 +
888 +void check_rx_dc_offset_pair_a(struct gsw_mt753x *gsw, u8 phyaddr)
889 +{
890 + u32 reg_tmp;
891 + u8 reg_val;
892 +
893 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x114f);
894 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
895 + reg_tmp = reg_tmp & 0xff;
896 + udelay(40);
897 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1142);
898 + udelay(40);
899 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
900 + reg_tmp = reg_tmp & 0xff;
901 + if ((reg_tmp & 0x80) != 0)
902 + reg_tmp = (~reg_tmp) + 1;
903 + if ((reg_tmp & 0xff) >4)
904 + pr_info("pairA RX_DC_OFFSET error");
905 +}
906 +
907 +void check_rx_dc_offset_pair_b(struct gsw_mt753x *gsw, u8 phyaddr)
908 +{
909 + u32 reg_tmp;
910 + u8 reg_val;
911 +
912 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1151);
913 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
914 + reg_tmp = reg_tmp & 0xff;
915 + udelay(40);
916 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1143);
917 + udelay(40);
918 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
919 + reg_tmp = reg_tmp & 0xff;
920 + if ((reg_tmp & 0x80) != 0)
921 + reg_tmp = (~reg_tmp) + 1;
922 + if ((reg_tmp & 0xff) >4)
923 + pr_info("pairB RX_DC_OFFSET error");
924 +}
925 +
926 +void check_rx_dc_offset_pair_c(struct gsw_mt753x *gsw, u8 phyaddr)
927 +{
928 + u32 reg_tmp;
929 + u8 reg_val;
930 +
931 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1153);
932 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
933 + reg_tmp = reg_tmp & 0xff;
934 + udelay(40);
935 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1144);
936 + udelay(40);
937 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
938 + reg_tmp = reg_tmp & 0xff;
939 + if ((reg_tmp & 0x80) != 0)
940 + reg_tmp = (~reg_tmp) + 1;
941 + if ((reg_tmp & 0xff) >4)
942 + pr_info("pairC RX_DC_OFFSET error");
943 +}
944 +
945 +void check_rx_dc_offset_pair_d(struct gsw_mt753x *gsw, u8 phyaddr)
946 +{
947 + u32 reg_tmp;
948 + u8 reg_val;
949 +
950 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1155);
951 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
952 + reg_tmp = reg_tmp & 0xff;
953 + udelay(40);
954 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1145);
955 + udelay(40);
956 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
957 + reg_tmp = reg_tmp & 0xff;
958 + if ((reg_tmp & 0x80) != 0)
959 + reg_tmp = (~reg_tmp) + 1;
960 + if ((reg_tmp & 0xff) >4)
961 + pr_info("pairD RX_DC_OFFSET error");
962 +}
963 +
964 +
965 +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr){
966 +
967 + int ret;
968 +
969 + phy_calibration(gsw, phyaddr);
970 +
971 + /*eye pic*/
972 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0, 0x187);
973 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x1, 0x1c9);
974 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x2, 0x1c6);
975 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3, 0x182);
976 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x4, 0x208);
977 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x5, 0x205);
978 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x6, 0x384);
979 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x7, 0x3cb);
980 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x8, 0x3c4);
981 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x9, 0x30a);
982 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xa, 0x00b);
983 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xb, 0x002);
984 +
985 + rx_dc_offset(gsw, phyaddr);
986 + check_rx_dc_offset_pair_a(gsw, phyaddr);
987 + check_rx_dc_offset_pair_b(gsw, phyaddr);
988 + check_rx_dc_offset_pair_c(gsw, phyaddr);
989 + check_rx_dc_offset_pair_d(gsw, phyaddr);
990 +
991 + return ret;
992 +}
993 diff --git a/target/linux/generic/files/drivers/net/phy/mtk/mt753x/mt753x_phy.h b/target/linux/generic/files/drivers/net/phy/mtk/mt753x/mt753x_phy.h
994 new file mode 100755
995 --- /dev/null
996 +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.h
997 @@ -0,0 +1,145 @@
998 +/* SPDX-License-Identifier: GPL-2.0+ */
999 +/*
1000 + * Register definitions for MediaTek MT753x Gigabit switches
1001 + *
1002 + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
1003 + *
1004 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1005 + */
1006 +
1007 +#ifndef _MT753X_PHY_H_
1008 +#define _MT753X_PHY_H_
1009 +
1010 +#include <linux/bitops.h>
1011 +
1012 +/*phy calibration use*/
1013 +#define DEV_1E 0x1E
1014 +/*global device 0x1f, always set P0*/
1015 +#define DEV_1F 0x1F
1016 +
1017 +
1018 +/************IEXT/REXT CAL***************/
1019 +/* bits range: for example BITS(16,23) = 0xFF0000*/
1020 +#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
1021 +#define ANACAL_INIT 0x01
1022 +#define ANACAL_ERROR 0xFD
1023 +#define ANACAL_SATURATION 0xFE
1024 +#define ANACAL_FINISH 0xFF
1025 +#define ANACAL_PAIR_A 0
1026 +#define ANACAL_PAIR_B 1
1027 +#define ANACAL_PAIR_C 2
1028 +#define ANACAL_PAIR_D 3
1029 +#define DAC_IN_0V 0x00
1030 +#define DAC_IN_2V 0xf0
1031 +#define TX_AMP_OFFSET_0MV 0x20
1032 +#define TX_AMP_OFFSET_VALID_BITS 6
1033 +
1034 +#define R0 0
1035 +#define PHY0 0
1036 +#define PHY1 1
1037 +#define PHY2 2
1038 +#define PHY3 3
1039 +#define PHY4 4
1040 +#define ANA_TEST_MODE BITS(8, 15)
1041 +#define TST_TCLK_SEL BITs(6, 7)
1042 +#define ANA_TEST_VGA_RG 0x100
1043 +
1044 +#define FORCE_MDI_CROSS_OVER BITS(3, 4)
1045 +#define T10_TEST_CTL_RG 0x145
1046 +#define RG_185 0x185
1047 +#define RG_TX_SLEW BIT(0)
1048 +#define ANA_CAL_0 0xdb
1049 +#define RG_CAL_CKINV BIT(12)
1050 +#define RG_ANA_CALEN BIT(8)
1051 +#define RG_REXT_CALEN BIT(4)
1052 +#define RG_ZCALEN_A BIT(0)
1053 +#define ANA_CAL_1 0xdc
1054 +#define RG_ZCALEN_B BIT(12)
1055 +#define RG_ZCALEN_C BIT(8)
1056 +#define RG_ZCALEN_D BIT(4)
1057 +#define RG_TXVOS_CALEN BIT(0)
1058 +#define ANA_CAL_6 0xe1
1059 +#define RG_CAL_REFSEL BIT(4)
1060 +#define RG_CAL_COMP_PWD BIT(0)
1061 +#define ANA_CAL_5 0xe0
1062 +#define RG_REXT_TRIM BITs(8, 13)
1063 +#define RG_ZCAL_CTRL BITs(0, 5)
1064 +#define RG_17A 0x17a
1065 +#define AD_CAL_COMP_OUT BIT(8)
1066 +#define RG_17B 0x17b
1067 +#define AD_CAL_CLK bit(0)
1068 +#define RG_17C 0x17c
1069 +#define DA_CALIN_FLAG bit(0)
1070 +/************R50 CAL****************************/
1071 +#define RG_174 0x174
1072 +#define RG_R50OHM_RSEL_TX_A_EN BIT[15]
1073 +#define CR_R50OHM_RSEL_TX_A BITS[8:14]
1074 +#define RG_R50OHM_RSEL_TX_B_EN BIT[7]
1075 +#define CR_R50OHM_RSEL_TX_B BITS[6:0]
1076 +#define RG_175 0x175
1077 +#define RG_R50OHM_RSEL_TX_C_EN BITS[15]
1078 +#define CR_R50OHM_RSEL_TX_C BITS[8:14]
1079 +#define RG_R50OHM_RSEL_TX_D_EN BIT[7]
1080 +#define CR_R50OHM_RSEL_TX_D BITS[0:6]
1081 +/**********TX offset Calibration***************************/
1082 +#define RG_95 0x96
1083 +#define BYPASS_TX_OFFSET_CAL BIT(15)
1084 +#define RG_3E 0x3e
1085 +#define BYPASS_PD_TXVLD_A BIT(15)
1086 +#define BYPASS_PD_TXVLD_B BIT(14)
1087 +#define BYPASS_PD_TXVLD_C BIT(13)
1088 +#define BYPASS_PD_TXVLD_D BIT(12)
1089 +#define BYPASS_PD_TX_10M BIT(11)
1090 +#define POWER_DOWN_TXVLD_A BIT(7)
1091 +#define POWER_DOWN_TXVLD_B BIT(6)
1092 +#define POWER_DOWN_TXVLD_C BIT(5)
1093 +#define POWER_DOWN_TXVLD_D BIT(4)
1094 +#define POWER_DOWN_TX_10M BIT(3)
1095 +#define RG_DD 0xdd
1096 +#define RG_TXG_CALEN_A BIT(12)
1097 +#define RG_TXG_CALEN_B BIT(8)
1098 +#define RG_TXG_CALEN_C BIT(4)
1099 +#define RG_TXG_CALEN_D BIT(0)
1100 +#define RG_17D 0x17D
1101 +#define FORCE_DASN_DAC_IN0_A BIT(15)
1102 +#define DASN_DAC_IN0_A BITS(0, 9)
1103 +#define RG_17E 0x17E
1104 +#define FORCE_DASN_DAC_IN0_B BIT(15)
1105 +#define DASN_DAC_IN0_B BITS(0, 9)
1106 +#define RG_17F 0x17F
1107 +
1108 +#define FORCE_DASN_DAC_IN0_C BIT(15)
1109 +#define DASN_DAC_IN0_C BITS(0, 9)
1110 +#define RG_180 0x180
1111 +#define FORCE_DASN_DAC_IN0_D BIT(15)
1112 +#define DASN_DAC_IN0_D BITS(0, 9)
1113 +
1114 +#define RG_181 0x181
1115 +#define FORCE_DASN_DAC_IN1_A BIT(15)
1116 +#define DASN_DAC_IN1_A BITS(0, 9)
1117 +#define RG_182 0x182
1118 +#define FORCE_DASN_DAC_IN1_B BIT(15)
1119 +#define DASN_DAC_IN1_B BITS(0, 9)
1120 +#define RG_183 0x183
1121 +#define FORCE_DASN_DAC_IN1_C BIT15]
1122 +#define DASN_DAC_IN1_C BITS(0, 9)
1123 +#define RG_184 0x184
1124 +#define FORCE_DASN_DAC_IN1_D BIT(15)
1125 +#define DASN_DAC_IN1_D BITS(0, 9)
1126 +#define RG_172 0x172
1127 +#define CR_TX_AMP_OFFSET_A BITS(8, 13)
1128 +#define CR_TX_AMP_OFFSET_B BITS(0, 5)
1129 +#define RG_173 0x173
1130 +#define CR_TX_AMP_OFFSET_C BITS(8, 13)
1131 +#define CR_TX_AMP_OFFSET_D BITS(0, 5)
1132 +/**********TX Amp Calibration ***************************/
1133 +#define RG_12 0x12
1134 +#define DA_TX_I2MPB_A_GBE BITS(10, 15)
1135 +#define RG_17 0x17
1136 +#define DA_TX_I2MPB_B_GBE BITS(8, 13)
1137 +#define RG_19 0x19
1138 +#define DA_TX_I2MPB_C_GBE BITS(8, 13)
1139 +#define RG_21 0x21
1140 +#define DA_TX_I2MPB_D_GBE BITS(8, 13)
1141 +
1142 +#endif /* _MT753X_REGS_H_ */
Staging tree of Jo-Philipp Wich