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6eba4017d754c4b87a8825638fb0ac5585f4557c
[openwrt/staging/jow.git] / target / linux / mediatek / patches-4.19 / 0003-mt7531-gsw-internal_phy_calibration.patch
1 --- a/drivers/net/phy/mtk/mt753x/Makefile
2 +++ b/drivers/net/phy/mtk/mt753x/Makefile
3 @@ -5,6 +5,6 @@
4 obj-$(CONFIG_MT753X_GSW) += mt753x.o
5
6 mt753x-y += mt753x_mdio.o mt7530.o mt7531.o \
7 - mt753x_common.o mt753x_nl.o
8 + mt753x_common.o mt753x_nl.o mt753x_phy.o
9
10
11 --- a/drivers/net/phy/mtk/mt753x/mt7531.c
12 +++ b/drivers/net/phy/mtk/mt753x/mt7531.c
13 @@ -454,6 +454,21 @@ static void mt7531_core_pll_setup(struct gsw_mt753x *gsw)
14
15 static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw)
16 {
17 + u32 i;
18 + int ret;
19 +
20 + dev_info(gsw->dev,">>>>>>>>>>>>>>>>>>>>>>>>>>>>> START CALIBRATION:\n");
21 + for (i = 0; i < 5; i++) {
22 + dev_info(gsw->dev, "-------- gephy-calbration (port:%d) --------\n",
23 + i);
24 + ret = mt753x_phy_calibration(gsw, i);
25 +
26 + /* set Auto-negotiation with giga extension. */
27 + gsw->mii_write(gsw, i, 0, 0x1340);
28 + if (ret)
29 + return ret;
30 + }
31 +
32 return 0;
33 }
34
35 --- a/drivers/net/phy/mtk/mt753x/mt753x.h
36 +++ b/drivers/net/phy/mtk/mt753x/mt753x.h
37 @@ -141,6 +141,8 @@ void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
38 void mt753x_irq_worker(struct work_struct *work);
39 void mt753x_irq_enable(struct gsw_mt753x *gsw);
40
41 +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr);
42 +
43 /* MDIO Indirect Access Registers */
44 #define MII_MMD_ACC_CTL_REG 0x0d
45 #define MMD_CMD_S 14
46 --- /dev/null
47 +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
48 @@ -0,0 +1,1061 @@
49 +// SPDX-License-Identifier: GPL-2.0+
50 +/*
51 + * Common part for MediaTek MT753x gigabit switch
52 + *
53 + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
54 + *
55 + * Author: Weijie Gao <weijie.gao@mediatek.com>
56 + */
57 +
58 +#include <linux/kernel.h>
59 +#include <linux/delay.h>
60 +
61 +#include "mt753x.h"
62 +#include "mt753x_regs.h"
63 +#include "mt753x_phy.h"
64 +
65 +u32 tc_phy_read_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr)
66 +{
67 + u32 phy_val;
68 + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
69 +
70 + //printk("switch phy cl45 r %d 0x%x 0x%x = %x\n",port_num, dev_addr, reg_addr, phy_val);
71 + //switch_phy_read_cl45(port_num, dev_addr, reg_addr, &phy_val);
72 + return phy_val;
73 +}
74 +
75 +void tc_phy_write_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
76 +{
77 + u32 phy_val;
78 + gsw->mmd_write(gsw, port_num, dev_addr, reg_addr, write_data);
79 + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
80 + //printk("switch phy cl45 w %d 0x%x 0x%x 0x%x --> read back 0x%x\n",port_num, dev_addr, reg_addr, write_data, phy_val);
81 + //switch_phy_write_cl45(port_num, dev_addr, reg_addr, write_data);
82 +}
83 +
84 +void switch_phy_write(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr, u32 write_data){
85 + gsw->mii_write(gsw, port_num, reg_addr, write_data);
86 +}
87 +
88 +u32 switch_phy_read(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr){
89 + return gsw->mii_read(gsw, port_num, reg_addr);
90 +}
91 +
92 +const u8 MT753x_ZCAL_TO_R50ohm_GE_TBL_100[64] = {
93 + 127, 127, 127, 127, 127, 127, 127, 127,
94 + 127, 127, 127, 127, 127, 123, 122, 117,
95 + 115, 112, 103, 100, 98, 87, 85, 83,
96 + 81, 72, 70, 68, 66, 64, 55, 53,
97 + 52, 50, 49, 48, 38, 36, 35, 34,
98 + 33, 32, 22, 21, 20, 19, 18, 17,
99 + 16, 7, 6, 5, 4, 3, 2, 1,
100 + 0, 0, 0, 0, 0, 0, 0, 0
101 +};
102 +
103 +const u8 MT753x_TX_OFFSET_TBL[64] = {
104 + 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
105 + 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
106 + 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8,
107 + 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, 0x0,
108 + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
109 + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
110 + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
111 + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f
112 +};
113 +
114 +u8 ge_cal_flag;
115 +
116 +u8 all_ge_ana_cal_wait(struct gsw_mt753x *gsw, u32 delay, u32 phyaddr) // for EN7512
117 +{
118 + u8 all_ana_cal_status;
119 + u32 cnt, tmp_1e_17c;
120 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017c, 0x0001); // da_calin_flag pull high
121 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
122 + //printk("delay = %d\n", delay);
123 +
124 + cnt = 10000;
125 + do {
126 + udelay(delay);
127 + cnt--;
128 + all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1;
129 +
130 + } while ((all_ana_cal_status == 0) && (cnt != 0));
131 +
132 +
133 + if(all_ana_cal_status == 1) {
134 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
135 + return all_ana_cal_status;
136 + } else {
137 + tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c);
138 + if ((tmp_1e_17c & 0x1) != 1) {
139 + pr_info("FIRST MDC/MDIO write error\n");
140 + pr_info("FIRST 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c));
141 +
142 + }
143 + printk("re-K again\n");
144 +
145 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
146 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
147 + cnt = 10000;
148 + do {
149 + udelay(delay);
150 + cnt--;
151 + tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c);
152 + if ((tmp_1e_17c & 0x1) != 1) {
153 + pr_info("SECOND MDC/MDIO write error\n");
154 + pr_info("SECOND 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c));
155 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
156 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
157 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
158 + }
159 + } while ((cnt != 0) && (tmp_1e_17c == 0));
160 +
161 + cnt = 10000;
162 + do {
163 + udelay(delay);
164 + cnt--;
165 + all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1;
166 +
167 + } while ((all_ana_cal_status == 0) && (cnt != 0));
168 +
169 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
170 + }
171 +
172 + if(all_ana_cal_status == 0){
173 + pr_info("!!!!!!!!!!!! dev1Eh_reg17b ERROR\n");
174 + }
175 +
176 + return all_ana_cal_status;
177 +}
178 +
179 +
180 +
181 +
182 +int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
183 +{
184 + u8 rg_zcal_ctrl, all_ana_cal_status;
185 + u16 ad_cal_comp_out_init;
186 + u16 dev1e_e0_ana_cal_r5;
187 + int calibration_polarity;
188 + u8 cnt = 0;
189 + u16 dev1e_17a_tmp, dev1e_e0_tmp;
190 +
191 + /* *** Iext/Rext Cal start ************ */
192 + all_ana_cal_status = ANACAL_INIT;
193 + /* analog calibration enable, Rext calibration enable */
194 + /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
195 + /* 1e_dc[0]:rg_txvos_calen */
196 + /* 1e_e1[4]:rg_cal_refsel(0:1.2V) */
197 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00db, 0x1110)
198 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1110);
199 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00dc, 0x0000);
200 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0);
201 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00e1, 0x0000);
202 + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
203 +
204 + rg_zcal_ctrl = 0x20;/* start with 0 dB */
205 + dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0); // get default value
206 + /* 1e_e0[5:0]:rg_zcal_ctrl */
207 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, rg_zcal_ctrl);
208 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr);/* delay 20 usec */
209 +
210 + if (all_ana_cal_status == 0) {
211 + all_ana_cal_status = ANACAL_ERROR;
212 + printk(" GE Rext AnaCal ERROR init! \r\n");
213 + return -1;
214 + }
215 + /* 1e_17a[8]:ad_cal_comp_out */
216 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a) >> 8) & 0x1;
217 + if (ad_cal_comp_out_init == 1)
218 + calibration_polarity = -1;
219 + else /* ad_cal_comp_out_init == 0 */
220 + calibration_polarity = 1;
221 + cnt = 0;
222 + while (all_ana_cal_status < ANACAL_ERROR) {
223 + cnt++;
224 + rg_zcal_ctrl += calibration_polarity;
225 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, (rg_zcal_ctrl));
226 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); /* delay 20 usec */
227 + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
228 + if (all_ana_cal_status == 0) {
229 + all_ana_cal_status = ANACAL_ERROR;
230 + printk(" GE Rext AnaCal ERROR 2! \r\n");
231 + return -1;
232 + } else if (((dev1e_17a_tmp >> 8) & 0x1) != ad_cal_comp_out_init) {
233 + all_ana_cal_status = ANACAL_FINISH;
234 + //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
235 + } else {
236 + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
237 + dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
238 + if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
239 + all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
240 + printk(" GE Rext AnaCal Saturation! \r\n");
241 + rg_zcal_ctrl = 0x20; /* 0 dB */
242 + }
243 + }
244 + }
245 +
246 + if (all_ana_cal_status == ANACAL_ERROR) {
247 + rg_zcal_ctrl = 0x20; /* 0 dB */
248 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
249 + } else if(all_ana_cal_status == ANACAL_FINISH){
250 + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
251 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, ((rg_zcal_ctrl << 8) | rg_zcal_ctrl));
252 + printk("0x1e-e0 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0));
253 + /* **** 1f_115[2:0] = rg_zcal_ctrl[5:3] // Mog review */
254 + tc_phy_write_dev_reg(gsw, PHY0, 0x1f, 0x0115, ((rg_zcal_ctrl & 0x3f) >> 3));
255 + printk("0x1f-115 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x115));
256 + printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
257 + ge_cal_flag = 1;
258 + } else {
259 + printk("GE Rxet cal something wrong2\n");
260 + }
261 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
262 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
263 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
264 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
265 +}
266 +
267 +//-----------------------------------------------------------------
268 +int ge_cal_r50(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
269 +{
270 + u8 rg_zcal_ctrl, all_ana_cal_status, calibration_pair;
271 + u16 ad_cal_comp_out_init;
272 + u16 dev1e_e0_ana_cal_r5;
273 + int calibration_polarity;
274 + u8 cnt = 0;
275 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
276 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // 1e_dc[0]:rg_txvos_calen
277 +
278 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
279 + rg_zcal_ctrl = 0x20; // start with 0 dB
280 + dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00e0) & (~0x003f));
281 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); // 1e_e0[5:0]:rg_zcal_ctrl
282 + if(calibration_pair == ANACAL_PAIR_A)
283 + {
284 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1101); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
285 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
286 + //printk("R50 pair A 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
287 +
288 + }
289 + else if(calibration_pair == ANACAL_PAIR_B)
290 + {
291 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
292 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x1000); // 1e_dc[12]:rg_zcalen_b
293 + //printk("R50 pair B 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db),tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
294 +
295 + }
296 + else if(calibration_pair == ANACAL_PAIR_C)
297 + {
298 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
299 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0100); // 1e_dc[8]:rg_zcalen_c
300 + //printk("R50 pair C 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
301 +
302 + }
303 + else // if(calibration_pair == ANACAL_PAIR_D)
304 + {
305 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
306 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0010); // 1e_dc[4]:rg_zcalen_d
307 + //printk("R50 pair D 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
308 +
309 + }
310 +
311 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
312 + if(all_ana_cal_status == 0)
313 + {
314 + all_ana_cal_status = ANACAL_ERROR;
315 + printk( "GE R50 AnaCal ERROR init! \r\n");
316 + return -1;
317 + }
318 +
319 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
320 + if(ad_cal_comp_out_init == 1)
321 + calibration_polarity = -1;
322 + else
323 + calibration_polarity = 1;
324 +
325 + cnt = 0;
326 + while(all_ana_cal_status < ANACAL_ERROR)
327 + {
328 + cnt ++;
329 + rg_zcal_ctrl += calibration_polarity;
330 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
331 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
332 +
333 + if(all_ana_cal_status == 0)
334 + {
335 + all_ana_cal_status = ANACAL_ERROR;
336 + printk( " GE R50 AnaCal ERROR 2! \r\n");
337 + return -1;
338 + }
339 + else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init)
340 + {
341 + all_ana_cal_status = ANACAL_FINISH;
342 + }
343 + else {
344 + if((rg_zcal_ctrl == 0x3F)||(rg_zcal_ctrl == 0x00))
345 + {
346 + all_ana_cal_status = ANACAL_SATURATION; // need to FT
347 + printk( " GE R50 AnaCal Saturation! \r\n");
348 + }
349 + }
350 + }
351 +
352 + if(all_ana_cal_status == ANACAL_ERROR) {
353 + rg_zcal_ctrl = 0x20; // 0 dB
354 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
355 + }
356 + else {
357 + rg_zcal_ctrl = MT753x_ZCAL_TO_R50ohm_GE_TBL_100[rg_zcal_ctrl - 9]; // wait Mog zcal/r50 mapping table
358 + printk( " GE R50 AnaCal Done! (%d) (0x%x)(0x%x) \r\n", cnt, rg_zcal_ctrl, (rg_zcal_ctrl|0x80));
359 + }
360 +
361 + if(calibration_pair == ANACAL_PAIR_A) {
362 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x7f00);
363 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
364 + //printk( " GE-a 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
365 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_174[15:8]
366 + //printk( " GE-a 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
367 + }
368 + else if(calibration_pair == ANACAL_PAIR_B) {
369 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x007f);
370 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
371 + //printk( " GE-b 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
372 +
373 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_174[7:0]
374 + //printk( " GE-b 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
375 + }
376 + else if(calibration_pair == ANACAL_PAIR_C) {
377 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x7f00);
378 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
379 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_175[15:8]
380 + //printk( " GE-c 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
381 + } else {// if(calibration_pair == ANACAL_PAIR_D)
382 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x007f);
383 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
384 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_175[7:0]
385 + //printk( " GE-d 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
386 + }
387 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, ((rg_zcal_ctrl<<8)|rg_zcal_ctrl));
388 + }
389 +
390 + printk( " GE 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
391 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
392 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
393 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
394 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
395 +}
396 +
397 +int ge_cal_tx_offset(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
398 +{
399 + u8 all_ana_cal_status, calibration_pair;
400 + u16 ad_cal_comp_out_init;
401 + int calibration_polarity, tx_offset_temp;
402 + u8 tx_offset_reg_shift, tabl_idx, i;
403 + u8 cnt = 0;
404 + u16 tx_offset_reg, reg_temp, cal_temp;
405 + //switch_phy_write(phyaddr, R0, 0x2100);//harry tmp
406 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
407 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen
408 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0096, 0x8000); // 1e_96[15]:bypass_tx_offset_cal, Hw bypass, Fw cal
409 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e
410 + for(i = 0; i <= 4; i++)
411 + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
412 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++)
413 + {
414 + tabl_idx = 31;
415 + tx_offset_temp = MT753x_TX_OFFSET_TBL[tabl_idx];
416 +
417 + if(calibration_pair == ANACAL_PAIR_A) {
418 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5010);
419 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:rg_txg_calen_a
420 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_0V)); // 1e_17d:dac_in0_a
421 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_0V)); // 1e_181:dac_in1_a
422 + //printk("tx offset pairA 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
423 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x3f00));
424 + tx_offset_reg_shift = 8; // 1e_172[13:8]
425 + tx_offset_reg = 0x0172;
426 +
427 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
428 + } else if(calibration_pair == ANACAL_PAIR_B) {
429 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5018);
430 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]:rg_txg_calen_b
431 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_0V)); // 1e_17e:dac_in0_b
432 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_0V)); // 1e_182:dac_in1_b
433 + //printk("tx offset pairB 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
434 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x003f));
435 + tx_offset_reg_shift = 0; // 1e_172[5:0]
436 + tx_offset_reg = 0x0172;
437 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
438 + } else if(calibration_pair == ANACAL_PAIR_C) {
439 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]:rg_txg_calen_c
440 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_0V)); // 1e_17f:dac_in0_c
441 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_0V)); // 1e_183:dac_in1_c
442 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x3f00));
443 + //printk("tx offset pairC 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
444 + tx_offset_reg_shift = 8; // 1e_173[13:8]
445 + tx_offset_reg = 0x0173;
446 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
447 + } else {// if(calibration_pair == ANACAL_PAIR_D)
448 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]:rg_txg_calen_d
449 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_0V)); // 1e_180:dac_in0_d
450 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_0V)); // 1e_184:dac_in1_d
451 + //printk("tx offset pairD 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
452 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x003f));
453 + tx_offset_reg_shift = 0; // 1e_173[5:0]
454 + tx_offset_reg = 0x0173;
455 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
456 + }
457 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); // 1e_172, 1e_173
458 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
459 + if(all_ana_cal_status == 0) {
460 + all_ana_cal_status = ANACAL_ERROR;
461 + printk( " GE Tx offset AnaCal ERROR init! \r\n");
462 + return -1;
463 + }
464 +
465 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
466 + if(ad_cal_comp_out_init == 1)
467 + calibration_polarity = 1;
468 + else
469 + calibration_polarity = -1;
470 +
471 + cnt = 0;
472 + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]);
473 + while(all_ana_cal_status < ANACAL_ERROR) {
474 +
475 + cnt ++;
476 + tabl_idx += calibration_polarity;
477 + //tx_offset_temp += calibration_polarity;
478 + //cal_temp = tx_offset_temp;
479 + cal_temp = MT753x_TX_OFFSET_TBL[tabl_idx];
480 + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]);
481 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(cal_temp<<tx_offset_reg_shift)));
482 +
483 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
484 + if(all_ana_cal_status == 0) {
485 + all_ana_cal_status = ANACAL_ERROR;
486 + printk( " GE Tx offset AnaCal ERROR init 2! \r\n");
487 + return -1;
488 + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) {
489 + all_ana_cal_status = ANACAL_FINISH;
490 + } else {
491 + if((tabl_idx == 0)||(tabl_idx == 0x3f)) {
492 + all_ana_cal_status = ANACAL_SATURATION; // need to FT
493 + printk( " GE Tx offset AnaCal Saturation! \r\n");
494 + }
495 + }
496 + }
497 +
498 + if(all_ana_cal_status == ANACAL_ERROR) {
499 + tx_offset_temp = TX_AMP_OFFSET_0MV;
500 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
501 + } else {
502 + printk( " GE Tx offset AnaCal Done! (pair-%d)(%d)(0x%x) 0x1e_%x=0x%x\n", calibration_pair, cnt, MT753x_TX_OFFSET_TBL[tabl_idx], tx_offset_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg));
503 + }
504 + }
505 +
506 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000);
507 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000);
508 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000);
509 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000);
510 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000);
511 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000);
512 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
513 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
514 +
515 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
516 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
517 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
518 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
519 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000); // disable Tx VLD force mode
520 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000); // disable Tx offset/amplitude calibration circuit
521 +}
522 +
523 +int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
524 +{
525 + u8 all_ana_cal_status, calibration_pair, i;
526 + u16 ad_cal_comp_out_init;
527 + int calibration_polarity;
528 + u32 tx_amp_reg_shift;
529 + u16 reg_temp;
530 + u32 tx_amp_temp, tx_amp_reg, cnt=0, tx_amp_reg_100;
531 + u32 debug_tmp, reg_backup, reg_tmp;
532 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
533 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen
534 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x0010); // 1e_e1[4]:select 1V
535 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e:enable Tx VLD
536 +
537 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, 0xff00);
538 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27a, 0x33);
539 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0xffff);
540 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x300, 0x4);
541 + for(i = 0; i <= 4; i++)
542 + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
543 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
544 + tx_amp_temp = 0x20; // start with 0 dB
545 +
546 + if(calibration_pair == ANACAL_PAIR_A) {
547 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:tx_a amp calibration enable
548 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_2V)); // 1e_17d:dac_in0_a
549 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_2V)); // 1e_181:dac_in1_a
550 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x012) & (~0xfc00));
551 + tx_amp_reg_shift = 10; // 1e_12[15:10]
552 + tx_amp_reg = 0x12;
553 + tx_amp_reg_100 = 0x16;
554 + } else if(calibration_pair == ANACAL_PAIR_B) {
555 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]:tx_b amp calibration enable
556 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_2V)); // 1e_17e:dac_in0_b
557 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_2V)); // 1e_182:dac_in1_b
558 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x017) & (~0x3f00));
559 + tx_amp_reg_shift = 8; // 1e_17[13:8]
560 + tx_amp_reg = 0x17;
561 + tx_amp_reg_100 = 0x18;
562 + } else if(calibration_pair == ANACAL_PAIR_C) {
563 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]:tx_c amp calibration enable
564 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_2V)); // 1e_17f:dac_in0_c
565 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_2V)); // 1e_183:dac_in1_c
566 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x019) & (~0x3f00));
567 + tx_amp_reg_shift = 8; // 1e_19[13:8]
568 + tx_amp_reg = 0x19;
569 + tx_amp_reg_100 = 0x20;
570 + } else { //if(calibration_pair == ANACAL_PAIR_D)
571 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]:tx_d amp calibration enable
572 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_2V)); // 1e_180:dac_in0_d
573 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_2V)); // 1e_184:dac_in1_d
574 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x021) & (~0x3f00));
575 + tx_amp_reg_shift = 8; // 1e_21[13:8]
576 + tx_amp_reg = 0x21;
577 + tx_amp_reg_100 = 0x22;
578 + }
579 + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift))); // 1e_12, 1e_17, 1e_19, 1e_21
580 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
581 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
582 + if(all_ana_cal_status == 0) {
583 + all_ana_cal_status = ANACAL_ERROR;
584 + printk( " GE Tx amp AnaCal ERROR init init! \r\n");
585 + return -1;
586 + }
587 +
588 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
589 + if(ad_cal_comp_out_init == 1)
590 + calibration_polarity = -1;
591 + else
592 + calibration_polarity = 1;
593 +
594 + cnt =0;
595 + while(all_ana_cal_status < ANACAL_ERROR) {
596 + cnt ++;
597 + tx_amp_temp += calibration_polarity;
598 + //printk("tx_amp : %x, 1e %x = %x\n", tx_amp_temp, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift)));
599 + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
600 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
601 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
602 + if(all_ana_cal_status == 0) {
603 + all_ana_cal_status = ANACAL_ERROR;
604 + printk( " GE Tx amp AnaCal ERROR 2! \r\n");
605 + return -1;
606 + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) {
607 + //printk("TX AMP ANACAL_FINISH\n");
608 + all_ana_cal_status = ANACAL_FINISH;
609 + if (phyaddr == 0) {
610 + if (calibration_pair == ANACAL_PAIR_A)
611 + tx_amp_temp = tx_amp_temp - 2;
612 + else if(calibration_pair == ANACAL_PAIR_B)
613 + tx_amp_temp = tx_amp_temp - 1;
614 + else if(calibration_pair == ANACAL_PAIR_C)
615 + tx_amp_temp = tx_amp_temp - 2;
616 + else if(calibration_pair == ANACAL_PAIR_D)
617 + tx_amp_temp = tx_amp_temp - 1;
618 + } else if (phyaddr == 1) {
619 + if (calibration_pair == ANACAL_PAIR_A)
620 + tx_amp_temp = tx_amp_temp - 1;
621 + else if(calibration_pair == ANACAL_PAIR_B)
622 + tx_amp_temp = tx_amp_temp ;
623 + else if(calibration_pair == ANACAL_PAIR_C)
624 + tx_amp_temp = tx_amp_temp - 1;
625 + else if(calibration_pair == ANACAL_PAIR_D)
626 + tx_amp_temp = tx_amp_temp - 1;
627 + } else if (phyaddr == 2) {
628 + if (calibration_pair == ANACAL_PAIR_A)
629 + tx_amp_temp = tx_amp_temp;
630 + else if(calibration_pair == ANACAL_PAIR_B)
631 + tx_amp_temp = tx_amp_temp - 1;
632 + else if(calibration_pair == ANACAL_PAIR_C)
633 + tx_amp_temp = tx_amp_temp;
634 + else if(calibration_pair == ANACAL_PAIR_D)
635 + tx_amp_temp = tx_amp_temp - 1;
636 + } else if (phyaddr == 3) {
637 + tx_amp_temp = tx_amp_temp;
638 + } else if (phyaddr == 4) {
639 + if (calibration_pair == ANACAL_PAIR_A)
640 + tx_amp_temp = tx_amp_temp;
641 + else if(calibration_pair == ANACAL_PAIR_B)
642 + tx_amp_temp = tx_amp_temp - 1;
643 + else if(calibration_pair == ANACAL_PAIR_C)
644 + tx_amp_temp = tx_amp_temp;
645 + else if(calibration_pair == ANACAL_PAIR_D)
646 + tx_amp_temp = tx_amp_temp;
647 + }
648 + reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
649 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
650 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
651 + if (phyaddr == 0) {
652 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
653 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
654 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
655 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
656 + }
657 + if (tx_amp_reg_100 == 0x16) {
658 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
659 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+1+4)<<tx_amp_reg_shift)));
660 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
661 + }
662 + if (tx_amp_reg_100 == 0x18) {
663 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
664 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift)));
665 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
666 + }
667 + } else if (phyaddr == 1) {
668 + if (tx_amp_reg == 0x12) {
669 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
670 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 9));
671 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
672 + }
673 + if (tx_amp_reg == 0x17){
674 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
675 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
676 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
677 + }
678 + if (tx_amp_reg_100 == 0x16) {
679 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
680 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift)));
681 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
682 + }
683 + if (tx_amp_reg_100 == 0x18) {
684 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
685 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
686 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
687 + }
688 + } else if (phyaddr == 2) {
689 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
690 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
691 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 6));
692 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
693 + }
694 + if ((tx_amp_reg_100 == 0x16) || (tx_amp_reg_100 == 0x18)) {
695 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
696 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
697 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
698 + }
699 + } else if (phyaddr == 3) {
700 + if (tx_amp_reg == 0x12) {
701 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
702 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 4));
703 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
704 + }
705 + if (tx_amp_reg == 0x17) {
706 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
707 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
708 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
709 + }
710 + if (tx_amp_reg_100 == 0x16) {
711 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
712 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift)));
713 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
714 + }
715 + if (tx_amp_reg_100 == 0x18) {
716 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
717 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+3)<<tx_amp_reg_shift)));
718 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
719 + }
720 + } else if (phyaddr == 4) {
721 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
722 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
723 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 5));
724 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
725 + }
726 + if (tx_amp_reg_100 == 0x16) {
727 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
728 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift)));
729 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
730 + }
731 + if (tx_amp_reg_100 == 0x18) {
732 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
733 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
734 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
735 + }
736 + }
737 +
738 + if (calibration_pair == ANACAL_PAIR_A){
739 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
740 + reg_tmp = ((reg_backup & 0xfc00) >> 10);
741 + reg_tmp -= 8;
742 + reg_backup = (reg_backup & (~0xfc00));
743 + reg_backup |= (reg_tmp << 10);
744 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
745 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
746 + //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
747 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
748 + reg_tmp = ((reg_backup & 0x3f) >> 0);
749 + reg_tmp -= 8;
750 + reg_backup = (reg_backup & (~0x3f));
751 + reg_backup |= (reg_tmp << 0);
752 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
753 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
754 + //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
755 + }
756 + else if(calibration_pair == ANACAL_PAIR_B){
757 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
758 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
759 + reg_tmp -= 8;
760 + reg_backup = (reg_backup & (~0x3f00));
761 + reg_backup |= (reg_tmp << 8);
762 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
763 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
764 + //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
765 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
766 + reg_tmp = ((reg_backup & 0x3f) >> 0);
767 + reg_tmp -= 8;
768 + reg_backup = (reg_backup & (~0x3f));
769 + reg_backup |= (reg_tmp << 0);
770 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
771 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
772 + //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
773 + }
774 + else if(calibration_pair == ANACAL_PAIR_C){
775 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
776 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
777 + reg_tmp -= 8;
778 + reg_backup = (reg_backup & (~0x3f00));
779 + reg_backup |= (reg_tmp << 8);
780 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
781 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
782 + //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
783 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
784 + reg_tmp = ((reg_backup & 0x3f) >> 0);
785 + reg_tmp -= 8;
786 + reg_backup = (reg_backup & (~0x3f));
787 + reg_backup |= (reg_tmp << 0);
788 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
789 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
790 + //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
791 + }
792 + else if(calibration_pair == ANACAL_PAIR_D){
793 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
794 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
795 + reg_tmp -= 8;
796 + reg_backup = (reg_backup & (~0x3f00));
797 + reg_backup |= (reg_tmp << 8);
798 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
799 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
800 + //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
801 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
802 + reg_tmp = ((reg_backup & 0x3f) >> 0);
803 + reg_tmp -= 8;
804 + reg_backup = (reg_backup & (~0x3f));
805 + reg_backup |= (reg_tmp << 0);
806 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
807 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
808 + //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
809 + }
810 +
811 + if (calibration_pair == ANACAL_PAIR_A){
812 + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
813 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
814 + //printk("1e.012 = 0x%x\n", debug_tmp);
815 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
816 + //printk("1e.016 = 0x%x\n", debug_tmp);
817 + }
818 +
819 + else if(calibration_pair == ANACAL_PAIR_B){
820 + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
821 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
822 + //printk("1e.017 = 0x%x\n", debug_tmp);
823 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
824 + //printk("1e.018 = 0x%x\n", debug_tmp);
825 + }
826 + else if(calibration_pair == ANACAL_PAIR_C){
827 + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
828 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
829 + //printk("1e.019 = 0x%x\n", debug_tmp);
830 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
831 + //printk("1e.020 = 0x%x\n", debug_tmp);
832 + }
833 + else if(calibration_pair == ANACAL_PAIR_D){
834 + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
835 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
836 + //printk("1e.021 = 0x%x\n", debug_tmp);
837 + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
838 + //printk("1e.022 = 0x%x\n", debug_tmp);
839 + }
840 +
841 +
842 + printk( " GE Tx amp AnaCal Done! (pair-%d)(1e_%x = 0x%x)\n", calibration_pair, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
843 +
844 + } else {
845 + if((tx_amp_temp == 0x3f)||(tx_amp_temp == 0x00)) {
846 + all_ana_cal_status = ANACAL_SATURATION; // need to FT
847 + printk( " GE Tx amp AnaCal Saturation! \r\n");
848 + }
849 + }
850 + }
851 +
852 + if(all_ana_cal_status == ANACAL_ERROR) {
853 + tx_amp_temp = 0x20;
854 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift)));
855 + }
856 + }
857 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000);
858 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000);
859 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000);
860 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000);
861 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000);
862 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000);
863 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
864 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
865 +
866 + /* disable analog calibration circuit */
867 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
868 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
869 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
870 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
871 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000); // disable Tx VLD force mode
872 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000); // disable Tx offset/amplitude calibration circuit
873 +
874 +
875 +
876 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000);
877 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0x0fff);
878 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1000);
879 +
880 +}
881 +
882 +//-----------------------------------------------------------------
883 +
884 +int phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr)
885 +{
886 + u32 reg_tmp,reg_tmp0, reg_tmp1, i;
887 + u32 CALDLY = 40;
888 + int ret;
889 + /* set [12]AN disable, [8]full duplex, [13/6]1000Mbps */
890 + //tc_phy_write_dev_reg(phyaddr, 0x0, 0x0140);
891 + switch_phy_write(gsw, phyaddr, R0, 0x140);
892 +
893 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1010);/* fix mdi */
894 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, RG_185, 0);/* disable tx slew control */
895 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x100, 0xc000);/* BG voltage output */
896 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x403, 0x1099); //bypass efuse
897 +
898 +#if (1)
899 + // 1f_27c[12:8] cr_da_tx_i2mpb_10m Trimming TX bias setup(@10M)
900 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1f1f);
901 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x3300);
902 +
903 + reg_tmp1 = tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x27c);
904 + //dev1Fh_reg273h TXVLD DA register - Adjust voltage mode TX amplitude.
905 + //tc_phy_write_dev_reg(phyaddr, 0x1f, 0x273, 0);
906 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x1000);
907 + //reg_tmp1 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x273);
908 + //printk("reg_tmp1273 = %x\n", reg_tmp1);
909 + /*1e_11 TX overshoot Enable (PAIR A/B/C/D) in gbe mode*/
910 +
911 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x11);
912 + reg_tmp = reg_tmp | (0xf << 12);
913 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, reg_tmp);
914 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
915 + /* calibration start ============ */
916 + printk("CALDLY = %d\n", CALDLY);
917 + if(ge_cal_flag == 0){
918 + ret = ge_cal_rext(gsw, 0, CALDLY);
919 + if (ret == -1){
920 + printk("ge_cal_rext error K port =%d\n", phyaddr);
921 + return ret;
922 + }
923 + ge_cal_flag = 1;
924 + }
925 +
926 + /* *** R50 Cal start ***************************** */
927 + /*phyaddress = 0*/
928 + ret = ge_cal_r50(gsw, phyaddr, CALDLY);
929 + if (ret == -1){
930 + printk("R50 error K port =%d\n", phyaddr);
931 + return ret;
932 + }
933 + /* *** R50 Cal end *** */
934 + /* *** Tx offset Cal start *********************** */
935 + ret = ge_cal_tx_offset(gsw, phyaddr, CALDLY);
936 + if (ret == -1){
937 + printk("ge_cal_tx_offset error K port =%d\n", phyaddr);
938 + return ret;
939 + }
940 + /* *** Tx offset Cal end *** */
941 +
942 + /* *** Tx Amp Cal start *** */
943 + ret = ge_cal_tx_amp(gsw, phyaddr, CALDLY);
944 + if (ret == -1){
945 + printk("ge_cal_tx_amp error K port =%d\n", phyaddr);
946 + return ret;
947 + }
948 + /* *** Tx Amp Cal end *** */
949 + /*tmp maybe changed*/
950 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1111);
951 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27b, 0x47);
952 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000);
953 +
954 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a8, 0x0810);
955 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, 0x0008);
956 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ab, 0x0810);
957 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ad, 0x0008);
958 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ae, 0x0106);
959 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b0, 0x0001);
960 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b1, 0x0106);
961 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b3, 0x0001);
962 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18c, 0x0001);
963 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18d, 0x0001);
964 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18e, 0x0001);
965 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18f, 0x0001);
966 +
967 + /*da_tx_bias1_b_tx_standby = 5'b10 (dev1eh_reg3aah[12:8])*/
968 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3aa);
969 + reg_tmp = reg_tmp & ~(0x1f00);
970 + reg_tmp = reg_tmp | 0x2 << 8;
971 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, reg_tmp);
972 +
973 + /*da_tx_bias1_a_tx_standby = 5'b10 (dev1eh_reg3a9h[4:0])*/
974 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3a9);
975 + reg_tmp = reg_tmp & ~(0x1f);
976 + reg_tmp = reg_tmp | 0x2;
977 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a9, reg_tmp);
978 +#endif
979 +}
980 +
981 +void rx_dc_offset(struct gsw_mt753x *gsw, u8 phyaddr)
982 +{
983 + u32 reg_tmp1;
984 +
985 + pr_info("PORT %d RX_DC_OFFSET\n", phyaddr);
986 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x96, 0x8000);
987 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x37, 0x3);
988 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x107, 0x4000);
989 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x1e5);
990 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x200f);
991 + udelay(40);
992 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x000f);
993 + udelay(40);
994 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x65);
995 +}
996 +
997 +void check_rx_dc_offset_pair_a(struct gsw_mt753x *gsw, u8 phyaddr)
998 +{
999 + u32 reg_tmp;
1000 + u8 reg_val;
1001 +
1002 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x114f);
1003 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1004 + reg_tmp = reg_tmp & 0xff;
1005 + pr_info("before pairA output = %x\n", reg_tmp);
1006 + udelay(40);
1007 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1142);
1008 + udelay(40);
1009 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1010 + reg_tmp = reg_tmp & 0xff;
1011 + pr_info("after pairA output = %x\n", reg_tmp);
1012 + if ((reg_tmp & 0x80) != 0)
1013 + reg_tmp = (~reg_tmp) + 1;
1014 + if ((reg_tmp & 0xff) >4)
1015 + pr_info("pairA RX_DC_OFFSET error");
1016 +}
1017 +
1018 +void check_rx_dc_offset_pair_b(struct gsw_mt753x *gsw, u8 phyaddr)
1019 +{
1020 + u32 reg_tmp;
1021 + u8 reg_val;
1022 +
1023 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1151);
1024 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1025 + reg_tmp = reg_tmp & 0xff;
1026 + pr_info("before pairB output = %x\n", reg_tmp);
1027 + udelay(40);
1028 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1143);
1029 + udelay(40);
1030 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1031 + reg_tmp = reg_tmp & 0xff;
1032 + pr_info("after pairB output = %x\n", reg_tmp);
1033 + if ((reg_tmp & 0x80) != 0)
1034 + reg_tmp = (~reg_tmp) + 1;
1035 + if ((reg_tmp & 0xff) >4)
1036 + pr_info("pairB RX_DC_OFFSET error");
1037 +}
1038 +
1039 +void check_rx_dc_offset_pair_c(struct gsw_mt753x *gsw, u8 phyaddr)
1040 +{
1041 + u32 reg_tmp;
1042 + u8 reg_val;
1043 +
1044 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1153);
1045 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1046 + reg_tmp = reg_tmp & 0xff;
1047 + pr_info("before pairC output = %x\n", reg_tmp);
1048 + udelay(40);
1049 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1144);
1050 + udelay(40);
1051 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1052 + reg_tmp = reg_tmp & 0xff;
1053 + pr_info("after pairC output = %x\n", reg_tmp);
1054 + if ((reg_tmp & 0x80) != 0)
1055 + reg_tmp = (~reg_tmp) + 1;
1056 + if ((reg_tmp & 0xff) >4)
1057 + pr_info("pairC RX_DC_OFFSET error");
1058 +}
1059 +
1060 +void check_rx_dc_offset_pair_d(struct gsw_mt753x *gsw, u8 phyaddr)
1061 +{
1062 + u32 reg_tmp;
1063 + u8 reg_val;
1064 +
1065 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1155);
1066 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1067 + reg_tmp = reg_tmp & 0xff;
1068 + pr_info("before pairD output = %x\n", reg_tmp);
1069 + udelay(40);
1070 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1145);
1071 + udelay(40);
1072 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
1073 + reg_tmp = reg_tmp & 0xff;
1074 + pr_info("after pairD output = %x\n", reg_tmp);
1075 + if ((reg_tmp & 0x80) != 0)
1076 + reg_tmp = (~reg_tmp) + 1;
1077 + if ((reg_tmp & 0xff) >4)
1078 + pr_info("pairD RX_DC_OFFSET error");
1079 +}
1080 +
1081 +
1082 +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr){
1083 +
1084 + int ret;
1085 +
1086 + phy_calibration(gsw, phyaddr);
1087 +
1088 + /*eye pic*/
1089 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0, 0x187);
1090 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x1, 0x1c9);
1091 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x2, 0x1c6);
1092 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3, 0x182);
1093 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x4, 0x208);
1094 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x5, 0x205);
1095 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x6, 0x384);
1096 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x7, 0x3cb);
1097 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x8, 0x3c4);
1098 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x9, 0x30a);
1099 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xa, 0x00b);
1100 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xb, 0x002);
1101 +
1102 + rx_dc_offset(gsw, phyaddr);
1103 + check_rx_dc_offset_pair_a(gsw, phyaddr);
1104 + check_rx_dc_offset_pair_b(gsw, phyaddr);
1105 + check_rx_dc_offset_pair_c(gsw, phyaddr);
1106 + check_rx_dc_offset_pair_d(gsw, phyaddr);
1107 +
1108 + return ret;
1109 +}
1110 diff --git a/target/linux/generic/files/drivers/net/phy/mtk/mt753x/mt753x_phy.h b/target/linux/generic/files/drivers/net/phy/mtk/mt753x/mt753x_phy.h
1111 new file mode 100755
1112 --- /dev/null
1113 +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.h
1114 @@ -0,0 +1,145 @@
1115 +/* SPDX-License-Identifier: GPL-2.0+ */
1116 +/*
1117 + * Register definitions for MediaTek MT753x Gigabit switches
1118 + *
1119 + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
1120 + *
1121 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1122 + */
1123 +
1124 +#ifndef _MT753X_PHY_H_
1125 +#define _MT753X_PHY_H_
1126 +
1127 +#include <linux/bitops.h>
1128 +
1129 +/*phy calibration use*/
1130 +#define DEV_1E 0x1E
1131 +/*global device 0x1f, always set P0*/
1132 +#define DEV_1F 0x1F
1133 +
1134 +
1135 +/************IEXT/REXT CAL***************/
1136 +/* bits range: for example BITS(16,23) = 0xFF0000*/
1137 +#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
1138 +#define ANACAL_INIT 0x01
1139 +#define ANACAL_ERROR 0xFD
1140 +#define ANACAL_SATURATION 0xFE
1141 +#define ANACAL_FINISH 0xFF
1142 +#define ANACAL_PAIR_A 0
1143 +#define ANACAL_PAIR_B 1
1144 +#define ANACAL_PAIR_C 2
1145 +#define ANACAL_PAIR_D 3
1146 +#define DAC_IN_0V 0x00
1147 +#define DAC_IN_2V 0xf0
1148 +#define TX_AMP_OFFSET_0MV 0x20
1149 +#define TX_AMP_OFFSET_VALID_BITS 6
1150 +
1151 +#define R0 0
1152 +#define PHY0 0
1153 +#define PHY1 1
1154 +#define PHY2 2
1155 +#define PHY3 3
1156 +#define PHY4 4
1157 +#define ANA_TEST_MODE BITS(8, 15)
1158 +#define TST_TCLK_SEL BITs(6, 7)
1159 +#define ANA_TEST_VGA_RG 0x100
1160 +
1161 +#define FORCE_MDI_CROSS_OVER BITS(3, 4)
1162 +#define T10_TEST_CTL_RG 0x145
1163 +#define RG_185 0x185
1164 +#define RG_TX_SLEW BIT(0)
1165 +#define ANA_CAL_0 0xdb
1166 +#define RG_CAL_CKINV BIT(12)
1167 +#define RG_ANA_CALEN BIT(8)
1168 +#define RG_REXT_CALEN BIT(4)
1169 +#define RG_ZCALEN_A BIT(0)
1170 +#define ANA_CAL_1 0xdc
1171 +#define RG_ZCALEN_B BIT(12)
1172 +#define RG_ZCALEN_C BIT(8)
1173 +#define RG_ZCALEN_D BIT(4)
1174 +#define RG_TXVOS_CALEN BIT(0)
1175 +#define ANA_CAL_6 0xe1
1176 +#define RG_CAL_REFSEL BIT(4)
1177 +#define RG_CAL_COMP_PWD BIT(0)
1178 +#define ANA_CAL_5 0xe0
1179 +#define RG_REXT_TRIM BITs(8, 13)
1180 +#define RG_ZCAL_CTRL BITs(0, 5)
1181 +#define RG_17A 0x17a
1182 +#define AD_CAL_COMP_OUT BIT(8)
1183 +#define RG_17B 0x17b
1184 +#define AD_CAL_CLK bit(0)
1185 +#define RG_17C 0x17c
1186 +#define DA_CALIN_FLAG bit(0)
1187 +/************R50 CAL****************************/
1188 +#define RG_174 0x174
1189 +#define RG_R50OHM_RSEL_TX_A_EN BIT[15]
1190 +#define CR_R50OHM_RSEL_TX_A BITS[8:14]
1191 +#define RG_R50OHM_RSEL_TX_B_EN BIT[7]
1192 +#define CR_R50OHM_RSEL_TX_B BITS[6:0]
1193 +#define RG_175 0x175
1194 +#define RG_R50OHM_RSEL_TX_C_EN BITS[15]
1195 +#define CR_R50OHM_RSEL_TX_C BITS[8:14]
1196 +#define RG_R50OHM_RSEL_TX_D_EN BIT[7]
1197 +#define CR_R50OHM_RSEL_TX_D BITS[0:6]
1198 +/**********TX offset Calibration***************************/
1199 +#define RG_95 0x96
1200 +#define BYPASS_TX_OFFSET_CAL BIT(15)
1201 +#define RG_3E 0x3e
1202 +#define BYPASS_PD_TXVLD_A BIT(15)
1203 +#define BYPASS_PD_TXVLD_B BIT(14)
1204 +#define BYPASS_PD_TXVLD_C BIT(13)
1205 +#define BYPASS_PD_TXVLD_D BIT(12)
1206 +#define BYPASS_PD_TX_10M BIT(11)
1207 +#define POWER_DOWN_TXVLD_A BIT(7)
1208 +#define POWER_DOWN_TXVLD_B BIT(6)
1209 +#define POWER_DOWN_TXVLD_C BIT(5)
1210 +#define POWER_DOWN_TXVLD_D BIT(4)
1211 +#define POWER_DOWN_TX_10M BIT(3)
1212 +#define RG_DD 0xdd
1213 +#define RG_TXG_CALEN_A BIT(12)
1214 +#define RG_TXG_CALEN_B BIT(8)
1215 +#define RG_TXG_CALEN_C BIT(4)
1216 +#define RG_TXG_CALEN_D BIT(0)
1217 +#define RG_17D 0x17D
1218 +#define FORCE_DASN_DAC_IN0_A BIT(15)
1219 +#define DASN_DAC_IN0_A BITS(0, 9)
1220 +#define RG_17E 0x17E
1221 +#define FORCE_DASN_DAC_IN0_B BIT(15)
1222 +#define DASN_DAC_IN0_B BITS(0, 9)
1223 +#define RG_17F 0x17F
1224 +
1225 +#define FORCE_DASN_DAC_IN0_C BIT(15)
1226 +#define DASN_DAC_IN0_C BITS(0, 9)
1227 +#define RG_180 0x180
1228 +#define FORCE_DASN_DAC_IN0_D BIT(15)
1229 +#define DASN_DAC_IN0_D BITS(0, 9)
1230 +
1231 +#define RG_181 0x181
1232 +#define FORCE_DASN_DAC_IN1_A BIT(15)
1233 +#define DASN_DAC_IN1_A BITS(0, 9)
1234 +#define RG_182 0x182
1235 +#define FORCE_DASN_DAC_IN1_B BIT(15)
1236 +#define DASN_DAC_IN1_B BITS(0, 9)
1237 +#define RG_183 0x183
1238 +#define FORCE_DASN_DAC_IN1_C BIT15]
1239 +#define DASN_DAC_IN1_C BITS(0, 9)
1240 +#define RG_184 0x184
1241 +#define FORCE_DASN_DAC_IN1_D BIT(15)
1242 +#define DASN_DAC_IN1_D BITS(0, 9)
1243 +#define RG_172 0x172
1244 +#define CR_TX_AMP_OFFSET_A BITS(8, 13)
1245 +#define CR_TX_AMP_OFFSET_B BITS(0, 5)
1246 +#define RG_173 0x173
1247 +#define CR_TX_AMP_OFFSET_C BITS(8, 13)
1248 +#define CR_TX_AMP_OFFSET_D BITS(0, 5)
1249 +/**********TX Amp Calibration ***************************/
1250 +#define RG_12 0x12
1251 +#define DA_TX_I2MPB_A_GBE BITS(10, 15)
1252 +#define RG_17 0x17
1253 +#define DA_TX_I2MPB_B_GBE BITS(8, 13)
1254 +#define RG_19 0x19
1255 +#define DA_TX_I2MPB_C_GBE BITS(8, 13)
1256 +#define RG_21 0x21
1257 +#define DA_TX_I2MPB_D_GBE BITS(8, 13)
1258 +
1259 +#endif /* _MT753X_REGS_H_ */
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