target/linux/mediatek/patches-4.14/0217-arm64-dts-mt7622-add-flash-related-device-nodes.patch

   1 From 0a84c72d1c606129b8af670cbcc73be4168ab753 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Fri, 29 Dec 2017 10:36:37 +0800
   4 Subject: [PATCH 217/224] arm64: dts: mt7622: add flash related device nodes
   5
   6 add nodes for NOR flash, parallel Nand flash with error correction code
   7 support.
   8
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 Cc: RogerCC Lin <rogercc.lin@mediatek.com>
  11 Cc: Guochun Mao <guochun.mao@mediatek.com>
  12 ---
  13  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 21 +++++++++++++++++
  14  arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 34 ++++++++++++++++++++++++++++
  15  2 files changed, 55 insertions(+)
  16
  17 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  18 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  19 @@ -235,6 +235,10 @@
  20         };
  21  };
  22
  23 +&bch {
  24 +       status = "disabled";
  25 +};
  26 +
  27  &btif {
  28         status = "okay";
  29  };
  30 @@ -257,6 +261,23 @@
  31         status = "okay";
  32  };
  33
  34 +&nandc {
  35 +       pinctrl-names = "default";
  36 +       pinctrl-0 = <&parallel_nand_pins>;
  37 +       status = "disabled";
  38 +};
  39 +
  40 +&nor_flash {
  41 +       pinctrl-names = "default";
  42 +       pinctrl-0 = <&spi_nor_pins>;
  43 +       status = "disabled";
  44 +
  45 +       flash@0 {
  46 +               compatible = "jedec,spi-nor";
  47 +               reg = <0>;
  48 +       };
  49 +};
  50 +
  51  &pwm {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pwm7_pins>;
  54 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  55 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  56 @@ -468,6 +468,40 @@
  57                 status = "disabled";
  58         };
  59
  60 +       nandc: nfi@1100d000 {
  61 +               compatible = "mediatek,mt7622-nfc";
  62 +               reg = <0 0x1100D000 0 0x1000>;
  63 +               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
  64 +               clocks = <&pericfg CLK_PERI_NFI_PD>,
  65 +                        <&pericfg CLK_PERI_SNFI_PD>;
  66 +               clock-names = "nfi_clk", "pad_clk";
  67 +               ecc-engine = <&bch>;
  68 +               #address-cells = <1>;
  69 +               #size-cells = <0>;
  70 +               status = "disabled";
  71 +       };
  72 +
  73 +       bch: ecc@1100e000 {
  74 +               compatible = "mediatek,mt7622-ecc";
  75 +               reg = <0 0x1100e000 0 0x1000>;
  76 +               interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
  77 +               clocks = <&pericfg CLK_PERI_NFIECC_PD>;
  78 +               clock-names = "nfiecc_clk";
  79 +               status = "disabled";
  80 +       };
  81 +
  82 +       nor_flash: spi@11014000 {
  83 +               compatible = "mediatek,mt7622-nor",
  84 +                            "mediatek,mt8173-nor";
  85 +               reg = <0 0x11014000 0 0xe0>;
  86 +               clocks = <&pericfg CLK_PERI_FLASH_PD>,
  87 +                        <&topckgen CLK_TOP_FLASH_SEL>;
  88 +               clock-names = "spi", "sf";
  89 +               #address-cells = <1>;
  90 +               #size-cells = <0>;
  91 +               status = "disabled";
  92 +       };
  93 +
  94         spi1: spi@11016000 {
  95                 compatible = "mediatek,mt7622-spi";
  96                 reg = <0 0x11016000 0 0x100>;