target/linux/mediatek/patches-4.14/0101-reset-mediatek-add-reset-controller-dt-bindings-requ.patch

   1 From 5d6a82632eb7258c8ca49cc96c18b8b4071b6639 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Wed, 20 Sep 2017 17:40:16 +0800
   4 Subject: [PATCH 101/224] reset: mediatek: add reset controller dt-bindings
   5  required header for MT7622 SoC
   6
   7 Add the reset controller dt-bindings exported from infracfg, pericfg,
   8 hifsys and ethsys which could be found on MT7622 SoC. So that we can
   9 reference them from within a device-tree file.
  10
  11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  12 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
  13 ---
  14  include/dt-bindings/reset/mt7622-reset.h | 94 ++++++++++++++++++++++++++++++++
  15  1 file changed, 94 insertions(+)
  16  create mode 100644 include/dt-bindings/reset/mt7622-reset.h
  17
  18 --- /dev/null
  19 +++ b/include/dt-bindings/reset/mt7622-reset.h
  20 @@ -0,0 +1,94 @@
  21 +/*
  22 + * Copyright (c) 2017 MediaTek Inc.
  23 + * Author: Sean Wang <sean.wang@mediatek.com>
  24 + *
  25 + * This program is free software; you can redistribute it and/or modify
  26 + * it under the terms of the GNU General Public License version 2 as
  27 + * published by the Free Software Foundation.
  28 + *
  29 + * This program is distributed in the hope that it will be useful,
  30 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32 + * GNU General Public License for more details.
  33 + */
  34 +
  35 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
  36 +#define _DT_BINDINGS_RESET_CONTROLLER_MT7622
  37 +
  38 +/* INFRACFG resets */
  39 +#define MT7622_INFRA_EMI_REG_RST               0
  40 +#define MT7622_INFRA_DRAMC0_A0_RST             1
  41 +#define MT7622_INFRA_APCIRQ_EINT_RST           3
  42 +#define MT7622_INFRA_APXGPT_RST                        4
  43 +#define MT7622_INFRA_SCPSYS_RST                        5
  44 +#define MT7622_INFRA_PMIC_WRAP_RST             7
  45 +#define MT7622_INFRA_IRRX_RST                  9
  46 +#define MT7622_INFRA_EMI_RST                   16
  47 +#define MT7622_INFRA_WED0_RST                  17
  48 +#define MT7622_INFRA_DRAMC_RST                 18
  49 +#define MT7622_INFRA_CCI_INTF_RST              19
  50 +#define MT7622_INFRA_TRNG_RST                  21
  51 +#define MT7622_INFRA_SYSIRQ_RST                        22
  52 +#define MT7622_INFRA_WED1_RST                  25
  53 +
  54 +/* PERICFG Subsystem resets */
  55 +#define MT7622_PERI_UART0_SW_RST               0
  56 +#define MT7622_PERI_UART1_SW_RST               1
  57 +#define MT7622_PERI_UART2_SW_RST               2
  58 +#define MT7622_PERI_UART3_SW_RST               3
  59 +#define MT7622_PERI_UART4_SW_RST               4
  60 +#define MT7622_PERI_BTIF_SW_RST                        6
  61 +#define MT7622_PERI_PWM_SW_RST                 8
  62 +#define MT7622_PERI_AUXADC_SW_RST              10
  63 +#define MT7622_PERI_DMA_SW_RST                 11
  64 +#define MT7622_PERI_IRTX_SW_RST                        13
  65 +#define MT7622_PERI_NFI_SW_RST                 14
  66 +#define MT7622_PERI_THERM_SW_RST               16
  67 +#define MT7622_PERI_MSDC0_SW_RST               19
  68 +#define MT7622_PERI_MSDC1_SW_RST               20
  69 +#define MT7622_PERI_I2C0_SW_RST                        22
  70 +#define MT7622_PERI_I2C1_SW_RST                        23
  71 +#define MT7622_PERI_I2C2_SW_RST                        24
  72 +#define MT7622_PERI_SPI0_SW_RST                        33
  73 +#define MT7622_PERI_SPI1_SW_RST                        34
  74 +#define MT7622_PERI_FLASHIF_SW_RST             36
  75 +
  76 +/* TOPRGU resets */
  77 +#define MT7622_TOPRGU_INFRA_RST                        0
  78 +#define MT7622_TOPRGU_ETHDMA_RST               1
  79 +#define MT7622_TOPRGU_DDRPHY_RST               6
  80 +#define MT7622_TOPRGU_INFRA_AO_RST             8
  81 +#define MT7622_TOPRGU_CONN_RST                 9
  82 +#define MT7622_TOPRGU_APMIXED_RST              10
  83 +#define MT7622_TOPRGU_CONN_MCU_RST             12
  84 +
  85 +/* PCIe/SATA Subsystem resets */
  86 +#define MT7622_SATA_PHY_REG_RST                        12
  87 +#define MT7622_SATA_PHY_SW_RST                 13
  88 +#define MT7622_SATA_AXI_BUS_RST                        15
  89 +#define MT7622_PCIE1_CORE_RST                  19
  90 +#define MT7622_PCIE1_MMIO_RST                  20
  91 +#define MT7622_PCIE1_HRST                      21
  92 +#define MT7622_PCIE1_USER_RST                  22
  93 +#define MT7622_PCIE1_PIPE_RST                  23
  94 +#define MT7622_PCIE0_CORE_RST                  27
  95 +#define MT7622_PCIE0_MMIO_RST                  28
  96 +#define MT7622_PCIE0_HRST                      29
  97 +#define MT7622_PCIE0_USER_RST                  30
  98 +#define MT7622_PCIE0_PIPE_RST                  31
  99 +
 100 +/* SSUSB Subsystem resets */
 101 +#define MT7622_SSUSB_PHY_PWR_RST               3
 102 +#define MT7622_SSUSB_MAC_PWR_RST               4
 103 +
 104 +/* ETHSYS Subsystem resets */
 105 +#define MT7622_ETHSYS_SYS_RST                  0
 106 +#define MT7622_ETHSYS_MCM_RST                  2
 107 +#define MT7622_ETHSYS_HSDMA_RST                        5
 108 +#define MT7622_ETHSYS_FE_RST                   6
 109 +#define MT7622_ETHSYS_GMAC_RST                 23
 110 +#define MT7622_ETHSYS_EPHY_RST                 24
 111 +#define MT7622_ETHSYS_CRYPTO_RST               29
 112 +#define MT7622_ETHSYS_PPE_RST                  31
 113 +
 114 +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */