target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2023 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include "clk-mtk.h"
  14 #include "clk-gate.h"
  15 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
  16
  17 static const struct mtk_gate_regs ethdma_cg_regs = {
  18         .set_ofs = 0x30,
  19         .clr_ofs = 0x30,
  20         .sta_ofs = 0x30,
  21 };
  22
  23 #define GATE_ETHDMA(_id, _name, _parent, _shift)                              \
  24         {                                                                     \
  25                 .id = _id, .name = _name, .parent_name = _parent,             \
  26                 .regs = &ethdma_cg_regs, .shift = _shift,                     \
  27                 .ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
  28         }
  29
  30 static const struct mtk_gate ethdma_clks[] = {
  31         GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
  32         GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
  33         GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
  34         GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
  35         GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
  36         GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
  37         GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
  38         GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
  39         GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
  40                     29),
  41 };
  42
  43 static const struct mtk_clk_desc ethdma_desc = {
  44         .clks = ethdma_clks,
  45         .num_clks = ARRAY_SIZE(ethdma_clks),
  46 };
  47
  48 static const struct mtk_gate_regs sgmii0_cg_regs = {
  49         .set_ofs = 0xe4,
  50         .clr_ofs = 0xe4,
  51         .sta_ofs = 0xe4,
  52 };
  53
  54 #define GATE_SGMII0(_id, _name, _parent, _shift)                              \
  55         {                                                                     \
  56                 .id = _id, .name = _name, .parent_name = _parent,             \
  57                 .regs = &sgmii0_cg_regs, .shift = _shift,                     \
  58                 .ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
  59         }
  60
  61 static const struct mtk_gate sgmii0_clks[] = {
  62         GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
  63         GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
  64 };
  65
  66 static const struct mtk_clk_desc sgmii0_desc = {
  67         .clks = sgmii0_clks,
  68         .num_clks = ARRAY_SIZE(sgmii0_clks),
  69 };
  70
  71 static const struct mtk_gate_regs sgmii1_cg_regs = {
  72         .set_ofs = 0xe4,
  73         .clr_ofs = 0xe4,
  74         .sta_ofs = 0xe4,
  75 };
  76
  77 #define GATE_SGMII1(_id, _name, _parent, _shift)                              \
  78         {                                                                     \
  79                 .id = _id, .name = _name, .parent_name = _parent,             \
  80                 .regs = &sgmii1_cg_regs, .shift = _shift,                     \
  81                 .ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
  82         }
  83
  84 static const struct mtk_gate sgmii1_clks[] = {
  85         GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
  86         GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
  87 };
  88
  89 static const struct mtk_clk_desc sgmii1_desc = {
  90         .clks = sgmii1_clks,
  91         .num_clks = ARRAY_SIZE(sgmii1_clks),
  92 };
  93
  94 static const struct mtk_gate_regs ethwarp_cg_regs = {
  95         .set_ofs = 0x14,
  96         .clr_ofs = 0x14,
  97         .sta_ofs = 0x14,
  98 };
  99
 100 #define GATE_ETHWARP(_id, _name, _parent, _shift)                             \
 101         {                                                                     \
 102                 .id = _id, .name = _name, .parent_name = _parent,             \
 103                 .regs = &ethwarp_cg_regs, .shift = _shift,                    \
 104                 .ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
 105         }
 106
 107 static const struct mtk_gate ethwarp_clks[] = {
 108         GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
 109                      "netsys_mcu_sel", 13),
 110         GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
 111                      "netsys_mcu_sel", 14),
 112         GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
 113                      "netsys_mcu_sel", 15),
 114 };
 115
 116 static const struct mtk_clk_desc ethwarp_desc = {
 117         .clks = ethwarp_clks,
 118         .num_clks = ARRAY_SIZE(ethwarp_clks),
 119 };
 120
 121 static const struct of_device_id of_match_clk_mt7986_eth[] = {
 122         { .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
 123         { .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc },
 124         { .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc },
 125         { .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
 126         { /* sentinel */ }
 127 };
 128 MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
 129
 130 static struct platform_driver clk_mt7988_eth_drv = {
 131         .driver = {
 132                 .name = "clk-mt7988-eth",
 133                 .of_match_table = of_match_clk_mt7986_eth,
 134         },
 135         .probe = mtk_clk_simple_probe,
 136         .remove = mtk_clk_simple_remove,
 137 };
 138 module_platform_driver(clk_mt7988_eth_drv);
 139
 140 MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
 141 MODULE_LICENSE("GPL");