target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2023 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include "clk-mtk.h"
  14 #include "clk-gate.h"
  15 #include "clk-mux.h"
  16 #include "clk-pll.h"
  17 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
  18
  19 #define MT7988_PLL_FMAX (2500UL * MHZ)
  20 #define MT7988_PCW_CHG_SHIFT 2
  21
  22 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
  23                  _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
  24                  _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg,           \
  25                  _div_table)                                                  \
  26         {                                                                     \
  27                 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,   \
  28                 .en_mask = _en_mask, .flags = _flags,                         \
  29                 .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX,  \
  30                 .pcwbits = _pcwbits, .pd_reg = _pd_reg,                       \
  31                 .pd_shift = _pd_shift, .tuner_reg = _tuner_reg,               \
  32                 .tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
  33                 .pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift,                 \
  34                 .pcw_chg_reg = _pcw_chg_reg,                                  \
  35                 .pcw_chg_shift = MT7988_PCW_CHG_SHIFT,                        \
  36                 .div_table = _div_table, .parent_name = "clkxtal",            \
  37         }
  38
  39 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,      \
  40             _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,          \
  41             _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg)                \
  42         PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
  43                  _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
  44                  _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
  45
  46 static const struct mtk_pll_data plls[] = {
  47         PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
  48             0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
  49         PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
  50             23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
  51         PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
  52             HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
  53         PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
  54             0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
  55         PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
  56             HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
  57         PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
  58             (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
  59             0x0154),
  60         PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
  61             0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
  62         PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
  63             0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
  64         PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
  65             (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
  66             0x0204),
  67         PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
  68             HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
  69         PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
  70             HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
  71         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
  72             32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
  73 };
  74
  75 static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
  76         { .compatible = "mediatek,mt7988-apmixedsys", },
  77         { /* sentinel */ }
  78 };
  79
  80 static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
  81 {
  82         struct clk_hw_onecell_data *clk_data;
  83         struct device_node *node = pdev->dev.of_node;
  84         int r;
  85
  86         clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
  87         if (!clk_data)
  88                 return -ENOMEM;
  89
  90         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  91
  92         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  93         if (r) {
  94                 pr_err("%s(): could not register clock provider: %d\n",
  95                        __func__, r);
  96                 goto free_apmixed_data;
  97         }
  98         return r;
  99
 100 free_apmixed_data:
 101         mtk_free_clk_data(clk_data);
 102         return r;
 103 }
 104
 105 static struct platform_driver clk_mt7988_apmixed_drv = {
 106         .probe = clk_mt7988_apmixed_probe,
 107         .driver = {
 108                 .name = "clk-mt7988-apmixed",
 109                 .of_match_table = of_match_clk_mt7988_apmixed,
 110         },
 111 };
 112 builtin_platform_driver(clk_mt7988_apmixed_drv);
 113 MODULE_LICENSE("GPL");