target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2023 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/pinctrl/mt65xx.h>
  13 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15
  16 /* TOPRGU resets */
  17 #define MT7988_TOPRGU_SGMII0_GRST               1
  18 #define MT7988_TOPRGU_SGMII1_GRST               2
  19 #define MT7988_TOPRGU_XFI0_GRST                 12
  20 #define MT7988_TOPRGU_XFI1_GRST                 13
  21 #define MT7988_TOPRGU_XFI_PEXTP0_GRST           14
  22 #define MT7988_TOPRGU_XFI_PEXTP1_GRST           15
  23 #define MT7988_TOPRGU_XFI_PLL_GRST              16
  24
  25 / {
  26         compatible = "mediatek,mt7988";
  27         interrupt-parent = <&gic>;
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         cci: cci {
  32                 compatible = "mediatek,mt7988-cci",
  33                              "mediatek,mt8183-cci";
  34                 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
  35                          <&topckgen CLK_TOP_XTAL>;
  36                 clock-names = "cci", "intermediate";
  37                 operating-points-v2 = <&cci_opp>;
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 cpu0: cpu@0 {
  45                         compatible = "arm,cortex-a73";
  46                         reg = <0x0>;
  47                         device_type = "cpu";
  48                         enable-method = "psci";
  49                         clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
  50                                  <&topckgen CLK_TOP_XTAL>;
  51                         clock-names = "cpu", "intermediate";
  52                         operating-points-v2 = <&cluster0_opp>;
  53                         mediatek,cci = <&cci>;
  54                 };
  55
  56                 cpu1: cpu@1 {
  57                         compatible = "arm,cortex-a73";
  58                         reg = <0x1>;
  59                         device_type = "cpu";
  60                         enable-method = "psci";
  61                         clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
  62                                  <&topckgen CLK_TOP_XTAL>;
  63                         clock-names = "cpu", "intermediate";
  64                         operating-points-v2 = <&cluster0_opp>;
  65                         mediatek,cci = <&cci>;
  66                 };
  67
  68                 cpu2: cpu@2 {
  69                         compatible = "arm,cortex-a73";
  70                         reg = <0x2>;
  71                         device_type = "cpu";
  72                         enable-method = "psci";
  73                         clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
  74                                  <&topckgen CLK_TOP_XTAL>;
  75                         clock-names = "cpu", "intermediate";
  76                         operating-points-v2 = <&cluster0_opp>;
  77                         mediatek,cci = <&cci>;
  78                 };
  79
  80                 cpu3: cpu@3 {
  81                         compatible = "arm,cortex-a73";
  82                         reg = <0x3>;
  83                         device_type = "cpu";
  84                         enable-method = "psci";
  85                         clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
  86                                  <&topckgen CLK_TOP_XTAL>;
  87                         clock-names = "cpu", "intermediate";
  88                         operating-points-v2 = <&cluster0_opp>;
  89                         mediatek,cci = <&cci>;
  90                 };
  91
  92                 cluster0_opp: opp_table0 {
  93                         compatible = "operating-points-v2";
  94                         opp-shared;
  95
  96                         opp00 {
  97                                 opp-hz = /bits/ 64 <800000000>;
  98                                 opp-microvolt = <850000>;
  99                         };
 100
 101                         opp01 {
 102                                 opp-hz = /bits/ 64 <1100000000>;
 103                                 opp-microvolt = <850000>;
 104                         };
 105
 106                         opp02 {
 107                                 opp-hz = /bits/ 64 <1500000000>;
 108                                 opp-microvolt = <850000>;
 109                         };
 110
 111                         opp03 {
 112                                 opp-hz = /bits/ 64 <1800000000>;
 113                                 opp-microvolt = <900000>;
 114                         };
 115                 };
 116         };
 117
 118         cci_opp: opp_table_cci {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121
 122                 opp00 {
 123                         opp-hz = /bits/ 64 <480000000>;
 124                         opp-microvolt = <850000>;
 125                 };
 126
 127                 opp01 {
 128                         opp-hz = /bits/ 64 <660000000>;
 129                         opp-microvolt = <850000>;
 130                 };
 131
 132                 opp02 {
 133                         opp-hz = /bits/ 64 <900000000>;
 134                         opp-microvolt = <850000>;
 135                 };
 136
 137                 opp03 {
 138                         opp-hz = /bits/ 64 <1080000000>;
 139                         opp-microvolt = <900000>;
 140                 };
 141         };
 142
 143         clk40m: oscillator@0 {
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <40000000>;
 146                 #clock-cells = <0>;
 147                 clock-output-names = "clkxtal";
 148         };
 149
 150         fan: pwm-fan {
 151                 compatible = "pwm-fan";
 152                 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
 153                 cooling-levels = <0 128 255>;
 154                 #cooling-cells = <2>;
 155                 #thermal-sensor-cells = <1>;
 156                 status = "disabled";
 157         };
 158
 159         pmu {
 160                 compatible = "arm,cortex-a73-pmu";
 161                 interrupt-parent = <&gic>;
 162                 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 163         };
 164
 165         psci {
 166                 compatible = "arm,psci-0.2";
 167                 method = "smc";
 168         };
 169
 170         reg_1p8v: regulator-1p8v {
 171                 compatible = "regulator-fixed";
 172                 regulator-name = "fixed-1.8V";
 173                 regulator-min-microvolt = <1800000>;
 174                 regulator-max-microvolt = <1800000>;
 175                 regulator-boot-on;
 176                 regulator-always-on;
 177         };
 178
 179         reg_3p3v: regulator-3p3v {
 180                 compatible = "regulator-fixed";
 181                 regulator-name = "fixed-3.3V";
 182                 regulator-min-microvolt = <3300000>;
 183                 regulator-max-microvolt = <3300000>;
 184                 regulator-boot-on;
 185                 regulator-always-on;
 186         };
 187
 188         reserved-memory {
 189                 ranges;
 190                 #address-cells = <2>;
 191                 #size-cells = <2>;
 192
 193                 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
 194                 secmon_reserved: secmon@43000000 {
 195                         reg = <0 0x43000000 0 0x50000>;
 196                         no-map;
 197                 };
 198         };
 199
 200         soc {
 201                 compatible = "simple-bus";
 202                 ranges;
 203                 #address-cells = <2>;
 204                 #size-cells = <2>;
 205
 206                 gic: interrupt-controller@c000000 {
 207                         compatible = "arm,gic-v3";
 208                         reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 209                               <0 0x0c080000 0 0x200000>, /* GICR */
 210                               <0 0x0c400000 0 0x2000>,   /* GICC */
 211                               <0 0x0c410000 0 0x1000>,   /* GICH */
 212                               <0 0x0c420000 0 0x2000>;   /* GICV */
 213                         interrupt-parent = <&gic>;
 214                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <3>;
 217                 };
 218
 219                 phyfw: phy-firmware@f000000 {
 220                         compatible = "mediatek,2p5gphy-fw";
 221                         reg = <0 0x0f100000 0 0x20000>,
 222                               <0 0x0f0f0018 0 0x20>;
 223                 };
 224
 225                 infracfg: infracfg@10001000 {
 226                         compatible = "mediatek,mt7988-infracfg", "syscon";
 227                         reg = <0 0x10001000 0 0x1000>;
 228                         #clock-cells = <1>;
 229                         #reset-cells = <1>;
 230                 };
 231
 232                 topckgen: topckgen@1001b000 {
 233                         compatible = "mediatek,mt7988-topckgen", "syscon";
 234                         reg = <0 0x1001b000 0 0x1000>;
 235                         #clock-cells = <1>;
 236                 };
 237
 238                 watchdog: watchdog@1001c000 {
 239                         compatible = "mediatek,mt7988-wdt",
 240                                      "mediatek,mt6589-wdt",
 241                                      "syscon";
 242                         reg = <0 0x1001c000 0 0x1000>;
 243                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 244                         #reset-cells = <1>;
 245                 };
 246
 247                 apmixedsys: apmixedsys@1001e000 {
 248                         compatible = "mediatek,mt7988-apmixedsys";
 249                         reg = <0 0x1001e000 0 0x1000>;
 250                         #clock-cells = <1>;
 251                 };
 252
 253                 pio: pinctrl@1001f000 {
 254                         compatible = "mediatek,mt7988-pinctrl", "syscon";
 255                         reg = <0 0x1001f000 0 0x1000>,
 256                               <0 0x11c10000 0 0x1000>,
 257                               <0 0x11d00000 0 0x1000>,
 258                               <0 0x11d20000 0 0x1000>,
 259                               <0 0x11e00000 0 0x1000>,
 260                               <0 0x11f00000 0 0x1000>,
 261                               <0 0x1000b000 0 0x1000>;
 262                         reg-names = "gpio_base", "iocfg_tr_base",
 263                                     "iocfg_br_base", "iocfg_rb_base",
 264                                     "iocfg_lb_base", "iocfg_tl_base", "eint";
 265                         gpio-controller;
 266                         #gpio-cells = <2>;
 267                         gpio-ranges = <&pio 0 0 84>;
 268                         interrupt-controller;
 269                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 270                         interrupt-parent = <&gic>;
 271                         #interrupt-cells = <2>;
 272
 273                         mdio0_pins: mdio0-pins {
 274                                 mux {
 275                                         function = "eth";
 276                                         groups = "mdc_mdio0";
 277                                 };
 278
 279                                 conf {
 280                                         groups = "mdc_mdio0";
 281                                         drive-strength = <MTK_DRIVE_8mA>;
 282                                 };
 283                         };
 284
 285                         i2c0_pins: i2c0-pins-g0 {
 286                                 mux {
 287                                         function = "i2c";
 288                                         groups = "i2c0_1";
 289                                 };
 290                         };
 291
 292                         i2c1_pins: i2c1-pins-g0 {
 293                                 mux {
 294                                         function = "i2c";
 295                                         groups = "i2c1_0";
 296                                 };
 297                         };
 298
 299                         i2c1_sfp_pins: i2c1-sfp-pins-g0 {
 300                                 mux {
 301                                         function = "i2c";
 302                                         groups = "i2c1_sfp";
 303                                 };
 304                         };
 305
 306                         i2c2_pins: i2c2-pins {
 307                                 mux {
 308                                         function = "i2c";
 309                                         groups = "i2c2";
 310                                 };
 311                         };
 312
 313                         i2c2_0_pins: i2c2-pins-g0 {
 314                                 mux {
 315                                         function = "i2c";
 316                                         groups = "i2c2_0";
 317                                 };
 318                         };
 319
 320                         i2c2_1_pins: i2c2-pins-g1 {
 321                                 mux {
 322                                         function = "i2c";
 323                                         groups = "i2c2_1";
 324                                 };
 325                         };
 326
 327                         gbe0_led0_pins: gbe0-led0-pins {
 328                                 mux {
 329                                         function = "led";
 330                                         groups = "gbe0_led0";
 331                                 };
 332                         };
 333
 334                         gbe1_led0_pins: gbe1-led0-pins {
 335                                 mux {
 336                                         function = "led";
 337                                         groups = "gbe1_led0";
 338                                 };
 339                         };
 340
 341                         gbe2_led0_pins: gbe2-led0-pins {
 342                                 mux {
 343                                         function = "led";
 344                                         groups = "gbe2_led0";
 345                                 };
 346                         };
 347
 348                         gbe3_led0_pins: gbe3-led0-pins {
 349                                 mux {
 350                                         function = "led";
 351                                         groups = "gbe3_led0";
 352                                 };
 353                         };
 354
 355                         gbe0_led1_pins: gbe0-led1-pins {
 356                                 mux {
 357                                         function = "led";
 358                                         groups = "gbe0_led1";
 359                                 };
 360                         };
 361
 362                         gbe1_led1_pins: gbe1-led1-pins {
 363                                 mux {
 364                                         function = "led";
 365                                         groups = "gbe1_led1";
 366                                 };
 367                         };
 368
 369                         gbe2_led1_pins: gbe2-led1-pins {
 370                                 mux {
 371                                         function = "led";
 372                                         groups = "gbe2_led1";
 373                                 };
 374                         };
 375
 376                         gbe3_led1_pins: gbe3-led1-pins {
 377                                 mux {
 378                                         function = "led";
 379                                         groups = "gbe3_led1";
 380                                 };
 381                         };
 382
 383                         i2p5gbe_led0_pins: 2p5gbe-led0-pins {
 384                                 mux {
 385                                         function = "led";
 386                                         groups = "2p5gbe_led0";
 387                                 };
 388                         };
 389
 390                         i2p5gbe_led1_pins: 2p5gbe-led1-pins {
 391                                 mux {
 392                                         function = "led";
 393                                         groups = "2p5gbe_led1";
 394                                 };
 395                         };
 396
 397                         mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
 398                                 mux {
 399                                         function = "flash";
 400                                         groups = "emmc_45";
 401                                 };
 402                         };
 403
 404                         mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
 405                                 mux {
 406                                         function = "flash";
 407                                         groups = "emmc_51";
 408                                 };
 409                         };
 410
 411                         mmc0_pins_sdcard: mmc0-pins-sdcard {
 412                                 mux {
 413                                         function = "flash";
 414                                         groups = "sdcard";
 415                                 };
 416                         };
 417
 418                         uart0_pins: uart0-pins {
 419                                 mux {
 420                                         function = "uart";
 421                                         groups =  "uart0";
 422                                 };
 423                         };
 424
 425                         uart1_0_pins: uart1-0-pins {
 426                                 mux {
 427                                         function = "uart";
 428                                         groups =  "uart1_0";
 429                                 };
 430                         };
 431
 432                         uart1_1_pins: uart1-1-pins {
 433                                 mux {
 434                                         function = "uart";
 435                                         groups =  "uart1_1";
 436                                 };
 437                         };
 438
 439                         uart1_2_pins: uart1-2-pins {
 440                                 mux {
 441                                         function = "uart";
 442                                         groups =  "uart1_2";
 443                                 };
 444                         };
 445
 446                         uart1_2_lite_pins: uart1-2-lite-pins {
 447                                 mux {
 448                                         function = "uart";
 449                                         groups =  "uart1_2_lite";
 450                                 };
 451                         };
 452
 453                         uart2_pins: uart2-pins {
 454                                 mux {
 455                                         function = "uart";
 456                                         groups =  "uart2";
 457                                 };
 458                         };
 459
 460                         uart2_0_pins: uart2-0-pins {
 461                                 mux {
 462                                         function = "uart";
 463                                         groups =  "uart2_0";
 464                                 };
 465                         };
 466
 467                         uart2_1_pins: uart2-1-pins {
 468                                 mux {
 469                                         function = "uart";
 470                                         groups =  "uart2_1";
 471                                 };
 472                         };
 473
 474                         uart2_2_pins: uart2-2-pins {
 475                                 mux {
 476                                         function = "uart";
 477                                         groups =  "uart2_2";
 478                                 };
 479                         };
 480
 481                         uart2_3_pins: uart2-3-pins {
 482                                 mux {
 483                                         function = "uart";
 484                                         groups =  "uart2_3";
 485                                 };
 486                         };
 487
 488                         snfi_pins: snfi-pins {
 489                                 mux {
 490                                         function = "flash";
 491                                         groups = "snfi";
 492                                 };
 493                         };
 494
 495                         spi0_pins: spi0-pins {
 496                                 mux {
 497                                         function = "spi";
 498                                         groups = "spi0";
 499                                 };
 500                         };
 501
 502                         spi0_flash_pins: spi0-flash-pins {
 503                                 mux {
 504                                         function = "spi";
 505                                         groups = "spi0", "spi0_wp_hold";
 506                                 };
 507                         };
 508
 509                         spi1_pins: spi1-pins {
 510                                 mux {
 511                                         function = "spi";
 512                                         groups = "spi1";
 513                                 };
 514                         };
 515
 516                         spi2_pins: spi2-pins {
 517                                 mux {
 518                                         function = "spi";
 519                                         groups = "spi2";
 520                                 };
 521                         };
 522
 523                         spi2_flash_pins: spi2-flash-pins {
 524                                 mux {
 525                                         function = "spi";
 526                                         groups = "spi2", "spi2_wp_hold";
 527                                 };
 528                         };
 529
 530                         pcie0_pins: pcie0-pins {
 531                                 mux {
 532                                         function = "pcie";
 533                                         groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
 534                                                  "pcie_wake_n0_0";
 535                                 };
 536                         };
 537
 538                         pcie1_pins: pcie1-pins {
 539                                 mux {
 540                                         function = "pcie";
 541                                         groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
 542                                                  "pcie_wake_n1_0";
 543                                 };
 544                         };
 545
 546                         pcie2_pins: pcie2-pins {
 547                                 mux {
 548                                         function = "pcie";
 549                                         groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
 550                                                  "pcie_wake_n2_0";
 551                                 };
 552                         };
 553
 554                         pcie3_pins: pcie3-pins {
 555                                 mux {
 556                                         function = "pcie";
 557                                         groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
 558                                                  "pcie_wake_n3_0";
 559                                 };
 560                         };
 561                 };
 562
 563                 pwm: pwm@10048000 {
 564                         compatible = "mediatek,mt7988-pwm";
 565                         reg = <0 0x10048000 0 0x1000>;
 566                         #pwm-cells = <2>;
 567                         clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
 568                                  <&infracfg CLK_INFRA_66M_PWM_HCK>,
 569                                  <&infracfg CLK_INFRA_66M_PWM_CK1>,
 570                                  <&infracfg CLK_INFRA_66M_PWM_CK2>,
 571                                  <&infracfg CLK_INFRA_66M_PWM_CK3>,
 572                                  <&infracfg CLK_INFRA_66M_PWM_CK4>,
 573                                  <&infracfg CLK_INFRA_66M_PWM_CK5>,
 574                                  <&infracfg CLK_INFRA_66M_PWM_CK6>,
 575                                  <&infracfg CLK_INFRA_66M_PWM_CK7>,
 576                                  <&infracfg CLK_INFRA_66M_PWM_CK8>;
 577                         clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
 578                                       "pwm4","pwm5","pwm6","pwm7","pwm8";
 579                         status = "disabled";
 580                 };
 581
 582                 sgmiisys0: syscon@10060000 {
 583                         compatible = "mediatek,mt7988-sgmiisys",
 584                                      "mediatek,mt7988-sgmiisys0",
 585                                      "syscon",
 586                                      "simple-mfd";
 587                         reg = <0 0x10060000 0 0x1000>;
 588                         resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
 589                         #clock-cells = <1>;
 590
 591                         sgmiipcs0: pcs {
 592                                 compatible = "mediatek,mt7988-sgmii";
 593                                 clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
 594                                          <&sgmiisys0 CLK_SGM0_TX_EN>,
 595                                          <&sgmiisys0 CLK_SGM0_RX_EN>;
 596                                 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
 597                         };
 598                 };
 599
 600                 sgmiisys1: syscon@10070000 {
 601                         compatible = "mediatek,mt7988-sgmiisys",
 602                                      "mediatek,mt7988-sgmiisys1",
 603                                      "syscon",
 604                                      "simple-mfd";
 605                         reg = <0 0x10070000 0 0x1000>;
 606                         resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
 607                         #clock-cells = <1>;
 608
 609                         sgmiipcs1: pcs {
 610                                 compatible = "mediatek,mt7988-sgmii";
 611                                 clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
 612                                          <&sgmiisys1 CLK_SGM1_TX_EN>,
 613                                          <&sgmiisys1 CLK_SGM1_RX_EN>;
 614                                 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
 615                         };
 616                 };
 617
 618                 usxgmiisys0: pcs@10080000 {
 619                         compatible = "mediatek,mt7988-usxgmiisys";
 620                         reg = <0 0x10080000 0 0x1000>;
 621                         resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
 622                         clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
 623                 };
 624
 625                 usxgmiisys1: pcs@10081000 {
 626                         compatible = "mediatek,mt7988-usxgmiisys";
 627                         reg = <0 0x10081000 0 0x1000>;
 628                         resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
 629                         clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
 630                 };
 631
 632                 mcusys: mcusys@100e0000 {
 633                         compatible = "mediatek,mt7988-mcusys", "syscon";
 634                         reg = <0 0x100e0000 0 0x1000>;
 635                         #clock-cells = <1>;
 636                 };
 637
 638                 uart0: serial@11000000 {
 639                         compatible = "mediatek,mt7986-uart",
 640                                      "mediatek,mt6577-uart";
 641                         reg = <0 0x11000000 0 0x100>;
 642                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 643                         /*
 644                          * 8250-mtk driver don't control "baud" clock since commit
 645                          * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
 646                          * still need to be passed to the driver to prevent probe fail
 647                          */
 648                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 649                                  <&infracfg CLK_INFRA_52M_UART0_CK>;
 650                         clock-names = "baud", "bus";
 651                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 652                                           <&infracfg CLK_INFRA_MUX_UART0_SEL>;
 653                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 654                                                  <&topckgen CLK_TOP_UART_SEL>;
 655                         pinctrl-names = "default";
 656                         pinctrl-0 = <&uart0_pins>;
 657                         status = "disabled";
 658                 };
 659
 660                 uart1: serial@11000100 {
 661                         compatible = "mediatek,mt7986-uart",
 662                                      "mediatek,mt6577-uart";
 663                         reg = <0 0x11000100 0 0x100>;
 664                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 665                         /*
 666                          * 8250-mtk driver don't control "baud" clock since commit
 667                          * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
 668                          * still need to be passed to the driver to prevent probe fail
 669                          */
 670                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 671                                  <&infracfg CLK_INFRA_52M_UART1_CK>;
 672                         clock-names = "baud", "bus";
 673                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 674                                           <&infracfg CLK_INFRA_MUX_UART1_SEL>;
 675                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 676                                                  <&topckgen CLK_TOP_UART_SEL>;
 677                         status = "disabled";
 678                 };
 679
 680                 uart2: serial@11000200 {
 681                         compatible = "mediatek,mt7986-uart",
 682                                      "mediatek,mt6577-uart";
 683                         reg = <0 0x11000200 0 0x100>;
 684                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 685                         /*
 686                          * 8250-mtk driver don't control "baud" clock since commit
 687                          * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
 688                          * still need to be passed to the driver to prevent probe fail
 689                          */
 690                         clocks = <&topckgen CLK_TOP_UART_SEL>,
 691                                  <&infracfg CLK_INFRA_52M_UART2_CK>;
 692                         clock-names = "baud", "bus";
 693                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 694                                           <&infracfg CLK_INFRA_MUX_UART2_SEL>;
 695                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 696                                                  <&topckgen CLK_TOP_UART_SEL>;
 697                         status = "disabled";
 698                 };
 699
 700                 snand: spi@11001000 {
 701                         compatible = "mediatek,mt7986-snand";
 702                         reg = <0 0x11001000 0 0x1000>;
 703                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 704                         clocks = <&infracfg CLK_INFRA_SPINFI>,
 705                                  <&infracfg CLK_INFRA_NFI>;
 706                         clock-names = "pad_clk", "nfi_clk";
 707                         assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
 708                                           <&topckgen CLK_TOP_NFI1X_SEL>;
 709                         assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
 710                                                  <&topckgen CLK_TOP_MPLL_D8>;
 711                         nand-ecc-engine = <&bch>;
 712                         mediatek,quad-spi;
 713                         #address-cells = <1>;
 714                         #size-cells = <0>;
 715                         pinctrl-names = "default";
 716                         pinctrl-0 = <&snfi_pins>;
 717                         status = "disabled";
 718                 };
 719
 720                 bch: ecc@11002000 {
 721                         compatible = "mediatek,mt7686-ecc";
 722                         reg = <0 0x11002000 0 0x1000>;
 723                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
 725                         clock-names = "nfiecc_clk";
 726                         status = "disabled";
 727                 };
 728
 729                 i2c0: i2c@11003000 {
 730                         compatible = "mediatek,mt7988-i2c",
 731                                      "mediatek,mt7981-i2c";
 732                         reg = <0 0x11003000 0 0x1000>,
 733                               <0 0x10217080 0 0x80>;
 734                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 735                         clock-div = <1>;
 736                         clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 737                                  <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 738                         clock-names = "main", "dma";
 739                         #address-cells = <1>;
 740                         #size-cells = <0>;
 741                         status = "disabled";
 742                 };
 743
 744                 i2c1: i2c@11004000 {
 745                         compatible = "mediatek,mt7988-i2c",
 746                                      "mediatek,mt7981-i2c";
 747                         reg = <0 0x11004000 0 0x1000>,
 748                               <0 0x10217100 0 0x80>;
 749                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 750                         clock-div = <1>;
 751                         clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 752                                  <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 753                         clock-names = "main", "dma";
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         status = "disabled";
 757                 };
 758
 759                 i2c2: i2c@11005000 {
 760                         compatible = "mediatek,mt7988-i2c",
 761                                 "mediatek,mt7981-i2c";
 762                         reg = <0 0x11005000 0 0x1000>,
 763                               <0 0x10217180 0 0x80>;
 764                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 765                         clock-div = <1>;
 766                         clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 767                                  <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 768                         clock-names = "main", "dma";
 769                         #address-cells = <1>;
 770                         #size-cells = <0>;
 771                         status = "disabled";
 772                 };
 773
 774                 spi0: spi@11007000 {
 775                         compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
 776                         reg = <0 0x11007000 0 0x100>;
 777                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 778                         clocks = <&topckgen CLK_TOP_MPLL_D2>,
 779                                  <&topckgen CLK_TOP_SPI_SEL>,
 780                                  <&infracfg CLK_INFRA_104M_SPI0>,
 781                                  <&infracfg CLK_INFRA_66M_SPI0_HCK>;
 782                         clock-names = "parent-clk", "sel-clk", "spi-clk",
 783                                       "spi-hclk";
 784                         #address-cells = <1>;
 785                         #size-cells = <0>;
 786                         status = "disabled";
 787                 };
 788
 789                 spi1: spi@11008000 {
 790                         compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
 791                         reg = <0 0x11008000 0 0x100>;
 792                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 793                         clocks = <&topckgen CLK_TOP_MPLL_D2>,
 794                                  <&topckgen CLK_TOP_SPI_SEL>,
 795                                  <&infracfg CLK_INFRA_104M_SPI1>,
 796                                  <&infracfg CLK_INFRA_66M_SPI1_HCK>;
 797                         clock-names = "parent-clk", "sel-clk", "spi-clk",
 798                                       "spi-hclk";
 799                         #address-cells = <1>;
 800                         #size-cells = <0>;
 801                         pinctrl-names = "default";
 802                         pinctrl-0 = <&spi1_pins>;
 803                         status = "disabled";
 804                 };
 805
 806                 spi2: spi@11009000 {
 807                         compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
 808                         reg = <0 0x11009000 0 0x100>;
 809                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 810                         clocks = <&topckgen CLK_TOP_MPLL_D2>,
 811                                  <&topckgen CLK_TOP_SPI_SEL>,
 812                                  <&infracfg CLK_INFRA_104M_SPI2_BCK>,
 813                                  <&infracfg CLK_INFRA_66M_SPI2_HCK>;
 814                         clock-names = "parent-clk", "sel-clk", "spi-clk",
 815                                       "spi-hclk";
 816                         #address-cells = <1>;
 817                         #size-cells = <0>;
 818                         status = "disabled";
 819                 };
 820
 821                 lvts: lvts@1100a000 {
 822                         compatible = "mediatek,mt7988-lvts-ap";
 823                         reg = <0 0x1100a000 0 0x1000>;
 824                         clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
 825                         clock-names = "lvts_clk";
 826                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 827                         resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
 828                         nvmem-cells = <&lvts_calibration>;
 829                         nvmem-cell-names = "lvts-calib-data-1";
 830                         #thermal-sensor-cells = <1>;
 831                 };
 832
 833                 ssusb0: usb@11190000 {
 834                         compatible = "mediatek,mt7988-xhci",
 835                                      "mediatek,mtk-xhci";
 836                         reg = <0 0x11190000 0 0x2e00>,
 837                               <0 0x11193e00 0 0x0100>;
 838                         reg-names = "mac", "ippc";
 839                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 840                         phys = <&xphyu2port0 PHY_TYPE_USB2>,
 841                                <&xphyu3port0 PHY_TYPE_USB3>;
 842                         clocks = <&infracfg CLK_INFRA_USB_SYS>,
 843                                  <&infracfg CLK_INFRA_USB_XHCI>,
 844                                  <&infracfg CLK_INFRA_USB_REF>,
 845                                  <&infracfg CLK_INFRA_66M_USB_HCK>,
 846                                  <&infracfg CLK_INFRA_133M_USB_HCK>;
 847                         clock-names = "sys_ck",
 848                                       "xhci_ck",
 849                                       "ref_ck",
 850                                       "mcu_ck",
 851                                       "dma_ck";
 852                         #address-cells = <2>;
 853                         #size-cells = <2>;
 854                         mediatek,p0_speed_fixup;
 855                         status = "disabled";
 856                 };
 857
 858                 ssusb1: usb@11200000 {
 859                         compatible = "mediatek,mt7988-xhci",
 860                                      "mediatek,mtk-xhci";
 861                         reg = <0 0x11200000 0 0x2e00>,
 862                               <0 0x11203e00 0 0x0100>;
 863                         reg-names = "mac", "ippc";
 864                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 865                         phys = <&tphyu2port0 PHY_TYPE_USB2>,
 866                                <&tphyu3port0 PHY_TYPE_USB3>;
 867                         clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
 868                                  <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
 869                                  <&infracfg CLK_INFRA_USB_CK_P1>,
 870                                  <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
 871                                  <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
 872                         clock-names = "sys_ck",
 873                                       "xhci_ck",
 874                                       "ref_ck",
 875                                       "mcu_ck",
 876                                       "dma_ck";
 877                         #address-cells = <2>;
 878                         #size-cells = <2>;
 879                         status = "disabled";
 880                 };
 881
 882                 afe: audio-controller@11210000 {
 883                         compatible = "mediatek,mt79xx-audio";
 884                         reg = <0 0x11210000 0 0x9000>;
 885                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 886                         clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
 887                                  <&infracfg CLK_INFRA_AUD_26M>,
 888                                  <&infracfg CLK_INFRA_AUD_L>,
 889                                  <&infracfg CLK_INFRA_AUD_AUD>,
 890                                  <&infracfg CLK_INFRA_AUD_EG2>,
 891                                  <&topckgen CLK_TOP_AUD_SEL>,
 892                                  <&topckgen CLK_TOP_AUD_I2S_M>;
 893                         clock-names = "aud_bus_ck",
 894                                       "aud_26m_ck",
 895                                       "aud_l_ck",
 896                                       "aud_aud_ck",
 897                                       "aud_eg2_ck",
 898                                       "aud_sel",
 899                                       "aud_i2s_m";
 900                         assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
 901                                           <&topckgen CLK_TOP_A1SYS_SEL>,
 902                                           <&topckgen CLK_TOP_AUD_L_SEL>,
 903                                           <&topckgen CLK_TOP_A_TUNER_SEL>;
 904                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
 905                                                  <&topckgen CLK_TOP_APLL2_D4>,
 906                                                  <&apmixedsys CLK_APMIXED_APLL2>,
 907                                                  <&topckgen CLK_TOP_APLL2_D4>;
 908                         status = "disabled";
 909                 };
 910
 911                 mmc0: mmc@11230000 {
 912                         compatible = "mediatek,mt7986-mmc",
 913                                      "mediatek,mt7981-mmc";
 914                         reg = <0 0x11230000 0 0x1000>,
 915                               <0 0x11D60000 0 0x1000>;
 916                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 917                         clocks = <&infracfg CLK_INFRA_MSDC400>,
 918                                  <&infracfg CLK_INFRA_MSDC2_HCK>,
 919                                  <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
 920                                  <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
 921                         assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
 922                                           <&topckgen CLK_TOP_EMMC_400M_SEL>;
 923                         assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
 924                                                  <&apmixedsys CLK_APMIXED_MSDCPLL>;
 925                         clock-names = "source",
 926                                       "hclk",
 927                                       "axi_cg",
 928                                       "ahb_cg";
 929                         #address-cells = <1>;
 930                         #size-cells = <0>;
 931                         status = "disabled";
 932                 };
 933
 934                 pcie2: pcie@11280000 {
 935                         compatible = "mediatek,mt7988-pcie",
 936                                      "mediatek,mt7986-pcie",
 937                                      "mediatek,mt8192-pcie";
 938                         reg = <0 0x11280000 0 0x2000>;
 939                         reg-names = "pcie-mac";
 940                         ranges = <0x81000000 0x00 0x20000000 0x00
 941                                   0x20000000 0x00 0x00200000>,
 942                                  <0x82000000 0x00 0x20200000 0x00
 943                                   0x20200000 0x00 0x07e00000>;
 944                         device_type = "pci";
 945                         linux,pci-domain = <3>;
 946                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 947                         bus-range = <0x00 0xff>;
 948                         clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
 949                                  <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
 950                                  <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
 951                                  <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
 952                         clock-names = "pl_250m", "tl_26m", "peri_26m",
 953                                       "top_133m";
 954                         pinctrl-names = "default";
 955                         pinctrl-0 = <&pcie2_pins>;
 956                         phys = <&xphyu3port0 PHY_TYPE_PCIE>;
 957                         phy-names = "pcie-phy";
 958                         #interrupt-cells = <1>;
 959                         interrupt-map-mask = <0 0 0 0x7>;
 960                         interrupt-map = <0 0 0 1 &pcie_intc2 0>,
 961                                         <0 0 0 2 &pcie_intc2 1>,
 962                                         <0 0 0 3 &pcie_intc2 2>,
 963                                         <0 0 0 4 &pcie_intc2 3>;
 964                         #address-cells = <3>;
 965                         #size-cells = <2>;
 966                         status = "disabled";
 967
 968                         pcie_intc2: interrupt-controller {
 969                                 #address-cells = <0>;
 970                                 #interrupt-cells = <1>;
 971                                 interrupt-controller;
 972                         };
 973                 };
 974
 975                 pcie3: pcie@11290000 {
 976                         compatible = "mediatek,mt7988-pcie",
 977                                      "mediatek,mt7986-pcie",
 978                                      "mediatek,mt8192-pcie";
 979                         reg = <0 0x11290000 0 0x2000>;
 980                         reg-names = "pcie-mac";
 981                         ranges = <0x81000000 0x00 0x28000000 0x00
 982                                   0x28000000 0x00 0x00200000>,
 983                                  <0x82000000 0x00 0x28200000 0x00
 984                                   0x28200000 0x00 0x07e00000>;
 985                         device_type = "pci";
 986                         linux,pci-domain = <2>;
 987                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 988                         bus-range = <0x00 0xff>;
 989                         clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
 990                                  <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
 991                                  <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
 992                                  <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
 993                         clock-names = "pl_250m", "tl_26m", "peri_26m",
 994                                       "top_133m";
 995                         pinctrl-names = "default";
 996                         pinctrl-0 = <&pcie3_pins>;
 997                         #interrupt-cells = <1>;
 998                         interrupt-map-mask = <0 0 0 0x7>;
 999                         interrupt-map = <0 0 0 1 &pcie_intc3 0>,
1000                                         <0 0 0 2 &pcie_intc3 1>,
1001                                         <0 0 0 3 &pcie_intc3 2>,
1002                                         <0 0 0 4 &pcie_intc3 3>;
1003                         #address-cells = <3>;
1004                         #size-cells = <2>;
1005                         status = "disabled";
1006
1007                         pcie_intc3: interrupt-controller {
1008                                 #address-cells = <0>;
1009                                 #interrupt-cells = <1>;
1010                                 interrupt-controller;
1011                         };
1012                 };
1013
1014                 pcie0: pcie@11300000 {
1015                         compatible = "mediatek,mt7988-pcie",
1016                                      "mediatek,mt7986-pcie",
1017                                      "mediatek,mt8192-pcie";
1018                         reg = <0 0x11300000 0 0x2000>;
1019                         reg-names = "pcie-mac";
1020                         ranges = <0x81000000 0x00 0x30000000 0x00
1021                                   0x30000000 0x00 0x00200000>,
1022                                  <0x82000000 0x00 0x30200000 0x00
1023                                   0x30200000 0x00 0x07e00000>;
1024                         device_type = "pci";
1025                         linux,pci-domain = <0>;
1026                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1027                         bus-range = <0x00 0xff>;
1028                         clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
1029                                  <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
1030                                  <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
1031                                  <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
1032                         clock-names = "pl_250m", "tl_26m", "peri_26m",
1033                                       "top_133m";
1034                         pinctrl-names = "default";
1035                         pinctrl-0 = <&pcie0_pins>;
1036                         #interrupt-cells = <1>;
1037                         interrupt-map-mask = <0 0 0 0x7>;
1038                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1039                                         <0 0 0 2 &pcie_intc0 1>,
1040                                         <0 0 0 3 &pcie_intc0 2>,
1041                                         <0 0 0 4 &pcie_intc0 3>;
1042                         #address-cells = <3>;
1043                         #size-cells = <2>;
1044                         status = "disabled";
1045
1046                         pcie_intc0: interrupt-controller {
1047                                 #address-cells = <0>;
1048                                 #interrupt-cells = <1>;
1049                                 interrupt-controller;
1050                         };
1051                 };
1052
1053                 pcie1: pcie@11310000 {
1054                         compatible = "mediatek,mt7988-pcie",
1055                                      "mediatek,mt7986-pcie",
1056                                      "mediatek,mt8192-pcie";
1057                         reg = <0 0x11310000 0 0x2000>;
1058                         reg-names = "pcie-mac";
1059                         ranges = <0x81000000 0x00 0x38000000 0x00
1060                                   0x38000000 0x00 0x00200000>,
1061                                  <0x82000000 0x00 0x38200000 0x00
1062                                   0x38200000 0x00 0x07e00000>;
1063                         device_type = "pci";
1064                         linux,pci-domain = <1>;
1065                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1066                         bus-range = <0x00 0xff>;
1067                         clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
1068                                  <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
1069                                  <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
1070                                  <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
1071                         clock-names = "pl_250m", "tl_26m", "peri_26m",
1072                                       "top_133m";
1073                         pinctrl-names = "default";
1074                         pinctrl-0 = <&pcie1_pins>;
1075                         #interrupt-cells = <1>;
1076                         interrupt-map-mask = <0 0 0 0x7>;
1077                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1078                                         <0 0 0 2 &pcie_intc1 1>,
1079                                         <0 0 0 3 &pcie_intc1 2>,
1080                                         <0 0 0 4 &pcie_intc1 3>;
1081                         #address-cells = <3>;
1082                         #size-cells = <2>;
1083                         status = "disabled";
1084
1085                         pcie_intc1: interrupt-controller {
1086                                 #address-cells = <0>;
1087                                 #interrupt-cells = <1>;
1088                                 interrupt-controller;
1089                         };
1090                 };
1091
1092                 tphy: tphy@11c50000 {
1093                         compatible = "mediatek,mt7988",
1094                                      "mediatek,generic-tphy-v2";
1095                         ranges;
1096                         #address-cells = <2>;
1097                         #size-cells = <2>;
1098                         status = "disabled";
1099
1100                         tphyu2port0: usb-phy@11c50000 {
1101                                 reg = <0 0x11c50000 0 0x700>;
1102                                 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
1103                                 clock-names = "ref";
1104                                 #phy-cells = <1>;
1105                         };
1106
1107                         tphyu3port0: usb-phy@11c50700 {
1108                                 reg = <0 0x11c50700 0 0x900>;
1109                                 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
1110                                 clock-names = "ref";
1111                                 #phy-cells = <1>;
1112                                 mediatek,usb3-pll-ssc-delta;
1113                                 mediatek,usb3-pll-ssc-delta1;
1114                         };
1115                 };
1116
1117                 topmisc: topmisc@11d10000 {
1118                         compatible = "mediatek,mt7988-topmisc", "syscon",
1119                                      "mediatek,mt7988-power-controller";
1120                         reg = <0 0x11d10000 0 0x10000>;
1121                         #clock-cells = <1>;
1122                         #power-domain-cells = <1>;
1123                         #address-cells = <1>;
1124                         #size-cells = <0>;
1125                 };
1126
1127                 xphy: xphy@11e10000 {
1128                         compatible = "mediatek,mt7988",
1129                                      "mediatek,xsphy";
1130                         ranges;
1131                         #address-cells = <2>;
1132                         #size-cells = <2>;
1133                         status = "disabled";
1134
1135                         xphyu2port0: usb-phy@11e10000 {
1136                                 reg = <0 0x11e10000 0 0x400>;
1137                                 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1138                                 clock-names = "ref";
1139                                 #phy-cells = <1>;
1140                         };
1141
1142                         xphyu3port0: usb-phy@11e13000 {
1143                                 reg = <0 0x11e13400 0 0x500>;
1144                                 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1145                                 clock-names = "ref";
1146                                 #phy-cells = <1>;
1147                                 mediatek,syscon-type = <&topmisc 0x218 0>;
1148                         };
1149                 };
1150
1151                 xfi_tphy0: phy@11f20000 {
1152                         compatible = "mediatek,mt7988-xfi-tphy";
1153                         reg = <0 0x11f20000 0 0x10000>;
1154                         resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
1155                         clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
1156                         clock-names = "xfipll", "topxtal";
1157                         mediatek,usxgmii-performance-errata;
1158                         #phy-cells = <0>;
1159                 };
1160
1161                 xfi_tphy1: phy@11f30000 {
1162                         compatible = "mediatek,mt7988-xfi-tphy";
1163                         reg = <0 0x11f30000 0 0x10000>;
1164                         resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
1165                         clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
1166                         clock-names = "xfipll", "topxtal";
1167                         #phy-cells = <0>;
1168                 };
1169
1170                 xfi_pll: clock-controller@11f40000 {
1171                         compatible = "mediatek,mt7988-xfi-pll";
1172                         reg = <0 0x11f40000 0 0x1000>;
1173                         resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
1174                         #clock-cells = <1>;
1175                 };
1176
1177                 efuse: efuse@11f50000 {
1178                         compatible = "mediatek,efuse";
1179                         reg = <0 0x11f50000 0 0x1000>;
1180                         #address-cells = <1>;
1181                         #size-cells = <1>;
1182
1183                         lvts_calibration: calib@918 {
1184                                 reg = <0x918 0x28>;
1185                         };
1186
1187                         phy_calibration_p0: calib@940 {
1188                                 reg = <0x940 0x10>;
1189                         };
1190
1191                         phy_calibration_p1: calib@954 {
1192                                 reg = <0x954 0x10>;
1193                         };
1194
1195                         phy_calibration_p2: calib@968 {
1196                                 reg = <0x968 0x10>;
1197                         };
1198
1199                         phy_calibration_p3: calib@97c {
1200                                 reg = <0x97c 0x10>;
1201                         };
1202
1203                         cpufreq_calibration: calib@278 {
1204                                 reg = <0x278 0x1>;
1205                         };
1206                 };
1207
1208                 ethsys: syscon@15000000 {
1209                         compatible = "mediatek,mt7988-ethsys", "syscon";
1210                         reg = <0 0x15000000 0 0x1000>;
1211                         #clock-cells = <1>;
1212                         #reset-cells = <1>;
1213                         #address-cells = <1>;
1214                         #size-cells = <1>;
1215                 };
1216
1217                 switch: switch@15020000 {
1218                         compatible = "mediatek,mt7988-switch";
1219                         reg = <0 0x15020000 0 0x8000>;
1220                         interrupt-controller;
1221                         #interrupt-cells = <1>;
1222                         interrupt-parent = <&gic>;
1223                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1224                         resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
1225                         #address-cells = <1>;
1226                         #size-cells = <1>;
1227
1228                         ports {
1229                                 #address-cells = <1>;
1230                                 #size-cells = <0>;
1231
1232                                 gsw_port0: port@0 {
1233                                         reg = <0>;
1234                                         label = "lan0";
1235                                         phy-mode = "internal";
1236                                         phy-handle = <&gsw_phy0>;
1237                                 };
1238
1239                                 gsw_port1: port@1 {
1240                                         reg = <1>;
1241                                         label = "lan1";
1242                                         phy-mode = "internal";
1243                                         phy-handle = <&gsw_phy1>;
1244                                 };
1245
1246                                 gsw_port2: port@2 {
1247                                         reg = <2>;
1248                                         label = "lan2";
1249                                         phy-mode = "internal";
1250                                         phy-handle = <&gsw_phy2>;
1251                                 };
1252
1253                                 gsw_port3: port@3 {
1254                                         reg = <3>;
1255                                         label = "lan3";
1256                                         phy-mode = "internal";
1257                                         phy-handle = <&gsw_phy3>;
1258                                 };
1259
1260                                 port@6 {
1261                                         reg = <6>;
1262                                         ethernet = <&gmac0>;
1263                                         phy-mode = "internal";
1264
1265                                         fixed-link {
1266                                                 speed = <10000>;
1267                                                 full-duplex;
1268                                                 pause;
1269                                         };
1270                                 };
1271                         };
1272
1273                         mdio {
1274                                 #address-cells = <1>;
1275                                 #size-cells = <0>;
1276                                 mediatek,pio = <&pio>;
1277
1278                                 gsw_phy0: ethernet-phy@0 {
1279                                         compatible = "ethernet-phy-ieee802.3-c22";
1280                                         reg = <0>;
1281                                         phy-mode = "internal";
1282                                         nvmem-cells = <&phy_calibration_p0>;
1283                                         nvmem-cell-names = "phy-cal-data";
1284
1285                                         leds {
1286                                                 #address-cells = <1>;
1287                                                 #size-cells = <0>;
1288
1289                                                 gsw_phy0_led0: gsw-phy0-led0@0 {
1290                                                         reg = <0>;
1291                                                         function = LED_FUNCTION_LAN;
1292                                                         status = "disabled";
1293                                                 };
1294
1295                                                 gsw_phy0_led1: gsw-phy0-led1@1 {
1296                                                         reg = <1>;
1297                                                         function = LED_FUNCTION_LAN;
1298                                                         status = "disabled";
1299                                                 };
1300                                         };
1301                                 };
1302
1303                                 gsw_phy1: ethernet-phy@1 {
1304                                         compatible = "ethernet-phy-ieee802.3-c22";
1305                                         reg = <1>;
1306                                         phy-mode = "internal";
1307                                         nvmem-cells = <&phy_calibration_p1>;
1308                                         nvmem-cell-names = "phy-cal-data";
1309
1310                                         leds {
1311                                                 #address-cells = <1>;
1312                                                 #size-cells = <0>;
1313
1314                                                 gsw_phy1_led0: gsw-phy1-led0@0 {
1315                                                         reg = <0>;
1316                                                         function = LED_FUNCTION_LAN;
1317                                                         status = "disabled";
1318                                                 };
1319
1320                                                 gsw_phy1_led1: gsw-phy1-led1@1 {
1321                                                         reg = <1>;
1322                                                         function = LED_FUNCTION_LAN;
1323                                                         status = "disabled";
1324                                                 };
1325                                         };
1326                                 };
1327
1328                                 gsw_phy2: ethernet-phy@2 {
1329                                         compatible = "ethernet-phy-ieee802.3-c22";
1330                                         reg = <2>;
1331                                         phy-mode = "internal";
1332                                         nvmem-cells = <&phy_calibration_p2>;
1333                                         nvmem-cell-names = "phy-cal-data";
1334
1335                                         leds {
1336                                                 #address-cells = <1>;
1337                                                 #size-cells = <0>;
1338
1339                                                 gsw_phy2_led0: gsw-phy2-led0@0 {
1340                                                         reg = <0>;
1341                                                         function = LED_FUNCTION_LAN;
1342                                                         status = "disabled";
1343                                                 };
1344
1345                                                 gsw_phy2_led1: gsw-phy2-led1@1 {
1346                                                         reg = <1>;
1347                                                         function = LED_FUNCTION_LAN;
1348                                                         status = "disabled";
1349                                                 };
1350                                         };
1351                                 };
1352
1353                                 gsw_phy3: ethernet-phy@3 {
1354                                         compatible = "ethernet-phy-ieee802.3-c22";
1355                                         reg = <3>;
1356                                         phy-mode = "internal";
1357                                         nvmem-cells = <&phy_calibration_p3>;
1358                                         nvmem-cell-names = "phy-cal-data";
1359
1360                                         leds {
1361                                                 #address-cells = <1>;
1362                                                 #size-cells = <0>;
1363
1364                                                 gsw_phy3_led0: gsw-phy3-led0@0 {
1365                                                         reg = <0>;
1366                                                         function = LED_FUNCTION_LAN;
1367                                                         status = "disabled";
1368                                                 };
1369
1370                                                 gsw_phy3_led1: gsw-phy3-led1@1 {
1371                                                         reg = <1>;
1372                                                         function = LED_FUNCTION_LAN;
1373                                                         status = "disabled";
1374                                                 };
1375                                         };
1376                                 };
1377                         };
1378                 };
1379
1380                 ethwarp: clock-controller@15031000 {
1381                         compatible = "mediatek,mt7988-ethwarp";
1382                         reg = <0 0x15031000 0 0x1000>;
1383                         #clock-cells = <1>;
1384                         #reset-cells = <1>;
1385                 };
1386
1387                 eth: ethernet@15100000 {
1388                         compatible = "mediatek,mt7988-eth";
1389                         reg = <0 0x15100000 0 0x80000>,
1390                               <0 0x15400000 0 0x380000>;
1391                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1392                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1393                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1394                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1395                         clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1396                                  <&ethsys CLK_ETHDMA_XGP2_EN>,
1397                                  <&ethsys CLK_ETHDMA_XGP3_EN>,
1398                                  <&ethsys CLK_ETHDMA_FE_EN>,
1399                                  <&ethsys CLK_ETHDMA_GP2_EN>,
1400                                  <&ethsys CLK_ETHDMA_GP1_EN>,
1401                                  <&ethsys CLK_ETHDMA_GP3_EN>,
1402                                  <&ethsys CLK_ETHDMA_ESW_EN>,
1403                                  <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1404                                  <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1405                                  <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1406                                  <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1407                                  <&topckgen CLK_TOP_ETH_GMII_SEL>,
1408                                  <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1409                                  <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1410                                  <&topckgen CLK_TOP_ETH_SYS_SEL>,
1411                                  <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1412                                  <&topckgen CLK_TOP_ETH_MII_SEL>,
1413                                  <&topckgen CLK_TOP_NETSYS_SEL>,
1414                                  <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1415                                  <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1416                                  <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1417                                  <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1418                                  <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1419                         clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1420                                       "gp3", "esw", "crypto",
1421                                       "ethwarp_wocpu2", "ethwarp_wocpu1",
1422                                       "ethwarp_wocpu0", "top_eth_gmii_sel",
1423                                       "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1424                                       "top_eth_sys_sel", "top_eth_xgmii_sel",
1425                                       "top_eth_mii_sel", "top_netsys_sel",
1426                                       "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1427                                       "top_netsys_sync_250m_sel",
1428                                       "top_netsys_ppefb_250m_sel",
1429                                       "top_netsys_warp_sel";
1430                         assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1431                                           <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1432                                           <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1433                                           <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1434                                           <&topckgen CLK_TOP_SGM_0_SEL>,
1435                                           <&topckgen CLK_TOP_SGM_1_SEL>;
1436                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1437                                                  <&topckgen CLK_TOP_NET1PLL_D4>,
1438                                                  <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1439                                                  <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1440                                                  <&apmixedsys CLK_APMIXED_SGMPLL>,
1441                                                  <&apmixedsys CLK_APMIXED_SGMPLL>;
1442                         mediatek,ethsys = <&ethsys>;
1443                         mediatek,infracfg = <&topmisc>;
1444                         #address-cells = <1>;
1445                         #size-cells = <0>;
1446
1447                         gmac0: mac@0 {
1448                                 compatible = "mediatek,eth-mac";
1449                                 reg = <0>;
1450                                 phy-mode = "internal";
1451                                 status = "disabled";
1452
1453                                 fixed-link {
1454                                         speed = <10000>;
1455                                         full-duplex;
1456                                         pause;
1457                                 };
1458                         };
1459
1460                         gmac1: mac@1 {
1461                                 compatible = "mediatek,eth-mac";
1462                                 reg = <1>;
1463                                 status = "disabled";
1464                                 pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
1465                                 phys = <&xfi_tphy1>;
1466                         };
1467
1468                         gmac2: mac@2 {
1469                                 compatible = "mediatek,eth-mac";
1470                                 reg = <2>;
1471                                 status = "disabled";
1472                                 pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
1473                                 phys = <&xfi_tphy0>;
1474                         };
1475
1476                         mdio_bus: mdio-bus {
1477                                 #address-cells = <1>;
1478                                 #size-cells = <0>;
1479
1480                                 /* internal 2.5G PHY */
1481                                 int_2p5g_phy: ethernet-phy@15 {
1482                                         compatible = "ethernet-phy-ieee802.3-c45";
1483                                         reg = <15>;
1484                                         phy-mode = "internal";
1485                                 };
1486                         };
1487                 };
1488
1489                 crypto: crypto@15600000 {
1490                         compatible = "inside-secure,safexcel-eip197b";
1491                         reg = <0 0x15600000 0 0x180000>;
1492                         interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1493                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1494                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1495                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1496                         interrupt-names = "ring0", "ring1", "ring2", "ring3";
1497                         status = "okay";
1498                 };
1499         };
1500
1501         thermal-zones {
1502                 cpu_thermal: cpu-thermal {
1503                         polling-delay-passive = <1000>;
1504                         polling-delay = <1000>;
1505                         thermal-sensors = <&lvts 0>;
1506
1507                         trips {
1508                                 cpu_trip_crit: crit {
1509                                         temperature = <125000>;
1510                                         hysteresis = <2000>;
1511                                         type = "critical";
1512                                 };
1513
1514                                 cpu_trip_hot: hot {
1515                                         temperature = <120000>;
1516                                         hysteresis = <2000>;
1517                                         type = "hot";
1518                                 };
1519
1520                                 cpu_trip_active_high: active-high {
1521                                         temperature = <115000>;
1522                                         hysteresis = <2000>;
1523                                         type = "active";
1524                                 };
1525
1526                                 cpu_trip_active_med: active-med {
1527                                         temperature = <85000>;
1528                                         hysteresis = <2000>;
1529                                         type = "active";
1530                                 };
1531
1532                                 cpu_trip_active_low: active-low {
1533                                         temperature = <40000>;
1534                                         hysteresis = <2000>;
1535                                         type = "active";
1536                                 };
1537                         };
1538
1539                         cooling-maps {
1540                                 cpu-active-high {
1541                                 /* active: set fan to cooling level 2 */
1542                                         cooling-device = <&fan 3 3>;
1543                                         trip = <&cpu_trip_active_high>;
1544                                 };
1545
1546                                 cpu-active-low {
1547                                 /* active: set fan to cooling level 1 */
1548                                         cooling-device = <&fan 2 2>;
1549                                         trip = <&cpu_trip_active_med>;
1550                                 };
1551
1552                                 cpu-passive {
1553                                 /* passive: set fan to cooling level 0 */
1554                                         cooling-device = <&fan 1 1>;
1555                                         trip = <&cpu_trip_active_low>;
1556                                 };
1557                         };
1558                 };
1559         };
1560
1561         timer {
1562                 compatible = "arm,armv8-timer";
1563                 interrupt-parent = <&gic>;
1564                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1565                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1566                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1567                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1568         };
1569 };