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mediatek: filogic: reorder mt7988a DTS properties
[openwrt/staging/jow.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/ti-syscon.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 compatible = "mediatek,mt7988";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cci: cci {
23 compatible = "mediatek,mt7988-cci",
24 "mediatek,mt8183-cci";
25 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
26 <&topckgen CLK_TOP_XTAL>;
27 clock-names = "cci", "intermediate";
28 operating-points-v2 = <&cci_opp>;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 cpu0: cpu@0 {
35 compatible = "arm,cortex-a73";
36 reg = <0x0>;
37 device_type = "cpu";
38 enable-method = "psci";
39 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
40 <&topckgen CLK_TOP_XTAL>;
41 clock-names = "cpu", "intermediate";
42 operating-points-v2 = <&cluster0_opp>;
43 mediatek,cci = <&cci>;
44 };
45
46 cpu1: cpu@1 {
47 compatible = "arm,cortex-a73";
48 reg = <0x1>;
49 device_type = "cpu";
50 enable-method = "psci";
51 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
52 <&topckgen CLK_TOP_XTAL>;
53 clock-names = "cpu", "intermediate";
54 operating-points-v2 = <&cluster0_opp>;
55 mediatek,cci = <&cci>;
56 };
57
58 cpu2: cpu@2 {
59 compatible = "arm,cortex-a73";
60 reg = <0x2>;
61 device_type = "cpu";
62 enable-method = "psci";
63 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
64 <&topckgen CLK_TOP_XTAL>;
65 clock-names = "cpu", "intermediate";
66 operating-points-v2 = <&cluster0_opp>;
67 mediatek,cci = <&cci>;
68 };
69
70 cpu3: cpu@3 {
71 compatible = "arm,cortex-a73";
72 reg = <0x3>;
73 device_type = "cpu";
74 enable-method = "psci";
75 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
76 <&topckgen CLK_TOP_XTAL>;
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cluster0_opp>;
79 mediatek,cci = <&cci>;
80 };
81
82 cluster0_opp: opp_table0 {
83 compatible = "operating-points-v2";
84 opp-shared;
85 opp00 {
86 opp-hz = /bits/ 64 <800000000>;
87 opp-microvolt = <850000>;
88 };
89 opp01 {
90 opp-hz = /bits/ 64 <1100000000>;
91 opp-microvolt = <850000>;
92 };
93 opp02 {
94 opp-hz = /bits/ 64 <1500000000>;
95 opp-microvolt = <850000>;
96 };
97 opp03 {
98 opp-hz = /bits/ 64 <1800000000>;
99 opp-microvolt = <900000>;
100 };
101 };
102 };
103
104 cci_opp: opp_table_cci {
105 compatible = "operating-points-v2";
106 opp-shared;
107 opp00 {
108 opp-hz = /bits/ 64 <480000000>;
109 opp-microvolt = <850000>;
110 };
111 opp01 {
112 opp-hz = /bits/ 64 <660000000>;
113 opp-microvolt = <850000>;
114 };
115 opp02 {
116 opp-hz = /bits/ 64 <900000000>;
117 opp-microvolt = <850000>;
118 };
119 opp03 {
120 opp-hz = /bits/ 64 <1080000000>;
121 opp-microvolt = <900000>;
122 };
123 };
124
125 clk40m: oscillator@0 {
126 compatible = "fixed-clock";
127 clock-frequency = <40000000>;
128 #clock-cells = <0>;
129 clock-output-names = "clkxtal";
130 };
131
132 pmu {
133 compatible = "arm,cortex-a73-pmu";
134 interrupt-parent = <&gic>;
135 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
136 };
137
138 psci {
139 compatible = "arm,psci-0.2";
140 method = "smc";
141 };
142
143 reg_1p8v: regulator-1p8v {
144 compatible = "regulator-fixed";
145 regulator-name = "fixed-1.8V";
146 regulator-min-microvolt = <1800000>;
147 regulator-max-microvolt = <1800000>;
148 regulator-boot-on;
149 regulator-always-on;
150 };
151
152 reg_3p3v: regulator-3p3v {
153 compatible = "regulator-fixed";
154 regulator-name = "fixed-3.3V";
155 regulator-min-microvolt = <3300000>;
156 regulator-max-microvolt = <3300000>;
157 regulator-boot-on;
158 regulator-always-on;
159 };
160
161 reserved-memory {
162 ranges;
163 #address-cells = <2>;
164 #size-cells = <2>;
165
166 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
167 secmon_reserved: secmon@43000000 {
168 reg = <0 0x43000000 0 0x50000>;
169 no-map;
170 };
171 };
172
173 soc {
174 compatible = "simple-bus";
175 ranges;
176 #address-cells = <2>;
177 #size-cells = <2>;
178
179 gic: interrupt-controller@c000000 {
180 compatible = "arm,gic-v3";
181 reg = <0 0x0c000000 0 0x40000>, /* GICD */
182 <0 0x0c080000 0 0x200000>, /* GICR */
183 <0 0x0c400000 0 0x2000>, /* GICC */
184 <0 0x0c410000 0 0x1000>, /* GICH */
185 <0 0x0c420000 0 0x2000>; /* GICV */
186 interrupt-parent = <&gic>;
187 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-controller;
189 #interrupt-cells = <3>;
190 };
191
192 phyfw: phy-firmware@f000000 {
193 compatible = "mediatek,2p5gphy-fw";
194 reg = <0 0x0f000000 0 0x8000>,
195 <0 0x0f100000 0 0x20000>,
196 <0 0x0f0f0000 0 0x200>;
197 };
198
199 infracfg: infracfg@10001000 {
200 compatible = "mediatek,mt7988-infracfg", "syscon";
201 reg = <0 0x10001000 0 0x1000>;
202 #clock-cells = <1>;
203 };
204
205 topckgen: topckgen@1001b000 {
206 compatible = "mediatek,mt7988-topckgen", "syscon";
207 reg = <0 0x1001b000 0 0x1000>;
208 #clock-cells = <1>;
209 };
210
211 watchdog: watchdog@1001c000 {
212 compatible = "mediatek,mt7988-wdt",
213 "mediatek,mt6589-wdt",
214 "syscon";
215 reg = <0 0x1001c000 0 0x1000>;
216 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
217 #reset-cells = <1>;
218 };
219
220 apmixedsys: apmixedsys@1001e000 {
221 compatible = "mediatek,mt7988-apmixedsys";
222 reg = <0 0x1001e000 0 0x1000>;
223 #clock-cells = <1>;
224 };
225
226 pio: pinctrl@1001f000 {
227 compatible = "mediatek,mt7988-pinctrl", "syscon";
228 reg = <0 0x1001f000 0 0x1000>,
229 <0 0x11c10000 0 0x1000>,
230 <0 0x11d00000 0 0x1000>,
231 <0 0x11d20000 0 0x1000>,
232 <0 0x11e00000 0 0x1000>,
233 <0 0x11f00000 0 0x1000>,
234 <0 0x1000b000 0 0x1000>;
235 reg-names = "gpio_base", "iocfg_tr_base",
236 "iocfg_br_base", "iocfg_rb_base",
237 "iocfg_lb_base", "iocfg_tl_base", "eint";
238 gpio-controller;
239 #gpio-cells = <2>;
240 gpio-ranges = <&pio 0 0 84>;
241 interrupt-controller;
242 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-parent = <&gic>;
244 #interrupt-cells = <2>;
245
246 mdio0_pins: mdio0-pins {
247 mux {
248 function = "eth";
249 groups = "mdc_mdio0";
250 };
251
252 conf {
253 groups = "mdc_mdio0";
254 drive-strength = <MTK_DRIVE_8mA>;
255 };
256 };
257
258 i2c0_pins: i2c0-pins-g0 {
259 mux {
260 function = "i2c";
261 groups = "i2c0_1";
262 };
263 };
264
265 i2c1_pins: i2c1-pins-g0 {
266 mux {
267 function = "i2c";
268 groups = "i2c1_0";
269 };
270 };
271
272 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
273 mux {
274 function = "i2c";
275 groups = "i2c1_sfp";
276 };
277 };
278
279 i2c2_pins: i2c2-pins {
280 mux {
281 function = "i2c";
282 groups = "i2c2";
283 };
284 };
285
286 i2c2_0_pins: i2c2-pins-g0 {
287 mux {
288 function = "i2c";
289 groups = "i2c2_0";
290 };
291 };
292
293 i2c2_1_pins: i2c2-pins-g1 {
294 mux {
295 function = "i2c";
296 groups = "i2c2_1";
297 };
298 };
299
300 gbe0_led0_pins: gbe0-led0-pins {
301 mux {
302 function = "led";
303 groups = "gbe0_led0";
304 };
305 };
306
307 gbe1_led0_pins: gbe1-led0-pins {
308 mux {
309 function = "led";
310 groups = "gbe1_led0";
311 };
312 };
313
314 gbe2_led0_pins: gbe2-led0-pins {
315 mux {
316 function = "led";
317 groups = "gbe2_led0";
318 };
319 };
320
321 gbe3_led0_pins: gbe3-led0-pins {
322 mux {
323 function = "led";
324 groups = "gbe3_led0";
325 };
326 };
327
328 gbe0_led1_pins: gbe0-led1-pins {
329 mux {
330 function = "led";
331 groups = "gbe0_led1";
332 };
333 };
334
335 gbe1_led1_pins: gbe1-led1-pins {
336 mux {
337 function = "led";
338 groups = "gbe1_led1";
339 };
340 };
341
342 gbe2_led1_pins: gbe2-led1-pins {
343 mux {
344 function = "led";
345 groups = "gbe2_led1";
346 };
347 };
348
349 gbe3_led1_pins: gbe3-led1-pins {
350 mux {
351 function = "led";
352 groups = "gbe3_led1";
353 };
354 };
355
356 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
357 mux {
358 function = "led";
359 groups = "2p5gbe_led0";
360 };
361 };
362
363 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
364 mux {
365 function = "led";
366 groups = "2p5gbe_led1";
367 };
368 };
369
370 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
371 mux {
372 function = "flash";
373 groups = "emmc_45";
374 };
375 };
376
377 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
378 mux {
379 function = "flash";
380 groups = "emmc_51";
381 };
382 };
383
384 mmc0_pins_sdcard: mmc0-pins-sdcard {
385 mux {
386 function = "flash";
387 groups = "sdcard";
388 };
389 };
390
391 uart0_pins: uart0-pins {
392 mux {
393 function = "uart";
394 groups = "uart0";
395 };
396 };
397
398 snfi_pins: snfi-pins {
399 mux {
400 function = "flash";
401 groups = "snfi";
402 };
403 };
404
405 spi0_pins: spi0-pins {
406 mux {
407 function = "spi";
408 groups = "spi0";
409 };
410 };
411
412 spi0_flash_pins: spi0-flash-pins {
413 mux {
414 function = "spi";
415 groups = "spi0", "spi0_wp_hold";
416 };
417 };
418
419 spi1_pins: spi1-pins {
420 mux {
421 function = "spi";
422 groups = "spi1";
423 };
424 };
425
426 spi2_pins: spi2-pins {
427 mux {
428 function = "spi";
429 groups = "spi2";
430 };
431 };
432
433 spi2_flash_pins: spi2-flash-pins {
434 mux {
435 function = "spi";
436 groups = "spi2", "spi2_wp_hold";
437 };
438 };
439
440 pcie0_pins: pcie0-pins {
441 mux {
442 function = "pcie";
443 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
444 "pcie_wake_n0_0";
445 };
446 };
447
448 pcie1_pins: pcie1-pins {
449 mux {
450 function = "pcie";
451 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
452 "pcie_wake_n1_0";
453 };
454 };
455
456 pcie2_pins: pcie2-pins {
457 mux {
458 function = "pcie";
459 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
460 "pcie_wake_n2_0";
461 };
462 };
463
464 pcie3_pins: pcie3-pins {
465 mux {
466 function = "pcie";
467 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
468 "pcie_wake_n3_0";
469 };
470 };
471 };
472
473 pwm: pwm@10048000 {
474 compatible = "mediatek,mt7988-pwm";
475 reg = <0 0x10048000 0 0x1000>;
476 #pwm-cells = <2>;
477 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
478 <&infracfg CLK_INFRA_66M_PWM_HCK>,
479 <&infracfg CLK_INFRA_66M_PWM_CK1>,
480 <&infracfg CLK_INFRA_66M_PWM_CK2>,
481 <&infracfg CLK_INFRA_66M_PWM_CK3>,
482 <&infracfg CLK_INFRA_66M_PWM_CK4>,
483 <&infracfg CLK_INFRA_66M_PWM_CK5>,
484 <&infracfg CLK_INFRA_66M_PWM_CK6>,
485 <&infracfg CLK_INFRA_66M_PWM_CK7>,
486 <&infracfg CLK_INFRA_66M_PWM_CK8>;
487 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
488 "pwm4","pwm5","pwm6","pwm7","pwm8";
489 status = "disabled";
490 };
491
492 sgmiisys0: syscon@10060000 {
493 compatible = "mediatek,mt7988-sgmiisys",
494 "mediatek,mt7988-sgmiisys_0",
495 "syscon";
496 reg = <0 0x10060000 0 0x1000>;
497 #clock-cells = <1>;
498 };
499
500 sgmiisys1: syscon@10070000 {
501 compatible = "mediatek,mt7988-sgmiisys",
502 "mediatek,mt7988-sgmiisys_1",
503 "syscon";
504 reg = <0 0x10070000 0 0x1000>;
505 #clock-cells = <1>;
506 };
507
508 usxgmiisys0: usxgmiisys@10080000 {
509 compatible = "mediatek,mt7988-usxgmiisys",
510 "mediatek,mt7988-usxgmiisys_0",
511 "syscon";
512 reg = <0 0x10080000 0 0x1000>;
513 #clock-cells = <1>;
514 };
515
516 usxgmiisys1: usxgmiisys@10081000 {
517 compatible = "mediatek,mt7988-usxgmiisys",
518 "mediatek,mt7988-usxgmiisys_1",
519 "syscon";
520 reg = <0 0x10081000 0 0x1000>;
521 #clock-cells = <1>;
522 };
523
524 mcusys: mcusys@100e0000 {
525 compatible = "mediatek,mt7988-mcusys", "syscon";
526 reg = <0 0x100e0000 0 0x1000>;
527 #clock-cells = <1>;
528 };
529
530 uart0: serial@11000000 {
531 compatible = "mediatek,mt7986-uart",
532 "mediatek,mt6577-uart";
533 reg = <0 0x11000000 0 0x100>;
534 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
535 /*
536 * 8250-mtk driver don't control "baud" clock since commit
537 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
538 * still need to be passed to the driver to prevent probe fail
539 */
540 clocks = <&topckgen CLK_TOP_UART_SEL>,
541 <&infracfg CLK_INFRA_52M_UART0_CK>;
542 clock-names = "baud", "bus";
543 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
544 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
545 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
546 <&topckgen CLK_TOP_UART_SEL>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&uart0_pins>;
549 status = "disabled";
550 };
551
552 snand: spi@11001000 {
553 compatible = "mediatek,mt7986-snand";
554 reg = <0 0x11001000 0 0x1000>;
555 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&infracfg CLK_INFRA_SPINFI>,
557 <&infracfg CLK_INFRA_NFI>;
558 clock-names = "pad_clk", "nfi_clk";
559 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
560 <&topckgen CLK_TOP_NFI1X_SEL>;
561 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
562 <&topckgen CLK_TOP_MPLL_D8>;
563 nand-ecc-engine = <&bch>;
564 mediatek,quad-spi;
565 #address-cells = <1>;
566 #size-cells = <0>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&snfi_pins>;
569 status = "disabled";
570 };
571
572 bch: ecc@11002000 {
573 compatible = "mediatek,mt7686-ecc";
574 reg = <0 0x11002000 0 0x1000>;
575 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
577 clock-names = "nfiecc_clk";
578 status = "disabled";
579 };
580
581 i2c0: i2c@11003000 {
582 compatible = "mediatek,mt7988-i2c",
583 "mediatek,mt7981-i2c";
584 reg = <0 0x11003000 0 0x1000>,
585 <0 0x10217080 0 0x80>;
586 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
587 clock-div = <1>;
588 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
589 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
590 clock-names = "main", "dma";
591 #address-cells = <1>;
592 #size-cells = <0>;
593 status = "disabled";
594 };
595
596 i2c1: i2c@11004000 {
597 compatible = "mediatek,mt7988-i2c",
598 "mediatek,mt7981-i2c";
599 reg = <0 0x11004000 0 0x1000>,
600 <0 0x10217100 0 0x80>;
601 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
602 clock-div = <1>;
603 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
604 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
605 clock-names = "main", "dma";
606 #address-cells = <1>;
607 #size-cells = <0>;
608 status = "disabled";
609 };
610
611 i2c2: i2c@11005000 {
612 compatible = "mediatek,mt7988-i2c",
613 "mediatek,mt7981-i2c";
614 reg = <0 0x11005000 0 0x1000>,
615 <0 0x10217180 0 0x80>;
616 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
617 clock-div = <1>;
618 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
619 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
620 clock-names = "main", "dma";
621 #address-cells = <1>;
622 #size-cells = <0>;
623 status = "disabled";
624 };
625
626 spi0: spi@11007000 {
627 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
628 reg = <0 0x11007000 0 0x100>;
629 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&topckgen CLK_TOP_MPLL_D2>,
631 <&topckgen CLK_TOP_SPI_SEL>,
632 <&infracfg CLK_INFRA_104M_SPI0>,
633 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
634 clock-names = "parent-clk", "sel-clk", "spi-clk",
635 "spi-hclk";
636 #address-cells = <1>;
637 #size-cells = <0>;
638 status = "disabled";
639 };
640
641 spi1: spi@11008000 {
642 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
643 reg = <0 0x11008000 0 0x100>;
644 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&topckgen CLK_TOP_MPLL_D2>,
646 <&topckgen CLK_TOP_SPI_SEL>,
647 <&infracfg CLK_INFRA_104M_SPI1>,
648 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
649 clock-names = "parent-clk", "sel-clk", "spi-clk",
650 "spi-hclk";
651 #address-cells = <1>;
652 #size-cells = <0>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&spi1_pins>;
655 status = "disabled";
656 };
657
658 spi2: spi@11009000 {
659 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
660 reg = <0 0x11009000 0 0x100>;
661 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&topckgen CLK_TOP_MPLL_D2>,
663 <&topckgen CLK_TOP_SPI_SEL>,
664 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
665 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
666 clock-names = "parent-clk", "sel-clk", "spi-clk",
667 "spi-hclk";
668 #address-cells = <1>;
669 #size-cells = <0>;
670 status = "disabled";
671 };
672
673 fan: pwm-fan {
674 compatible = "pwm-fan";
675 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
676 cooling-levels = <0 128 255>;
677 #cooling-cells = <2>;
678 #thermal-sensor-cells = <1>;
679 status = "disabled";
680 };
681
682 lvts: lvts@1100a000 {
683 compatible = "mediatek,mt7988-lvts";
684 reg = <0 0x1100a000 0 0x1000>;
685 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
686 clock-names = "lvts_clk";
687 nvmem-cells = <&lvts_calibration>;
688 nvmem-cell-names = "e_data1";
689 #thermal-sensor-cells = <1>;
690 };
691
692 ssusb0: usb@11190000 {
693 compatible = "mediatek,mt7988-xhci",
694 "mediatek,mtk-xhci";
695 reg = <0 0x11190000 0 0x2e00>,
696 <0 0x11193e00 0 0x0100>;
697 reg-names = "mac", "ippc";
698 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
699 phys = <&xphyu2port0 PHY_TYPE_USB2>,
700 <&xphyu3port0 PHY_TYPE_USB3>;
701 clocks = <&infracfg CLK_INFRA_USB_SYS>,
702 <&infracfg CLK_INFRA_USB_XHCI>,
703 <&infracfg CLK_INFRA_USB_REF>,
704 <&infracfg CLK_INFRA_66M_USB_HCK>,
705 <&infracfg CLK_INFRA_133M_USB_HCK>;
706 clock-names = "sys_ck",
707 "xhci_ck",
708 "ref_ck",
709 "mcu_ck",
710 "dma_ck";
711 #address-cells = <2>;
712 #size-cells = <2>;
713 mediatek,p0_speed_fixup;
714 status = "disabled";
715 };
716
717 ssusb1: usb@11200000 {
718 compatible = "mediatek,mt7988-xhci",
719 "mediatek,mtk-xhci";
720 reg = <0 0x11200000 0 0x2e00>,
721 <0 0x11203e00 0 0x0100>;
722 reg-names = "mac", "ippc";
723 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
724 phys = <&tphyu2port0 PHY_TYPE_USB2>,
725 <&tphyu3port0 PHY_TYPE_USB3>;
726 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
727 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
728 <&infracfg CLK_INFRA_USB_CK_P1>,
729 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
730 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
731 clock-names = "sys_ck",
732 "xhci_ck",
733 "ref_ck",
734 "mcu_ck",
735 "dma_ck";
736 #address-cells = <2>;
737 #size-cells = <2>;
738 status = "disabled";
739 };
740
741 afe: audio-controller@11210000 {
742 compatible = "mediatek,mt79xx-audio";
743 reg = <0 0x11210000 0 0x9000>;
744 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
746 <&infracfg CLK_INFRA_AUD_26M>,
747 <&infracfg CLK_INFRA_AUD_L>,
748 <&infracfg CLK_INFRA_AUD_AUD>,
749 <&infracfg CLK_INFRA_AUD_EG2>,
750 <&topckgen CLK_TOP_AUD_SEL>,
751 <&topckgen CLK_TOP_AUD_I2S_M>;
752 clock-names = "aud_bus_ck",
753 "aud_26m_ck",
754 "aud_l_ck",
755 "aud_aud_ck",
756 "aud_eg2_ck",
757 "aud_sel",
758 "aud_i2s_m";
759 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
760 <&topckgen CLK_TOP_A1SYS_SEL>,
761 <&topckgen CLK_TOP_AUD_L_SEL>,
762 <&topckgen CLK_TOP_A_TUNER_SEL>;
763 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
764 <&topckgen CLK_TOP_APLL2_D4>,
765 <&apmixedsys CLK_APMIXED_APLL2>,
766 <&topckgen CLK_TOP_APLL2_D4>;
767 status = "disabled";
768 };
769
770 mmc0: mmc@11230000 {
771 compatible = "mediatek,mt7986-mmc",
772 "mediatek,mt7981-mmc";
773 reg = <0 0x11230000 0 0x1000>,
774 <0 0x11D60000 0 0x1000>;
775 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&infracfg CLK_INFRA_MSDC400>,
777 <&infracfg CLK_INFRA_MSDC2_HCK>,
778 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
779 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
780 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
781 <&topckgen CLK_TOP_EMMC_400M_SEL>;
782 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
783 <&apmixedsys CLK_APMIXED_MSDCPLL>;
784 clock-names = "source",
785 "hclk",
786 "axi_cg",
787 "ahb_cg";
788 #address-cells = <1>;
789 #size-cells = <0>;
790 status = "disabled";
791 };
792
793 pcie2: pcie@11280000 {
794 compatible = "mediatek,mt7988-pcie",
795 "mediatek,mt7986-pcie",
796 "mediatek,mt8192-pcie";
797 reg = <0 0x11280000 0 0x2000>;
798 reg-names = "pcie-mac";
799 ranges = <0x81000000 0x00 0x20000000 0x00
800 0x20000000 0x00 0x00200000>,
801 <0x82000000 0x00 0x20200000 0x00
802 0x20200000 0x00 0x07e00000>;
803 device_type = "pci";
804 linux,pci-domain = <3>;
805 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
806 bus-range = <0x00 0xff>;
807 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
808 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
809 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
810 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
811 clock-names = "pl_250m", "tl_26m", "peri_26m",
812 "top_133m";
813 pinctrl-names = "default";
814 pinctrl-0 = <&pcie2_pins>;
815 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
816 phy-names = "pcie-phy";
817 #interrupt-cells = <1>;
818 interrupt-map-mask = <0 0 0 0x7>;
819 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
820 <0 0 0 2 &pcie_intc2 1>,
821 <0 0 0 3 &pcie_intc2 2>,
822 <0 0 0 4 &pcie_intc2 3>;
823 #address-cells = <3>;
824 #size-cells = <2>;
825 status = "disabled";
826
827 pcie_intc2: interrupt-controller {
828 #address-cells = <0>;
829 #interrupt-cells = <1>;
830 interrupt-controller;
831 };
832 };
833
834 pcie3: pcie@11290000 {
835 compatible = "mediatek,mt7988-pcie",
836 "mediatek,mt7986-pcie",
837 "mediatek,mt8192-pcie";
838 reg = <0 0x11290000 0 0x2000>;
839 reg-names = "pcie-mac";
840 ranges = <0x81000000 0x00 0x28000000 0x00
841 0x28000000 0x00 0x00200000>,
842 <0x82000000 0x00 0x28200000 0x00
843 0x28200000 0x00 0x07e00000>;
844 device_type = "pci";
845 linux,pci-domain = <2>;
846 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
847 bus-range = <0x00 0xff>;
848 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
849 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
850 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
851 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
852 clock-names = "pl_250m", "tl_26m", "peri_26m",
853 "top_133m";
854 pinctrl-names = "default";
855 pinctrl-0 = <&pcie3_pins>;
856 #interrupt-cells = <1>;
857 interrupt-map-mask = <0 0 0 0x7>;
858 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
859 <0 0 0 2 &pcie_intc3 1>,
860 <0 0 0 3 &pcie_intc3 2>,
861 <0 0 0 4 &pcie_intc3 3>;
862 #address-cells = <3>;
863 #size-cells = <2>;
864 status = "disabled";
865
866 pcie_intc3: interrupt-controller {
867 #address-cells = <0>;
868 #interrupt-cells = <1>;
869 interrupt-controller;
870 };
871 };
872
873 pcie0: pcie@11300000 {
874 compatible = "mediatek,mt7988-pcie",
875 "mediatek,mt7986-pcie",
876 "mediatek,mt8192-pcie";
877 reg = <0 0x11300000 0 0x2000>;
878 reg-names = "pcie-mac";
879 ranges = <0x81000000 0x00 0x30000000 0x00
880 0x30000000 0x00 0x00200000>,
881 <0x82000000 0x00 0x30200000 0x00
882 0x30200000 0x00 0x07e00000>;
883 device_type = "pci";
884 linux,pci-domain = <0>;
885 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
886 bus-range = <0x00 0xff>;
887 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
888 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
889 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
890 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
891 clock-names = "pl_250m", "tl_26m", "peri_26m",
892 "top_133m";
893 pinctrl-names = "default";
894 pinctrl-0 = <&pcie0_pins>;
895 #interrupt-cells = <1>;
896 interrupt-map-mask = <0 0 0 0x7>;
897 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
898 <0 0 0 2 &pcie_intc0 1>,
899 <0 0 0 3 &pcie_intc0 2>,
900 <0 0 0 4 &pcie_intc0 3>;
901 #address-cells = <3>;
902 #size-cells = <2>;
903 status = "disabled";
904
905 pcie_intc0: interrupt-controller {
906 #address-cells = <0>;
907 #interrupt-cells = <1>;
908 interrupt-controller;
909 };
910 };
911
912 pcie1: pcie@11310000 {
913 compatible = "mediatek,mt7988-pcie",
914 "mediatek,mt7986-pcie",
915 "mediatek,mt8192-pcie";
916 reg = <0 0x11310000 0 0x2000>;
917 reg-names = "pcie-mac";
918 ranges = <0x81000000 0x00 0x38000000 0x00
919 0x38000000 0x00 0x00200000>,
920 <0x82000000 0x00 0x38200000 0x00
921 0x38200000 0x00 0x07e00000>;
922 device_type = "pci";
923 linux,pci-domain = <1>;
924 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
925 bus-range = <0x00 0xff>;
926 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
927 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
928 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
929 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
930 clock-names = "pl_250m", "tl_26m", "peri_26m",
931 "top_133m";
932 pinctrl-names = "default";
933 pinctrl-0 = <&pcie1_pins>;
934 #interrupt-cells = <1>;
935 interrupt-map-mask = <0 0 0 0x7>;
936 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
937 <0 0 0 2 &pcie_intc1 1>,
938 <0 0 0 3 &pcie_intc1 2>,
939 <0 0 0 4 &pcie_intc1 3>;
940 #address-cells = <3>;
941 #size-cells = <2>;
942 status = "disabled";
943
944 pcie_intc1: interrupt-controller {
945 #address-cells = <0>;
946 #interrupt-cells = <1>;
947 interrupt-controller;
948 };
949 };
950
951 tphy: tphy@11c50000 {
952 compatible = "mediatek,mt7988",
953 "mediatek,generic-tphy-v2";
954 ranges;
955 #address-cells = <2>;
956 #size-cells = <2>;
957 status = "disabled";
958 tphyu2port0: usb-phy@11c50000 {
959 reg = <0 0x11c50000 0 0x700>;
960 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
961 clock-names = "ref";
962 #phy-cells = <1>;
963 };
964 tphyu3port0: usb-phy@11c50700 {
965 reg = <0 0x11c50700 0 0x900>;
966 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
967 clock-names = "ref";
968 #phy-cells = <1>;
969 mediatek,usb3-pll-ssc-delta;
970 mediatek,usb3-pll-ssc-delta1;
971 };
972 };
973
974 topmisc: topmisc@11d10000 {
975 compatible = "mediatek,mt7988-topmisc", "syscon",
976 "mediatek,mt7988-power-controller";
977 reg = <0 0x11d10000 0 0x10000>;
978 #clock-cells = <1>;
979 #power-domain-cells = <1>;
980 #address-cells = <1>;
981 #size-cells = <0>;
982 };
983
984 xphy: xphy@11e10000 {
985 compatible = "mediatek,mt7988",
986 "mediatek,xsphy";
987 ranges;
988 #address-cells = <2>;
989 #size-cells = <2>;
990 status = "disabled";
991
992 xphyu2port0: usb-phy@11e10000 {
993 reg = <0 0x11e10000 0 0x400>;
994 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
995 clock-names = "ref";
996 #phy-cells = <1>;
997 };
998
999 xphyu3port0: usb-phy@11e13000 {
1000 reg = <0 0x11e13400 0 0x500>;
1001 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1002 clock-names = "ref";
1003 #phy-cells = <1>;
1004 mediatek,syscon-type = <&topmisc 0x218 0>;
1005 };
1006 };
1007
1008 xfi_pextp0: xfi-pextp@11f20000 {
1009 compatible = "mediatek,mt7988-xfi-pextp",
1010 "mediatek,mt7988-xfi-pextp_0",
1011 "syscon";
1012 reg = <0 0x11f20000 0 0x10000>;
1013 #clock-cells = <1>;
1014 };
1015
1016 xfi_pextp1: xfi-pextp@11f30000 {
1017 compatible = "mediatek,mt7988-xfi-pextp",
1018 "mediatek,mt7988-xfi-pextp_1",
1019 "syscon";
1020 reg = <0 0x11f30000 0 0x10000>;
1021 #clock-cells = <1>;
1022 };
1023
1024 xfi_pll: xfi-pll@11f40000 {
1025 compatible = "mediatek,mt7988-xfi-pll", "syscon";
1026 reg = <0 0x11f40000 0 0x1000>;
1027 #clock-cells = <1>;
1028 };
1029
1030 efuse: efuse@11f50000 {
1031 compatible = "mediatek,efuse";
1032 reg = <0 0x11f50000 0 0x1000>;
1033 #address-cells = <1>;
1034 #size-cells = <1>;
1035
1036 lvts_calibration: calib@918 {
1037 reg = <0x918 0x28>;
1038 };
1039 phy_calibration_p0: calib@940 {
1040 reg = <0x940 0x10>;
1041 };
1042 phy_calibration_p1: calib@954 {
1043 reg = <0x954 0x10>;
1044 };
1045 phy_calibration_p2: calib@968 {
1046 reg = <0x968 0x10>;
1047 };
1048 phy_calibration_p3: calib@97c {
1049 reg = <0x97c 0x10>;
1050 };
1051 cpufreq_calibration: calib@278 {
1052 reg = <0x278 0x1>;
1053 };
1054 };
1055
1056 ethsys: syscon@15000000 {
1057 compatible = "mediatek,mt7988-ethsys", "syscon";
1058 reg = <0 0x15000000 0 0x1000>;
1059 #clock-cells = <1>;
1060 #reset-cells = <1>;
1061 #address-cells = <1>;
1062 #size-cells = <1>;
1063 };
1064
1065 switch: switch@15020000 {
1066 compatible = "mediatek,mt7988-switch";
1067 reg = <0 0x15020000 0 0x8000>;
1068 interrupt-controller;
1069 #interrupt-cells = <1>;
1070 interrupt-parent = <&gic>;
1071 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1072 resets = <&ethrst 0>;
1073 #address-cells = <1>;
1074 #size-cells = <1>;
1075
1076 ports {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079
1080 port@0 {
1081 reg = <0>;
1082 label = "lan0";
1083 phy-mode = "internal";
1084 phy-handle = <&gsw_phy0>;
1085 };
1086
1087 port@1 {
1088 reg = <1>;
1089 label = "lan1";
1090 phy-mode = "internal";
1091 phy-handle = <&gsw_phy1>;
1092 };
1093
1094 port@2 {
1095 reg = <2>;
1096 label = "lan2";
1097 phy-mode = "internal";
1098 phy-handle = <&gsw_phy2>;
1099 };
1100
1101 port@3 {
1102 reg = <3>;
1103 label = "lan3";
1104 phy-mode = "internal";
1105 phy-handle = <&gsw_phy3>;
1106 };
1107
1108 port@6 {
1109 reg = <6>;
1110 ethernet = <&gmac0>;
1111 phy-mode = "internal";
1112
1113 fixed-link {
1114 speed = <10000>;
1115 full-duplex;
1116 pause;
1117 };
1118 };
1119 };
1120
1121 mdio {
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1124 mediatek,pio = <&pio>;
1125
1126 gsw_phy0: ethernet-phy@0 {
1127 compatible = "ethernet-phy-ieee802.3-c22";
1128 reg = <0>;
1129 phy-mode = "internal";
1130 nvmem-cells = <&phy_calibration_p0>;
1131 nvmem-cell-names = "phy-cal-data";
1132
1133 leds {
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136
1137 gsw_phy0_led0: gsw-phy0-led0@0 {
1138 reg = <0>;
1139 function = LED_FUNCTION_LAN;
1140 status = "disabled";
1141 };
1142
1143 gsw_phy0_led1: gsw-phy0-led1@1 {
1144 reg = <1>;
1145 function = LED_FUNCTION_LAN;
1146 status = "disabled";
1147 };
1148 };
1149 };
1150
1151 gsw_phy1: ethernet-phy@1 {
1152 compatible = "ethernet-phy-ieee802.3-c22";
1153 reg = <1>;
1154 phy-mode = "internal";
1155 nvmem-cells = <&phy_calibration_p1>;
1156 nvmem-cell-names = "phy-cal-data";
1157
1158 leds {
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161
1162 gsw_phy1_led0: gsw-phy1-led0@0 {
1163 reg = <0>;
1164 function = LED_FUNCTION_LAN;
1165 status = "disabled";
1166 };
1167
1168 gsw_phy1_led1: gsw-phy1-led1@1 {
1169 reg = <1>;
1170 function = LED_FUNCTION_LAN;
1171 status = "disabled";
1172 };
1173 };
1174 };
1175
1176 gsw_phy2: ethernet-phy@2 {
1177 compatible = "ethernet-phy-ieee802.3-c22";
1178 reg = <2>;
1179 phy-mode = "internal";
1180 nvmem-cells = <&phy_calibration_p2>;
1181 nvmem-cell-names = "phy-cal-data";
1182
1183 leds {
1184 #address-cells = <1>;
1185 #size-cells = <0>;
1186
1187 gsw_phy2_led0: gsw-phy2-led0@0 {
1188 reg = <0>;
1189 function = LED_FUNCTION_LAN;
1190 status = "disabled";
1191 };
1192
1193 gsw_phy2_led1: gsw-phy2-led1@1 {
1194 reg = <1>;
1195 function = LED_FUNCTION_LAN;
1196 status = "disabled";
1197 };
1198 };
1199 };
1200
1201 gsw_phy3: ethernet-phy@3 {
1202 compatible = "ethernet-phy-ieee802.3-c22";
1203 reg = <3>;
1204 phy-mode = "internal";
1205 nvmem-cells = <&phy_calibration_p3>;
1206 nvmem-cell-names = "phy-cal-data";
1207
1208 leds {
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1211
1212 gsw_phy3_led0: gsw-phy3-led0@0 {
1213 reg = <0>;
1214 function = LED_FUNCTION_LAN;
1215 status = "disabled";
1216 };
1217
1218 gsw_phy3_led1: gsw-phy3-led1@1 {
1219 reg = <1>;
1220 function = LED_FUNCTION_LAN;
1221 status = "disabled";
1222 };
1223 };
1224 };
1225 };
1226 };
1227
1228 ethwarp: syscon@15031000 {
1229 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
1230 reg = <0 0x15031000 0 0x1000>;
1231 #clock-cells = <1>;
1232
1233 ethrst: reset-controller {
1234 compatible = "ti,syscon-reset";
1235 #reset-cells = <1>;
1236 ti,reset-bits = <
1237 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
1238 >;
1239 };
1240 };
1241
1242 eth: ethernet@15100000 {
1243 compatible = "mediatek,mt7988-eth";
1244 reg = <0 0x15100000 0 0x80000>,
1245 <0 0x15400000 0 0x380000>;
1246 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1251 <&ethsys CLK_ETHDMA_XGP2_EN>,
1252 <&ethsys CLK_ETHDMA_XGP3_EN>,
1253 <&ethsys CLK_ETHDMA_FE_EN>,
1254 <&ethsys CLK_ETHDMA_GP2_EN>,
1255 <&ethsys CLK_ETHDMA_GP1_EN>,
1256 <&ethsys CLK_ETHDMA_GP3_EN>,
1257 <&ethsys CLK_ETHDMA_ESW_EN>,
1258 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1259 <&sgmiisys0 CLK_SGM0_TX_EN>,
1260 <&sgmiisys0 CLK_SGM0_RX_EN>,
1261 <&sgmiisys1 CLK_SGM1_TX_EN>,
1262 <&sgmiisys1 CLK_SGM1_RX_EN>,
1263 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1264 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1265 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1266 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1267 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1268 <&topckgen CLK_TOP_SGM_0_SEL>,
1269 <&topckgen CLK_TOP_SGM_1_SEL>,
1270 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
1271 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
1272 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1273 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1274 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1275 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1276 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1277 <&topckgen CLK_TOP_ETH_MII_SEL>,
1278 <&topckgen CLK_TOP_NETSYS_SEL>,
1279 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1280 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1281 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1282 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1283 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1284 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1285 "gp3", "esw", "crypto", "sgmii_tx250m",
1286 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
1287 "ethwarp_wocpu2", "ethwarp_wocpu1",
1288 "ethwarp_wocpu0", "top_usxgmii0_sel",
1289 "top_usxgmii1_sel", "top_sgm0_sel",
1290 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
1291 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
1292 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1293 "top_eth_sys_sel", "top_eth_xgmii_sel",
1294 "top_eth_mii_sel", "top_netsys_sel",
1295 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1296 "top_netsys_sync_250m_sel",
1297 "top_netsys_ppefb_250m_sel",
1298 "top_netsys_warp_sel";
1299 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1300 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1301 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1302 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1303 <&topckgen CLK_TOP_SGM_0_SEL>,
1304 <&topckgen CLK_TOP_SGM_1_SEL>;
1305 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1306 <&topckgen CLK_TOP_NET1PLL_D4>,
1307 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1308 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1309 <&apmixedsys CLK_APMIXED_SGMPLL>,
1310 <&apmixedsys CLK_APMIXED_SGMPLL>;
1311 mediatek,ethsys = <&ethsys>;
1312 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
1313 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
1314 mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
1315 mediatek,xfi-pll = <&xfi_pll>;
1316 mediatek,infracfg = <&topmisc>;
1317 mediatek,toprgu = <&watchdog>;
1318 #reset-cells = <1>;
1319 #address-cells = <1>;
1320 #size-cells = <0>;
1321
1322 gmac0: mac@0 {
1323 compatible = "mediatek,eth-mac";
1324 reg = <0>;
1325 phy-mode = "internal";
1326 status = "disabled";
1327
1328 fixed-link {
1329 speed = <10000>;
1330 full-duplex;
1331 pause;
1332 };
1333 };
1334
1335 gmac1: mac@1 {
1336 compatible = "mediatek,eth-mac";
1337 reg = <1>;
1338 status = "disabled";
1339 };
1340
1341 gmac2: mac@2 {
1342 compatible = "mediatek,eth-mac";
1343 reg = <2>;
1344 status = "disabled";
1345 };
1346
1347 mdio_bus: mdio-bus {
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1350
1351 /* internal 2.5G PHY */
1352 int_2p5g_phy: ethernet-phy@15 {
1353 compatible = "ethernet-phy-ieee802.3-c45";
1354 reg = <15>;
1355 phy-mode = "internal";
1356 };
1357 };
1358 };
1359
1360 crypto: crypto@15600000 {
1361 compatible = "inside-secure,safexcel-eip197b";
1362 reg = <0 0x15600000 0 0x180000>;
1363 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1367 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1368 status = "okay";
1369 };
1370 };
1371
1372 thermal-zones {
1373 cpu_thermal: cpu-thermal {
1374 polling-delay-passive = <1000>;
1375 polling-delay = <1000>;
1376 thermal-sensors = <&lvts 0>;
1377 trips {
1378 cpu_trip_crit: crit {
1379 temperature = <125000>;
1380 hysteresis = <2000>;
1381 type = "critical";
1382 };
1383
1384 cpu_trip_hot: hot {
1385 temperature = <120000>;
1386 hysteresis = <2000>;
1387 type = "hot";
1388 };
1389
1390 cpu_trip_active_high: active-high {
1391 temperature = <115000>;
1392 hysteresis = <2000>;
1393 type = "active";
1394 };
1395
1396 cpu_trip_active_med: active-med {
1397 temperature = <85000>;
1398 hysteresis = <2000>;
1399 type = "active";
1400 };
1401
1402 cpu_trip_active_low: active-low {
1403 temperature = <40000>;
1404 hysteresis = <2000>;
1405 type = "active";
1406 };
1407 };
1408
1409 cooling-maps {
1410 cpu-active-high {
1411 /* active: set fan to cooling level 2 */
1412 cooling-device = <&fan 3 3>;
1413 trip = <&cpu_trip_active_high>;
1414 };
1415
1416 cpu-active-low {
1417 /* active: set fan to cooling level 1 */
1418 cooling-device = <&fan 2 2>;
1419 trip = <&cpu_trip_active_med>;
1420 };
1421
1422 cpu-passive {
1423 /* passive: set fan to cooling level 0 */
1424 cooling-device = <&fan 1 1>;
1425 trip = <&cpu_trip_active_low>;
1426 };
1427 };
1428 };
1429 };
1430
1431 timer {
1432 compatible = "arm,armv8-timer";
1433 interrupt-parent = <&gic>;
1434 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1435 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1436 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1437 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1438 };
1439 };
Staging tree of Jo-Philipp Wich