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mediatek: filogic: move mt7981 on-SoC blocks to "soc" node in DT
[openwrt/staging/jow.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7981.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 * Author: Jianhui Zhao <zhaojh329@gmail.com>
6 */
7
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
12 #include <dt-bindings/reset/mt7986-resets.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/input/linux-event-codes.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/mux/mux.h>
18
19 / {
20 compatible = "mediatek,mt7981";
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 reg = <0x0>;
34 };
35
36 cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 reg = <0x1>;
41 };
42 };
43
44 soc {
45 compatible = "simple-bus";
46 ranges;
47 #address-cells = <2>;
48 #size-cells = <2>;
49
50 pwm: pwm@10048000 {
51 compatible = "mediatek,mt7981-pwm";
52 reg = <0 0x10048000 0 0x1000>;
53 #pwm-cells = <2>;
54 clocks = <&infracfg CLK_INFRA_PWM_STA>,
55 <&infracfg CLK_INFRA_PWM_HCK>,
56 <&infracfg CLK_INFRA_PWM1_CK>,
57 <&infracfg CLK_INFRA_PWM2_CK>,
58 <&infracfg CLK_INFRA_PWM3_CK>;
59 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
60 };
61
62 thermal: thermal@1100c800 {
63 #thermal-sensor-cells = <1>;
64 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
65 reg = <0 0x1100c800 0 0x800>;
66 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
67 clocks = <&infracfg CLK_INFRA_THERM_CK>,
68 <&infracfg CLK_INFRA_ADC_26M_CK>;
69 clock-names = "therm", "auxadc";
70 mediatek,auxadc = <&auxadc>;
71 mediatek,apmixedsys = <&apmixedsys>;
72 nvmem-cells = <&thermal_calibration>;
73 nvmem-cell-names = "calibration-data";
74 };
75
76 auxadc: adc@1100d000 {
77 compatible = "mediatek,mt7981-auxadc",
78 "mediatek,mt7986-auxadc",
79 "mediatek,mt7622-auxadc";
80 reg = <0 0x1100d000 0 0x1000>;
81 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
82 <&infracfg CLK_INFRA_ADC_FRC_CK>;
83 clock-names = "main", "32k";
84 #io-channel-cells = <1>;
85 };
86
87 wdma: wdma@15104800 {
88 compatible = "mediatek,wed-wdma";
89 reg = <0 0x15104800 0 0x400>,
90 <0 0x15104c00 0 0x400>;
91 };
92
93 ap2woccif: ap2woccif@151a5000 {
94 compatible = "mediatek,ap2woccif";
95 reg = <0 0x151a5000 0 0x1000>,
96 <0 0x151ad000 0 0x1000>;
97 interrupt-parent = <&gic>;
98 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 infracfg: infracfg@10001000 {
103 compatible = "mediatek,mt7981-infracfg", "syscon";
104 reg = <0 0x10001000 0 0x1000>;
105 #clock-cells = <1>;
106 };
107
108 topckgen: topckgen@1001B000 {
109 compatible = "mediatek,mt7981-topckgen", "syscon";
110 reg = <0 0x1001B000 0 0x1000>;
111 #clock-cells = <1>;
112 };
113
114 apmixedsys: apmixedsys@1001E000 {
115 compatible = "mediatek,mt7981-apmixedsys", "syscon";
116 reg = <0 0x1001E000 0 0x1000>;
117 #clock-cells = <1>;
118 };
119
120 watchdog: watchdog@1001c000 {
121 compatible = "mediatek,mt7986-wdt",
122 "mediatek,mt6589-wdt";
123 reg = <0 0x1001c000 0 0x1000>;
124 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
125 #reset-cells = <1>;
126 status = "disabled";
127 };
128
129 gic: interrupt-controller@c000000 {
130 compatible = "arm,gic-v3";
131 #interrupt-cells = <3>;
132 interrupt-parent = <&gic>;
133 interrupt-controller;
134 reg = <0 0x0c000000 0 0x40000>, /* GICD */
135 <0 0x0c080000 0 0x200000>; /* GICR */
136
137 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
138 };
139
140 uart0: serial@11002000 {
141 compatible = "mediatek,mt6577-uart";
142 reg = <0 0x11002000 0 0x400>;
143 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
145 <&infracfg CLK_INFRA_UART0_CK>;
146 clock-names = "baud", "bus";
147 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
148 <&infracfg CLK_INFRA_UART0_SEL>;
149 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
150 <&topckgen CLK_TOP_UART_SEL>;
151 pinctrl-0 = <&uart0_pins>;
152 pinctrl-names = "default";
153 status = "disabled";
154 };
155
156 uart1: serial@11003000 {
157 compatible = "mediatek,mt6577-uart";
158 reg = <0 0x11003000 0 0x400>;
159 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
161 <&infracfg CLK_INFRA_UART1_CK>;
162 clock-names = "baud", "bus";
163 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
164 <&infracfg CLK_INFRA_UART1_SEL>;
165 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
166 <&topckgen CLK_TOP_UART_SEL>;
167 status = "disabled";
168 };
169
170 uart2: serial@11004000 {
171 compatible = "mediatek,mt6577-uart";
172 reg = <0 0x11004000 0 0x400>;
173 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
175 <&infracfg CLK_INFRA_UART2_CK>;
176 clock-names = "baud", "bus";
177 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
178 <&infracfg CLK_INFRA_UART2_SEL>;
179 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
180 <&topckgen CLK_TOP_UART_SEL>;
181 status = "disabled";
182 };
183
184 i2c0: i2c@11007000 {
185 compatible = "mediatek,mt7981-i2c";
186 reg = <0 0x11007000 0 0x1000>,
187 <0 0x10217080 0 0x80>;
188 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
189 clock-div = <1>;
190 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
191 <&infracfg CLK_INFRA_AP_DMA_CK>,
192 <&infracfg CLK_INFRA_I2C_MCK_CK>,
193 <&infracfg CLK_INFRA_I2C_PCK_CK>;
194 clock-names = "main", "dma", "arb", "pmic";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 status = "disabled";
198 };
199
200 pcie: pcie@11280000 {
201 compatible = "mediatek,mt7981-pcie",
202 "mediatek,mt7986-pcie";
203 device_type = "pci";
204 reg = <0 0x11280000 0 0x4000>;
205 reg-names = "pcie-mac";
206 #address-cells = <3>;
207 #size-cells = <2>;
208 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
209 bus-range = <0x00 0xff>;
210 ranges = <0x82000000 0 0x20000000
211 0x0 0x20000000 0 0x10000000>;
212 status = "disabled";
213
214 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
215 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
216 <&infracfg CLK_INFRA_IPCIER_CK>,
217 <&infracfg CLK_INFRA_IPCIEB_CK>;
218
219 phys = <&u3port0 PHY_TYPE_PCIE>;
220 phy-names = "pcie-phy";
221
222 #interrupt-cells = <1>;
223 interrupt-map-mask = <0 0 0 7>;
224 interrupt-map = <0 0 0 1 &pcie_intc 0>,
225 <0 0 0 2 &pcie_intc 1>,
226 <0 0 0 3 &pcie_intc 2>,
227 <0 0 0 4 &pcie_intc 3>;
228 pcie_intc: interrupt-controller {
229 interrupt-controller;
230 #address-cells = <0>;
231 #interrupt-cells = <1>;
232 };
233 };
234
235 crypto: crypto@10320000 {
236 compatible = "inside-secure,safexcel-eip97";
237 reg = <0 0x10320000 0 0x40000>;
238 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-names = "ring0", "ring1", "ring2", "ring3";
243 clocks = <&topckgen CLK_TOP_EIP97B>;
244 clock-names = "top_eip97_ck";
245 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
246 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
247 };
248
249 pio: pinctrl@11d00000 {
250 compatible = "mediatek,mt7981-pinctrl";
251 reg = <0 0x11d00000 0 0x1000>,
252 <0 0x11c00000 0 0x1000>,
253 <0 0x11c10000 0 0x1000>,
254 <0 0x11d20000 0 0x1000>,
255 <0 0x11e00000 0 0x1000>,
256 <0 0x11e20000 0 0x1000>,
257 <0 0x11f00000 0 0x1000>,
258 <0 0x11f10000 0 0x1000>,
259 <0 0x1000b000 0 0x1000>;
260 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
261 "iocfg_rb", "iocfg_lb", "iocfg_bl",
262 "iocfg_tm", "iocfg_tl", "eint";
263 gpio-controller;
264 #gpio-cells = <2>;
265 gpio-ranges = <&pio 0 0 56>;
266 interrupt-controller;
267 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-parent = <&gic>;
269 #interrupt-cells = <2>;
270
271 mdio_pins: mdc-mdio-pins {
272 mux {
273 function = "eth";
274 groups = "smi_mdc_mdio";
275 };
276 };
277
278 uart0_pins: uart0-pins {
279 mux {
280 function = "uart";
281 groups = "uart0";
282 };
283 };
284
285 wifi_dbdc_pins: wifi-dbdc-pins {
286 mux {
287 function = "eth";
288 groups = "wf0_mode1";
289 };
290 conf {
291 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
292 "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
293 "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
294 "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
295 "WF_CBA_RESETB", "WF_DIG_RESETB";
296 drive-strength = <4>;
297 };
298 };
299
300 gbe_led0_pins: gbe-led0-pins {
301 mux {
302 function = "led";
303 groups = "gbe_led0";
304 };
305 };
306
307 gbe_led1_pins: gbe-led1-pins {
308 mux {
309 function = "led";
310 groups = "gbe_led1";
311 };
312 };
313 };
314
315 ethsys: syscon@15000000 {
316 #address-cells = <1>;
317 #size-cells = <1>;
318 compatible = "mediatek,mt7981-ethsys",
319 "syscon";
320 reg = <0 0x15000000 0 0x1000>;
321 #clock-cells = <1>;
322 #reset-cells = <1>;
323 };
324
325 wed: wed@15010000 {
326 compatible = "mediatek,mt7981-wed",
327 "mediatek,mt7986-wed",
328 "syscon";
329 reg = <0 0x15010000 0 0x1000>;
330 interrupt-parent = <&gic>;
331 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
332 memory-region = <&wo_emi0>, <&wo_data>;
333 memory-region-names = "wo-emi", "wo-data";
334 mediatek,wo-ccif = <&wo_ccif0>;
335 mediatek,wo-ilm = <&wo_ilm0>;
336 mediatek,wo-dlm = <&wo_dlm0>;
337 mediatek,wo-cpuboot = <&wo_cpuboot>;
338 };
339
340 eth: ethernet@15100000 {
341 compatible = "mediatek,mt7981-eth";
342 reg = <0 0x15100000 0 0x80000>;
343 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&ethsys CLK_ETH_FE_EN>,
348 <&ethsys CLK_ETH_GP2_EN>,
349 <&ethsys CLK_ETH_GP1_EN>,
350 <&ethsys CLK_ETH_WOCPU0_EN>,
351 <&sgmiisys0 CLK_SGM0_TX_EN>,
352 <&sgmiisys0 CLK_SGM0_RX_EN>,
353 <&sgmiisys0 CLK_SGM0_CK0_EN>,
354 <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
355 <&sgmiisys1 CLK_SGM1_TX_EN>,
356 <&sgmiisys1 CLK_SGM1_RX_EN>,
357 <&sgmiisys1 CLK_SGM1_CK1_EN>,
358 <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
359 <&topckgen CLK_TOP_SGM_REG>,
360 <&topckgen CLK_TOP_NETSYS_SEL>,
361 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
362 clock-names = "fe", "gp2", "gp1", "wocpu0",
363 "sgmii_tx250m", "sgmii_rx250m",
364 "sgmii_cdr_ref", "sgmii_cdr_fb",
365 "sgmii2_tx250m", "sgmii2_rx250m",
366 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
367 "sgmii_ck", "netsys0", "netsys1";
368 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
369 <&topckgen CLK_TOP_SGM_325M_SEL>;
370 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
371 <&topckgen CLK_TOP_CB_SGM_325M>;
372 mediatek,ethsys = <&ethsys>;
373 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
374 mediatek,infracfg = <&topmisc>;
375 mediatek,wed = <&wed>;
376 #reset-cells = <1>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 status = "disabled";
380
381 mdio_bus: mdio-bus {
382 #address-cells = <1>;
383 #size-cells = <0>;
384
385 int_gbe_phy: ethernet-phy@0 {
386 reg = <0>;
387 compatible = "ethernet-phy-ieee802.3-c22";
388 phy-mode = "gmii";
389 phy-is-integrated;
390 nvmem-cells = <&phy_calibration>;
391 nvmem-cell-names = "phy-cal-data";
392
393 leds {
394 #address-cells = <1>;
395 #size-cells = <0>;
396
397 int_gbe_phy_led0: int-gbe-phy-led0@0 {
398 reg = <0>;
399 function = LED_FUNCTION_LAN;
400 status = "disabled";
401 };
402
403 int_gbe_phy_led1: int-gbe-phy-led1@1 {
404 reg = <1>;
405 function = LED_FUNCTION_LAN;
406 status = "disabled";
407 };
408 };
409 };
410 };
411 };
412
413 wo_dlm0: syscon@151e8000 {
414 compatible = "mediatek,mt7986-wo-dlm", "syscon";
415 reg = <0 0x151e8000 0 0x2000>;
416 };
417
418 wo_ilm0: syscon@151e0000 {
419 compatible = "mediatek,mt7986-wo-ilm", "syscon";
420 reg = <0 0x151e0000 0 0x8000>;
421 };
422
423 wo_cpuboot: syscon@15194000 {
424 compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
425 reg = <0 0x15194000 0 0x1000>;
426 };
427
428 wo_ccif0: syscon@151a5000 {
429 compatible = "mediatek,mt7986-wo-ccif", "syscon";
430 reg = <0 0x151a5000 0 0x1000>;
431 interrupt-parent = <&gic>;
432 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
433 };
434
435 sgmiisys0: syscon@10060000 {
436 compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
437 reg = <0 0x10060000 0 0x1000>;
438 mediatek,pnswap;
439 #clock-cells = <1>;
440 };
441
442 sgmiisys1: syscon@10070000 {
443 compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
444 reg = <0 0x10070000 0 0x1000>;
445 #clock-cells = <1>;
446 };
447
448 topmisc: topmisc@11d10000 {
449 compatible = "mediatek,mt7981-topmisc", "syscon";
450 reg = <0 0x11d10000 0 0x10000>;
451 #clock-cells = <1>;
452 };
453
454 snand: snfi@11005000 {
455 compatible = "mediatek,mt7986-snand";
456 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
457 reg-names = "nfi", "ecc";
458 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
460 <&infracfg CLK_INFRA_NFI1_CK>,
461 <&infracfg CLK_INFRA_NFI_HCK_CK>;
462 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
463 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
464 <&topckgen CLK_TOP_NFI1X_SEL>;
465 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
466 <&topckgen CLK_TOP_CB_M_D8>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 status = "disabled";
470 };
471
472 mmc0: mmc@11230000 {
473 compatible = "mediatek,mt7986-mmc",
474 "mediatek,mt7981-mmc";
475 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
476 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
478 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
479 <&infracfg CLK_INFRA_MSDC_66M_CK>,
480 <&infracfg CLK_INFRA_MSDC_133M_CK>;
481 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
482 <&topckgen CLK_TOP_EMMC_400M_SEL>;
483 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
484 <&topckgen CLK_TOP_CB_NET2_D2>;
485 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
486 status = "disabled";
487 };
488
489 wed_pcie: wed_pcie@10003000 {
490 compatible = "mediatek,wed_pcie";
491 reg = <0 0x10003000 0 0x10>;
492 };
493
494 spi0: spi@1100a000 {
495 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
496 #address-cells = <1>;
497 #size-cells = <0>;
498 reg = <0 0x1100a000 0 0x100>;
499 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&topckgen CLK_TOP_CB_M_D2>,
501 <&topckgen CLK_TOP_SPI_SEL>,
502 <&infracfg CLK_INFRA_SPI0_CK>,
503 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
504
505 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
506 status = "disabled";
507 };
508
509 spi1: spi@1100b000 {
510 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
511 #address-cells = <1>;
512 #size-cells = <0>;
513 reg = <0 0x1100b000 0 0x100>;
514 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&topckgen CLK_TOP_CB_M_D2>,
516 <&topckgen CLK_TOP_SPIM_MST_SEL>,
517 <&infracfg CLK_INFRA_SPI1_CK>,
518 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
519 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
520 status = "disabled";
521 };
522
523 spi2: spi@11009000 {
524 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
525 #address-cells = <1>;
526 #size-cells = <0>;
527 reg = <0 0x11009000 0 0x100>;
528 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&topckgen CLK_TOP_CB_M_D2>,
530 <&topckgen CLK_TOP_SPI_SEL>,
531 <&infracfg CLK_INFRA_SPI2_CK>,
532 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
533 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
534 status = "disabled";
535 };
536
537 consys: consys@10000000 {
538 compatible = "mediatek,mt7981-consys";
539 reg = <0 0x10000000 0 0x8600000>;
540 memory-region = <&wmcpu_emi>;
541 };
542
543 xhci: usb@11200000 {
544 compatible = "mediatek,mt7986-xhci",
545 "mediatek,mtk-xhci";
546 reg = <0 0x11200000 0 0x2e00>,
547 <0 0x11203e00 0 0x0100>;
548 reg-names = "mac", "ippc";
549 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
551 <&infracfg CLK_INFRA_IUSB_CK>,
552 <&infracfg CLK_INFRA_IUSB_133_CK>,
553 <&infracfg CLK_INFRA_IUSB_66M_CK>,
554 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
555 clock-names = "sys_ck",
556 "ref_ck",
557 "mcu_ck",
558 "dma_ck",
559 "xhci_ck";
560 phys = <&u2port0 PHY_TYPE_USB2>,
561 <&u3port0 PHY_TYPE_USB3>;
562 vusb33-supply = <&reg_3p3v>;
563 status = "disabled";
564 };
565
566 usb_phy: usb-phy@11e10000 {
567 compatible = "mediatek,mt7981",
568 "mediatek,generic-tphy-v2";
569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges = <0 0 0x11e10000 0x1700>;
572 status = "disabled";
573
574 u2port0: usb-phy@0 {
575 reg = <0x0 0x700>;
576 clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
577 clock-names = "ref";
578 #phy-cells = <1>;
579 };
580
581 u3port0: usb-phy@700 {
582 reg = <0x700 0x900>;
583 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
584 clock-names = "ref";
585 #phy-cells = <1>;
586 mediatek,syscon-type = <&topmisc 0x218 0>;
587 status = "okay";
588 };
589 };
590
591 efuse: efuse@11f20000 {
592 compatible = "mediatek,mt7981-efuse",
593 "mediatek,efuse";
594 reg = <0 0x11f20000 0 0x1000>;
595 #address-cells = <1>;
596 #size-cells = <1>;
597 status = "okay";
598
599 thermal_calibration: thermal-calib@274 {
600 reg = <0x274 0xc>;
601 };
602
603 phy_calibration: phy-calib@8dc {
604 reg = <0x8dc 0x10>;
605 };
606
607 comb_rx_imp_p0: usb3-rx-imp@8c8 {
608 reg = <0x8c8 1>;
609 bits = <0 5>;
610 };
611
612 comb_tx_imp_p0: usb3-tx-imp@8c8 {
613 reg = <0x8c8 2>;
614 bits = <5 5>;
615 };
616
617 comb_intr_p0: usb3-intr@8c9 {
618 reg = <0x8c9 1>;
619 bits = <2 6>;
620 };
621 };
622
623 afe: audio-controller@11210000 {
624 compatible = "mediatek,mt79xx-audio";
625 reg = <0 0x11210000 0 0x9000>;
626 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
628 <&infracfg CLK_INFRA_AUD_26M_CK>,
629 <&infracfg CLK_INFRA_AUD_L_CK>,
630 <&infracfg CLK_INFRA_AUD_AUD_CK>,
631 <&infracfg CLK_INFRA_AUD_EG2_CK>,
632 <&topckgen CLK_TOP_AUD_SEL>;
633 clock-names = "aud_bus_ck",
634 "aud_26m_ck",
635 "aud_l_ck",
636 "aud_aud_ck",
637 "aud_eg2_ck",
638 "aud_sel";
639 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
640 <&topckgen CLK_TOP_A1SYS_SEL>,
641 <&topckgen CLK_TOP_AUD_L_SEL>,
642 <&topckgen CLK_TOP_A_TUNER_SEL>;
643 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
644 <&topckgen CLK_TOP_APLL2_D4>,
645 <&topckgen CLK_TOP_CB_APLL2_196M>,
646 <&topckgen CLK_TOP_APLL2_D4>;
647 status = "disabled";
648 };
649
650 wifi: wifi@18000000 {
651 compatible = "mediatek,mt7981-wmac";
652 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
653 reset-names = "consys";
654 pinctrl-0 = <&wifi_dbdc_pins>;
655 pinctrl-names = "dbdc";
656 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
657 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
658 clock-names = "mcu", "ap2conn";
659 reg = <0 0x18000000 0 0x1000000>,
660 <0 0x10003000 0 0x1000>,
661 <0 0x11d10000 0 0x1000>;
662 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
666 memory-region = <&wmcpu_emi>;
667 status = "disabled";
668 };
669 };
670
671 fan: pwm-fan {
672 compatible = "pwm-fan";
673 /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
674 cooling-levels = <0 63 95 127 159 191 223 255>;
675 #cooling-cells = <2>;
676 status = "disabled";
677 };
678
679 thermal-zones {
680 cpu_thermal: cpu-thermal {
681 polling-delay-passive = <1000>;
682 polling-delay = <1000>;
683 thermal-sensors = <&thermal 0>;
684 trips {
685 cpu_trip_active_highest: active-highest {
686 temperature = <70000>;
687 hysteresis = <2000>;
688 type = "active";
689 };
690
691 cpu_trip_active_high: active-high {
692 temperature = <60000>;
693 hysteresis = <2000>;
694 type = "active";
695 };
696
697 cpu_trip_active_med: active-med {
698 temperature = <50000>;
699 hysteresis = <2000>;
700 type = "active";
701 };
702
703 cpu_trip_active_low: active-low {
704 temperature = <45000>;
705 hysteresis = <2000>;
706 type = "active";
707 };
708
709 cpu_trip_active_lowest: active-lowest {
710 temperature = <40000>;
711 hysteresis = <2000>;
712 type = "active";
713 };
714 };
715
716 cooling-maps {
717 cpu-active-highest {
718 /* active: set fan to cooling level 7 */
719 cooling-device = <&fan 7 7>;
720 trip = <&cpu_trip_active_highest>;
721 };
722
723 cpu-active-high {
724 /* active: set fan to cooling level 5 */
725 cooling-device = <&fan 5 5>;
726 trip = <&cpu_trip_active_high>;
727 };
728
729 cpu-active-med {
730 /* active: set fan to cooling level 3 */
731 cooling-device = <&fan 3 3>;
732 trip = <&cpu_trip_active_med>;
733 };
734
735 cpu-active-low {
736 /* active: set fan to cooling level 2 */
737 cooling-device = <&fan 2 2>;
738 trip = <&cpu_trip_active_low>;
739 };
740
741 cpu-active-lowest {
742 /* active: set fan to cooling level 1 */
743 cooling-device = <&fan 1 1>;
744 trip = <&cpu_trip_active_lowest>;
745 };
746 };
747 };
748 };
749
750 reserved-memory {
751 #address-cells = <2>;
752 #size-cells = <2>;
753 ranges;
754
755 /* 64 KiB reserved for ramoops/pstore */
756 ramoops@42ff0000 {
757 compatible = "ramoops";
758 reg = <0 0x42ff0000 0 0x10000>;
759 record-size = <0x1000>;
760 };
761
762 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
763 secmon_reserved: secmon@43000000 {
764 reg = <0 0x43000000 0 0x30000>;
765 no-map;
766 };
767
768 wmcpu_emi: wmcpu-reserved@47c80000 {
769 reg = <0 0x47c80000 0 0x100000>;
770 no-map;
771 };
772
773 wo_emi0: wo-emi@47d80000 {
774 reg = <0 0x47d80000 0 0x40000>;
775 no-map;
776 };
777
778 wo_data: wo-data@47dc0000 {
779 reg = <0 0x47dc0000 0 0x240000>;
780 no-map;
781 };
782 };
783
784 psci {
785 compatible = "arm,psci-0.2";
786 method = "smc";
787 };
788
789 trng {
790 compatible = "mediatek,mt7981-rng";
791 };
792
793 clk40m: oscillator@0 {
794 compatible = "fixed-clock";
795 #clock-cells = <0>;
796 clock-frequency = <40000000>;
797 clock-output-names = "clkxtal";
798 };
799
800 timer {
801 compatible = "arm,armv8-timer";
802 interrupt-parent = <&gic>;
803 clock-frequency = <13000000>;
804 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
805 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
806 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
807 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
808
809 };
810
811 reg_3p3v: regulator-3p3v {
812 compatible = "regulator-fixed";
813 regulator-name = "fixed-3.3V";
814 regulator-min-microvolt = <3300000>;
815 regulator-max-microvolt = <3300000>;
816 regulator-boot-on;
817 regulator-always-on;
818 };
819
820 ice: ice_debug {
821 compatible = "mediatek,mt7981-ice_debug",
822 "mediatek,mt2701-ice_debug";
823 clocks = <&infracfg CLK_INFRA_DBG_CK>;
824 clock-names = "ice_dbg";
825 };
826 };
Staging tree of Jo-Philipp Wich