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cb7b5d7f9d359a11a195c03e0544882770f2c121
[openwrt/staging/jow.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7981.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 * Author: Jianhui Zhao <zhaojh329@gmail.com>
6 */
7
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
12 #include <dt-bindings/reset/mt7986-resets.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/input/linux-event-codes.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/mux/mux.h>
18
19 / {
20 compatible = "mediatek,mt7981";
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 compatible = "arm,cortex-a53";
31 reg = <0x0>;
32 device_type = "cpu";
33 enable-method = "psci";
34 };
35
36 cpu@1 {
37 compatible = "arm,cortex-a53";
38 reg = <0x1>;
39 device_type = "cpu";
40 enable-method = "psci";
41 };
42 };
43
44 ice: ice_debug {
45 compatible = "mediatek,mt7981-ice_debug",
46 "mediatek,mt2701-ice_debug";
47 clocks = <&infracfg CLK_INFRA_DBG_CK>;
48 clock-names = "ice_dbg";
49 };
50
51 clk40m: oscillator@0 {
52 compatible = "fixed-clock";
53 clock-frequency = <40000000>;
54 clock-output-names = "clkxtal";
55 #clock-cells = <0>;
56 };
57
58 psci {
59 compatible = "arm,psci-0.2";
60 method = "smc";
61 };
62
63 fan: pwm-fan {
64 compatible = "pwm-fan";
65 /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
66 cooling-levels = <0 63 95 127 159 191 223 255>;
67 #cooling-cells = <2>;
68 status = "disabled";
69 };
70
71 reg_3p3v: regulator-3p3v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-3.3V";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 regulator-boot-on;
77 regulator-always-on;
78 };
79
80 reserved-memory {
81 ranges;
82 #address-cells = <2>;
83 #size-cells = <2>;
84
85 /* 64 KiB reserved for ramoops/pstore */
86 ramoops@42ff0000 {
87 compatible = "ramoops";
88 reg = <0 0x42ff0000 0 0x10000>;
89 record-size = <0x1000>;
90 };
91
92 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
93 secmon_reserved: secmon@43000000 {
94 reg = <0 0x43000000 0 0x30000>;
95 no-map;
96 };
97
98 wmcpu_emi: wmcpu-reserved@47c80000 {
99 reg = <0 0x47c80000 0 0x100000>;
100 no-map;
101 };
102
103 wo_emi0: wo-emi@47d80000 {
104 reg = <0 0x47d80000 0 0x40000>;
105 no-map;
106 };
107
108 wo_data: wo-data@47dc0000 {
109 reg = <0 0x47dc0000 0 0x240000>;
110 no-map;
111 };
112 };
113
114 soc {
115 compatible = "simple-bus";
116 ranges;
117 #address-cells = <2>;
118 #size-cells = <2>;
119
120 gic: interrupt-controller@c000000 {
121 compatible = "arm,gic-v3";
122 reg = <0 0x0c000000 0 0x40000>, /* GICD */
123 <0 0x0c080000 0 0x200000>; /* GICR */
124 interrupt-parent = <&gic>;
125 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
126 interrupt-controller;
127 #interrupt-cells = <3>;
128 };
129
130 consys: consys@10000000 {
131 compatible = "mediatek,mt7981-consys";
132 reg = <0 0x10000000 0 0x8600000>;
133 memory-region = <&wmcpu_emi>;
134 };
135
136 infracfg: infracfg@10001000 {
137 compatible = "mediatek,mt7981-infracfg", "syscon";
138 reg = <0 0x10001000 0 0x1000>;
139 #clock-cells = <1>;
140 };
141
142 wed_pcie: wed_pcie@10003000 {
143 compatible = "mediatek,wed_pcie";
144 reg = <0 0x10003000 0 0x10>;
145 };
146
147 topckgen: topckgen@1001B000 {
148 compatible = "mediatek,mt7981-topckgen", "syscon";
149 reg = <0 0x1001B000 0 0x1000>;
150 #clock-cells = <1>;
151 };
152
153 watchdog: watchdog@1001c000 {
154 compatible = "mediatek,mt7986-wdt",
155 "mediatek,mt6589-wdt";
156 reg = <0 0x1001c000 0 0x1000>;
157 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
158 #reset-cells = <1>;
159 status = "disabled";
160 };
161
162 apmixedsys: apmixedsys@1001E000 {
163 compatible = "mediatek,mt7981-apmixedsys", "syscon";
164 reg = <0 0x1001E000 0 0x1000>;
165 #clock-cells = <1>;
166 };
167
168 pwm: pwm@10048000 {
169 compatible = "mediatek,mt7981-pwm";
170 reg = <0 0x10048000 0 0x1000>;
171 clocks = <&infracfg CLK_INFRA_PWM_STA>,
172 <&infracfg CLK_INFRA_PWM_HCK>,
173 <&infracfg CLK_INFRA_PWM1_CK>,
174 <&infracfg CLK_INFRA_PWM2_CK>,
175 <&infracfg CLK_INFRA_PWM3_CK>;
176 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
177 #pwm-cells = <2>;
178 };
179
180 sgmiisys0: syscon@10060000 {
181 compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
182 reg = <0 0x10060000 0 0x1000>;
183 mediatek,pnswap;
184 #clock-cells = <1>;
185 };
186
187 sgmiisys1: syscon@10070000 {
188 compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
189 reg = <0 0x10070000 0 0x1000>;
190 #clock-cells = <1>;
191 };
192
193 crypto: crypto@10320000 {
194 compatible = "inside-secure,safexcel-eip97";
195 reg = <0 0x10320000 0 0x40000>;
196 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
200 interrupt-names = "ring0", "ring1", "ring2", "ring3";
201 clocks = <&topckgen CLK_TOP_EIP97B>;
202 clock-names = "top_eip97_ck";
203 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
204 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
205 };
206
207 uart0: serial@11002000 {
208 compatible = "mediatek,mt6577-uart";
209 reg = <0 0x11002000 0 0x400>;
210 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
212 <&infracfg CLK_INFRA_UART0_CK>;
213 clock-names = "baud", "bus";
214 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
215 <&infracfg CLK_INFRA_UART0_SEL>;
216 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
217 <&topckgen CLK_TOP_UART_SEL>;
218 pinctrl-0 = <&uart0_pins>;
219 pinctrl-names = "default";
220 status = "disabled";
221 };
222
223 uart1: serial@11003000 {
224 compatible = "mediatek,mt6577-uart";
225 reg = <0 0x11003000 0 0x400>;
226 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
228 <&infracfg CLK_INFRA_UART1_CK>;
229 clock-names = "baud", "bus";
230 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
231 <&infracfg CLK_INFRA_UART1_SEL>;
232 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
233 <&topckgen CLK_TOP_UART_SEL>;
234 status = "disabled";
235 };
236
237 uart2: serial@11004000 {
238 compatible = "mediatek,mt6577-uart";
239 reg = <0 0x11004000 0 0x400>;
240 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
242 <&infracfg CLK_INFRA_UART2_CK>;
243 clock-names = "baud", "bus";
244 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
245 <&infracfg CLK_INFRA_UART2_SEL>;
246 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
247 <&topckgen CLK_TOP_UART_SEL>;
248 status = "disabled";
249 };
250
251 snand: snfi@11005000 {
252 compatible = "mediatek,mt7986-snand";
253 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
254 reg-names = "nfi", "ecc";
255 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
257 <&infracfg CLK_INFRA_NFI1_CK>,
258 <&infracfg CLK_INFRA_NFI_HCK_CK>;
259 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
260 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
261 <&topckgen CLK_TOP_NFI1X_SEL>;
262 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
263 <&topckgen CLK_TOP_CB_M_D8>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 status = "disabled";
267 };
268
269 i2c0: i2c@11007000 {
270 compatible = "mediatek,mt7981-i2c";
271 reg = <0 0x11007000 0 0x1000>,
272 <0 0x10217080 0 0x80>;
273 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
274 clock-div = <1>;
275 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
276 <&infracfg CLK_INFRA_AP_DMA_CK>,
277 <&infracfg CLK_INFRA_I2C_MCK_CK>,
278 <&infracfg CLK_INFRA_I2C_PCK_CK>;
279 clock-names = "main", "dma", "arb", "pmic";
280 #address-cells = <1>;
281 #size-cells = <0>;
282 status = "disabled";
283 };
284
285 spi2: spi@11009000 {
286 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
287 reg = <0 0x11009000 0 0x100>;
288 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&topckgen CLK_TOP_CB_M_D2>,
290 <&topckgen CLK_TOP_SPI_SEL>,
291 <&infracfg CLK_INFRA_SPI2_CK>,
292 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
293 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 status = "disabled";
297 };
298
299 spi0: spi@1100a000 {
300 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
301 reg = <0 0x1100a000 0 0x100>;
302 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&topckgen CLK_TOP_CB_M_D2>,
304 <&topckgen CLK_TOP_SPI_SEL>,
305 <&infracfg CLK_INFRA_SPI0_CK>,
306 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
307
308 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312 };
313
314 spi1: spi@1100b000 {
315 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
316 reg = <0 0x1100b000 0 0x100>;
317 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&topckgen CLK_TOP_CB_M_D2>,
319 <&topckgen CLK_TOP_SPIM_MST_SEL>,
320 <&infracfg CLK_INFRA_SPI1_CK>,
321 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
322 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
323 #address-cells = <1>;
324 #size-cells = <0>;
325 status = "disabled";
326 };
327
328 thermal: thermal@1100c800 {
329 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
330 reg = <0 0x1100c800 0 0x800>;
331 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&infracfg CLK_INFRA_THERM_CK>,
333 <&infracfg CLK_INFRA_ADC_26M_CK>;
334 clock-names = "therm", "auxadc";
335 nvmem-cells = <&thermal_calibration>;
336 nvmem-cell-names = "calibration-data";
337 #thermal-sensor-cells = <1>;
338 mediatek,auxadc = <&auxadc>;
339 mediatek,apmixedsys = <&apmixedsys>;
340 };
341
342 auxadc: adc@1100d000 {
343 compatible = "mediatek,mt7981-auxadc",
344 "mediatek,mt7986-auxadc",
345 "mediatek,mt7622-auxadc";
346 reg = <0 0x1100d000 0 0x1000>;
347 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
348 <&infracfg CLK_INFRA_ADC_FRC_CK>;
349 clock-names = "main", "32k";
350 #io-channel-cells = <1>;
351 };
352
353 xhci: usb@11200000 {
354 compatible = "mediatek,mt7986-xhci",
355 "mediatek,mtk-xhci";
356 reg = <0 0x11200000 0 0x2e00>,
357 <0 0x11203e00 0 0x0100>;
358 reg-names = "mac", "ippc";
359 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
361 <&infracfg CLK_INFRA_IUSB_CK>,
362 <&infracfg CLK_INFRA_IUSB_133_CK>,
363 <&infracfg CLK_INFRA_IUSB_66M_CK>,
364 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
365 clock-names = "sys_ck",
366 "ref_ck",
367 "mcu_ck",
368 "dma_ck",
369 "xhci_ck";
370 phys = <&u2port0 PHY_TYPE_USB2>,
371 <&u3port0 PHY_TYPE_USB3>;
372 vusb33-supply = <&reg_3p3v>;
373 status = "disabled";
374 };
375
376 afe: audio-controller@11210000 {
377 compatible = "mediatek,mt79xx-audio";
378 reg = <0 0x11210000 0 0x9000>;
379 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
381 <&infracfg CLK_INFRA_AUD_26M_CK>,
382 <&infracfg CLK_INFRA_AUD_L_CK>,
383 <&infracfg CLK_INFRA_AUD_AUD_CK>,
384 <&infracfg CLK_INFRA_AUD_EG2_CK>,
385 <&topckgen CLK_TOP_AUD_SEL>;
386 clock-names = "aud_bus_ck",
387 "aud_26m_ck",
388 "aud_l_ck",
389 "aud_aud_ck",
390 "aud_eg2_ck",
391 "aud_sel";
392 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
393 <&topckgen CLK_TOP_A1SYS_SEL>,
394 <&topckgen CLK_TOP_AUD_L_SEL>,
395 <&topckgen CLK_TOP_A_TUNER_SEL>;
396 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
397 <&topckgen CLK_TOP_APLL2_D4>,
398 <&topckgen CLK_TOP_CB_APLL2_196M>,
399 <&topckgen CLK_TOP_APLL2_D4>;
400 status = "disabled";
401 };
402
403 mmc0: mmc@11230000 {
404 compatible = "mediatek,mt7986-mmc",
405 "mediatek,mt7981-mmc";
406 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
407 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
409 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
410 <&infracfg CLK_INFRA_MSDC_66M_CK>,
411 <&infracfg CLK_INFRA_MSDC_133M_CK>;
412 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
413 <&topckgen CLK_TOP_EMMC_400M_SEL>;
414 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
415 <&topckgen CLK_TOP_CB_NET2_D2>;
416 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
417 status = "disabled";
418 };
419
420 pcie: pcie@11280000 {
421 compatible = "mediatek,mt7981-pcie",
422 "mediatek,mt7986-pcie";
423 reg = <0 0x11280000 0 0x4000>;
424 reg-names = "pcie-mac";
425 ranges = <0x82000000 0 0x20000000
426 0x0 0x20000000 0 0x10000000>;
427 device_type = "pci";
428 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
429 bus-range = <0x00 0xff>;
430
431 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
432 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
433 <&infracfg CLK_INFRA_IPCIER_CK>,
434 <&infracfg CLK_INFRA_IPCIEB_CK>;
435
436 phys = <&u3port0 PHY_TYPE_PCIE>;
437 phy-names = "pcie-phy";
438
439 interrupt-map-mask = <0 0 0 7>;
440 interrupt-map = <0 0 0 1 &pcie_intc 0>,
441 <0 0 0 2 &pcie_intc 1>,
442 <0 0 0 3 &pcie_intc 2>,
443 <0 0 0 4 &pcie_intc 3>;
444 #interrupt-cells = <1>;
445 #address-cells = <3>;
446 #size-cells = <2>;
447 status = "disabled";
448 pcie_intc: interrupt-controller {
449 interrupt-controller;
450 #interrupt-cells = <1>;
451 #address-cells = <0>;
452 };
453 };
454
455 pio: pinctrl@11d00000 {
456 compatible = "mediatek,mt7981-pinctrl";
457 reg = <0 0x11d00000 0 0x1000>,
458 <0 0x11c00000 0 0x1000>,
459 <0 0x11c10000 0 0x1000>,
460 <0 0x11d20000 0 0x1000>,
461 <0 0x11e00000 0 0x1000>,
462 <0 0x11e20000 0 0x1000>,
463 <0 0x11f00000 0 0x1000>,
464 <0 0x11f10000 0 0x1000>,
465 <0 0x1000b000 0 0x1000>;
466 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
467 "iocfg_rb", "iocfg_lb", "iocfg_bl",
468 "iocfg_tm", "iocfg_tl", "eint";
469 gpio-controller;
470 #gpio-cells = <2>;
471 gpio-ranges = <&pio 0 0 56>;
472 interrupt-controller;
473 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-parent = <&gic>;
475 #interrupt-cells = <2>;
476
477 mdio_pins: mdc-mdio-pins {
478 mux {
479 function = "eth";
480 groups = "smi_mdc_mdio";
481 };
482 };
483
484 uart0_pins: uart0-pins {
485 mux {
486 function = "uart";
487 groups = "uart0";
488 };
489 };
490
491 wifi_dbdc_pins: wifi-dbdc-pins {
492 mux {
493 function = "eth";
494 groups = "wf0_mode1";
495 };
496 conf {
497 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
498 "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
499 "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
500 "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
501 "WF_CBA_RESETB", "WF_DIG_RESETB";
502 drive-strength = <4>;
503 };
504 };
505
506 gbe_led0_pins: gbe-led0-pins {
507 mux {
508 function = "led";
509 groups = "gbe_led0";
510 };
511 };
512
513 gbe_led1_pins: gbe-led1-pins {
514 mux {
515 function = "led";
516 groups = "gbe_led1";
517 };
518 };
519 };
520
521 topmisc: topmisc@11d10000 {
522 compatible = "mediatek,mt7981-topmisc", "syscon";
523 reg = <0 0x11d10000 0 0x10000>;
524 #clock-cells = <1>;
525 };
526
527 usb_phy: usb-phy@11e10000 {
528 compatible = "mediatek,mt7981",
529 "mediatek,generic-tphy-v2";
530 ranges = <0 0 0x11e10000 0x1700>;
531 #address-cells = <1>;
532 #size-cells = <1>;
533 status = "disabled";
534
535 u2port0: usb-phy@0 {
536 reg = <0x0 0x700>;
537 clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
538 clock-names = "ref";
539 #phy-cells = <1>;
540 };
541
542 u3port0: usb-phy@700 {
543 reg = <0x700 0x900>;
544 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
545 clock-names = "ref";
546 #phy-cells = <1>;
547 mediatek,syscon-type = <&topmisc 0x218 0>;
548 status = "okay";
549 };
550 };
551
552 efuse: efuse@11f20000 {
553 compatible = "mediatek,mt7981-efuse",
554 "mediatek,efuse";
555 reg = <0 0x11f20000 0 0x1000>;
556 #address-cells = <1>;
557 #size-cells = <1>;
558 status = "okay";
559
560 thermal_calibration: thermal-calib@274 {
561 reg = <0x274 0xc>;
562 };
563
564 phy_calibration: phy-calib@8dc {
565 reg = <0x8dc 0x10>;
566 };
567
568 comb_rx_imp_p0: usb3-rx-imp@8c8 {
569 reg = <0x8c8 1>;
570 bits = <0 5>;
571 };
572
573 comb_tx_imp_p0: usb3-tx-imp@8c8 {
574 reg = <0x8c8 2>;
575 bits = <5 5>;
576 };
577
578 comb_intr_p0: usb3-intr@8c9 {
579 reg = <0x8c9 1>;
580 bits = <2 6>;
581 };
582 };
583
584 ethsys: syscon@15000000 {
585 compatible = "mediatek,mt7981-ethsys",
586 "syscon";
587 reg = <0 0x15000000 0 0x1000>;
588 #clock-cells = <1>;
589 #reset-cells = <1>;
590 #address-cells = <1>;
591 #size-cells = <1>;
592 };
593
594 wed: wed@15010000 {
595 compatible = "mediatek,mt7981-wed",
596 "mediatek,mt7986-wed",
597 "syscon";
598 reg = <0 0x15010000 0 0x1000>;
599 interrupt-parent = <&gic>;
600 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
601 memory-region = <&wo_emi0>, <&wo_data>;
602 memory-region-names = "wo-emi", "wo-data";
603 mediatek,wo-ccif = <&wo_ccif0>;
604 mediatek,wo-ilm = <&wo_ilm0>;
605 mediatek,wo-dlm = <&wo_dlm0>;
606 mediatek,wo-cpuboot = <&wo_cpuboot>;
607 };
608
609 eth: ethernet@15100000 {
610 compatible = "mediatek,mt7981-eth";
611 reg = <0 0x15100000 0 0x80000>;
612 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&ethsys CLK_ETH_FE_EN>,
617 <&ethsys CLK_ETH_GP2_EN>,
618 <&ethsys CLK_ETH_GP1_EN>,
619 <&ethsys CLK_ETH_WOCPU0_EN>,
620 <&sgmiisys0 CLK_SGM0_TX_EN>,
621 <&sgmiisys0 CLK_SGM0_RX_EN>,
622 <&sgmiisys0 CLK_SGM0_CK0_EN>,
623 <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
624 <&sgmiisys1 CLK_SGM1_TX_EN>,
625 <&sgmiisys1 CLK_SGM1_RX_EN>,
626 <&sgmiisys1 CLK_SGM1_CK1_EN>,
627 <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
628 <&topckgen CLK_TOP_SGM_REG>,
629 <&topckgen CLK_TOP_NETSYS_SEL>,
630 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
631 clock-names = "fe", "gp2", "gp1", "wocpu0",
632 "sgmii_tx250m", "sgmii_rx250m",
633 "sgmii_cdr_ref", "sgmii_cdr_fb",
634 "sgmii2_tx250m", "sgmii2_rx250m",
635 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
636 "sgmii_ck", "netsys0", "netsys1";
637 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
638 <&topckgen CLK_TOP_SGM_325M_SEL>;
639 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
640 <&topckgen CLK_TOP_CB_SGM_325M>;
641 mediatek,ethsys = <&ethsys>;
642 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
643 mediatek,infracfg = <&topmisc>;
644 mediatek,wed = <&wed>;
645 #reset-cells = <1>;
646 #address-cells = <1>;
647 #size-cells = <0>;
648 status = "disabled";
649
650 mdio_bus: mdio-bus {
651 #address-cells = <1>;
652 #size-cells = <0>;
653
654 int_gbe_phy: ethernet-phy@0 {
655 compatible = "ethernet-phy-ieee802.3-c22";
656 reg = <0>;
657 phy-mode = "gmii";
658 phy-is-integrated;
659 nvmem-cells = <&phy_calibration>;
660 nvmem-cell-names = "phy-cal-data";
661
662 leds {
663 #address-cells = <1>;
664 #size-cells = <0>;
665
666 int_gbe_phy_led0: int-gbe-phy-led0@0 {
667 reg = <0>;
668 function = LED_FUNCTION_LAN;
669 status = "disabled";
670 };
671
672 int_gbe_phy_led1: int-gbe-phy-led1@1 {
673 reg = <1>;
674 function = LED_FUNCTION_LAN;
675 status = "disabled";
676 };
677 };
678 };
679 };
680 };
681
682 wdma: wdma@15104800 {
683 compatible = "mediatek,wed-wdma";
684 reg = <0 0x15104800 0 0x400>,
685 <0 0x15104c00 0 0x400>;
686 };
687
688 wo_cpuboot: syscon@15194000 {
689 compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
690 reg = <0 0x15194000 0 0x1000>;
691 };
692
693 ap2woccif: ap2woccif@151a5000 {
694 compatible = "mediatek,ap2woccif";
695 reg = <0 0x151a5000 0 0x1000>,
696 <0 0x151ad000 0 0x1000>;
697 interrupt-parent = <&gic>;
698 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
700 };
701
702 wo_ccif0: syscon@151a5000 {
703 compatible = "mediatek,mt7986-wo-ccif", "syscon";
704 reg = <0 0x151a5000 0 0x1000>;
705 interrupt-parent = <&gic>;
706 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
707 };
708
709 wo_ilm0: syscon@151e0000 {
710 compatible = "mediatek,mt7986-wo-ilm", "syscon";
711 reg = <0 0x151e0000 0 0x8000>;
712 };
713
714 wo_dlm0: syscon@151e8000 {
715 compatible = "mediatek,mt7986-wo-dlm", "syscon";
716 reg = <0 0x151e8000 0 0x2000>;
717 };
718
719 wifi: wifi@18000000 {
720 compatible = "mediatek,mt7981-wmac";
721 reg = <0 0x18000000 0 0x1000000>,
722 <0 0x10003000 0 0x1000>,
723 <0 0x11d10000 0 0x1000>;
724 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
725 reset-names = "consys";
726 pinctrl-0 = <&wifi_dbdc_pins>;
727 pinctrl-names = "dbdc";
728 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
729 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
730 clock-names = "mcu", "ap2conn";
731 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
735 memory-region = <&wmcpu_emi>;
736 status = "disabled";
737 };
738 };
739
740 thermal-zones {
741 cpu_thermal: cpu-thermal {
742 polling-delay-passive = <1000>;
743 polling-delay = <1000>;
744 thermal-sensors = <&thermal 0>;
745 trips {
746 cpu_trip_active_highest: active-highest {
747 temperature = <70000>;
748 hysteresis = <2000>;
749 type = "active";
750 };
751
752 cpu_trip_active_high: active-high {
753 temperature = <60000>;
754 hysteresis = <2000>;
755 type = "active";
756 };
757
758 cpu_trip_active_med: active-med {
759 temperature = <50000>;
760 hysteresis = <2000>;
761 type = "active";
762 };
763
764 cpu_trip_active_low: active-low {
765 temperature = <45000>;
766 hysteresis = <2000>;
767 type = "active";
768 };
769
770 cpu_trip_active_lowest: active-lowest {
771 temperature = <40000>;
772 hysteresis = <2000>;
773 type = "active";
774 };
775 };
776
777 cooling-maps {
778 cpu-active-highest {
779 /* active: set fan to cooling level 7 */
780 cooling-device = <&fan 7 7>;
781 trip = <&cpu_trip_active_highest>;
782 };
783
784 cpu-active-high {
785 /* active: set fan to cooling level 5 */
786 cooling-device = <&fan 5 5>;
787 trip = <&cpu_trip_active_high>;
788 };
789
790 cpu-active-med {
791 /* active: set fan to cooling level 3 */
792 cooling-device = <&fan 3 3>;
793 trip = <&cpu_trip_active_med>;
794 };
795
796 cpu-active-low {
797 /* active: set fan to cooling level 2 */
798 cooling-device = <&fan 2 2>;
799 trip = <&cpu_trip_active_low>;
800 };
801
802 cpu-active-lowest {
803 /* active: set fan to cooling level 1 */
804 cooling-device = <&fan 1 1>;
805 trip = <&cpu_trip_active_lowest>;
806 };
807 };
808 };
809 };
810
811 timer {
812 compatible = "arm,armv8-timer";
813 interrupt-parent = <&gic>;
814 clock-frequency = <13000000>;
815 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
816 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
817 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
818 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
819
820 };
821
822 trng {
823 compatible = "mediatek,mt7981-rng";
824 };
825 };
Staging tree of Jo-Philipp Wich