target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2020 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  * Author: Jianhui Zhao <zhaojh329@gmail.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/phy/phy.h>
  11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
  12 #include <dt-bindings/reset/mt7986-resets.h>
  13 #include <dt-bindings/pinctrl/mt65xx.h>
  14 #include <dt-bindings/leds/common.h>
  15 #include <dt-bindings/input/linux-event-codes.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/mux/mux.h>
  18
  19 / {
  20         compatible = "mediatek,mt7981";
  21         interrupt-parent = <&gic>;
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a53";
  32                         enable-method = "psci";
  33                         reg = <0x0>;
  34                 };
  35
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         enable-method = "psci";
  40                         reg = <0x1>;
  41                 };
  42         };
  43
  44         pwm: pwm@10048000 {
  45                 compatible = "mediatek,mt7981-pwm";
  46                 reg = <0 0x10048000 0 0x1000>;
  47                 #pwm-cells = <2>;
  48                 clocks = <&infracfg CLK_INFRA_PWM_STA>,
  49                          <&infracfg CLK_INFRA_PWM_HCK>,
  50                          <&infracfg CLK_INFRA_PWM1_CK>,
  51                          <&infracfg CLK_INFRA_PWM2_CK>,
  52                          <&infracfg CLK_INFRA_PWM3_CK>;
  53                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
  54         };
  55
  56         fan: pwm-fan {
  57                 compatible = "pwm-fan";
  58                 /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
  59                 cooling-levels = <0 63 95 127 159 191 223 255>;
  60                 #cooling-cells = <2>;
  61                 status = "disabled";
  62         };
  63
  64         thermal-zones {
  65                 cpu_thermal: cpu-thermal {
  66                         polling-delay-passive = <1000>;
  67                         polling-delay = <1000>;
  68                         thermal-sensors = <&thermal 0>;
  69                         trips {
  70                                 cpu_trip_active_highest: active-highest {
  71                                         temperature = <70000>;
  72                                         hysteresis = <2000>;
  73                                         type = "active";
  74                                 };
  75
  76                                 cpu_trip_active_high: active-high {
  77                                         temperature = <60000>;
  78                                         hysteresis = <2000>;
  79                                         type = "active";
  80                                 };
  81
  82                                 cpu_trip_active_med: active-med {
  83                                         temperature = <50000>;
  84                                         hysteresis = <2000>;
  85                                         type = "active";
  86                                 };
  87
  88                                 cpu_trip_active_low: active-low {
  89                                         temperature = <45000>;
  90                                         hysteresis = <2000>;
  91                                         type = "active";
  92                                 };
  93
  94                                 cpu_trip_active_lowest: active-lowest {
  95                                         temperature = <40000>;
  96                                         hysteresis = <2000>;
  97                                         type = "active";
  98                                 };
  99                         };
 100
 101                         cooling-maps {
 102                                 cpu-active-highest {
 103                                         /* active: set fan to cooling level 7 */
 104                                         cooling-device = <&fan 7 7>;
 105                                         trip = <&cpu_trip_active_highest>;
 106                                 };
 107
 108                                 cpu-active-high {
 109                                         /* active: set fan to cooling level 5 */
 110                                         cooling-device = <&fan 5 5>;
 111                                         trip = <&cpu_trip_active_high>;
 112                                 };
 113
 114                                 cpu-active-med {
 115                                         /* active: set fan to cooling level 3 */
 116                                         cooling-device = <&fan 3 3>;
 117                                         trip = <&cpu_trip_active_med>;
 118                                 };
 119
 120                                 cpu-active-low {
 121                                         /* active: set fan to cooling level 2 */
 122                                         cooling-device = <&fan 2 2>;
 123                                         trip = <&cpu_trip_active_low>;
 124                                 };
 125
 126                                 cpu-active-lowest {
 127                                         /* active: set fan to cooling level 1 */
 128                                         cooling-device = <&fan 1 1>;
 129                                         trip = <&cpu_trip_active_lowest>;
 130                                 };
 131                         };
 132                 };
 133         };
 134
 135         thermal: thermal@1100c800 {
 136                 #thermal-sensor-cells = <1>;
 137                 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
 138                 reg = <0 0x1100c800 0 0x800>;
 139                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 140                 clocks = <&infracfg CLK_INFRA_THERM_CK>,
 141                          <&infracfg CLK_INFRA_ADC_26M_CK>;
 142                 clock-names = "therm", "auxadc";
 143                 mediatek,auxadc = <&auxadc>;
 144                 mediatek,apmixedsys = <&apmixedsys>;
 145                 nvmem-cells = <&thermal_calibration>;
 146                 nvmem-cell-names = "calibration-data";
 147         };
 148
 149         auxadc: adc@1100d000 {
 150                 compatible = "mediatek,mt7981-auxadc",
 151                              "mediatek,mt7986-auxadc",
 152                              "mediatek,mt7622-auxadc";
 153                 reg = <0 0x1100d000 0 0x1000>;
 154                 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
 155                          <&infracfg CLK_INFRA_ADC_FRC_CK>;
 156                 clock-names = "main", "32k";
 157                 #io-channel-cells = <1>;
 158         };
 159
 160         wdma: wdma@15104800 {
 161                 compatible = "mediatek,wed-wdma";
 162                 reg = <0 0x15104800 0 0x400>,
 163                       <0 0x15104c00 0 0x400>;
 164         };
 165
 166         ap2woccif: ap2woccif@151a5000 {
 167                 compatible = "mediatek,ap2woccif";
 168                 reg = <0 0x151a5000 0 0x1000>,
 169                       <0 0x151ad000 0 0x1000>;
 170                 interrupt-parent = <&gic>;
 171                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 173         };
 174
 175         reserved-memory {
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges;
 179
 180                 /* 64 KiB reserved for ramoops/pstore */
 181                 ramoops@42ff0000 {
 182                         compatible = "ramoops";
 183                         reg = <0 0x42ff0000 0 0x10000>;
 184                         record-size = <0x1000>;
 185                 };
 186
 187                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 188                 secmon_reserved: secmon@43000000 {
 189                         reg = <0 0x43000000 0 0x30000>;
 190                         no-map;
 191                 };
 192
 193                 wmcpu_emi: wmcpu-reserved@47c80000 {
 194                         reg = <0 0x47c80000 0 0x100000>;
 195                         no-map;
 196                 };
 197
 198                 wo_emi0: wo-emi@47d80000 {
 199                         reg = <0 0x47d80000 0 0x40000>;
 200                         no-map;
 201                 };
 202
 203                 wo_data: wo-data@47dc0000 {
 204                         reg = <0 0x47dc0000 0 0x240000>;
 205                         no-map;
 206                 };
 207         };
 208
 209         psci {
 210                 compatible  = "arm,psci-0.2";
 211                 method      = "smc";
 212         };
 213
 214         trng {
 215                 compatible = "mediatek,mt7981-rng";
 216         };
 217
 218         clk40m: oscillator@0 {
 219                 compatible = "fixed-clock";
 220                 #clock-cells = <0>;
 221                 clock-frequency = <40000000>;
 222                 clock-output-names = "clkxtal";
 223         };
 224
 225         infracfg: infracfg@10001000 {
 226                 compatible = "mediatek,mt7981-infracfg", "syscon";
 227                 reg = <0 0x10001000 0 0x1000>;
 228                 #clock-cells = <1>;
 229         };
 230
 231         topckgen: topckgen@1001B000 {
 232                 compatible = "mediatek,mt7981-topckgen", "syscon";
 233                 reg = <0 0x1001B000 0 0x1000>;
 234                 #clock-cells = <1>;
 235         };
 236
 237         apmixedsys: apmixedsys@1001E000 {
 238                 compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
 239                 reg = <0 0x1001E000 0 0x1000>;
 240                 #clock-cells = <1>;
 241         };
 242
 243         timer {
 244                 compatible = "arm,armv8-timer";
 245                 interrupt-parent = <&gic>;
 246                 clock-frequency = <13000000>;
 247                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 249                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 250                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 251
 252         };
 253
 254         watchdog: watchdog@1001c000 {
 255                 compatible = "mediatek,mt7986-wdt",
 256                              "mediatek,mt6589-wdt";
 257                 reg = <0 0x1001c000 0 0x1000>;
 258                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 259                 #reset-cells = <1>;
 260                 status = "disabled";
 261         };
 262
 263         gic: interrupt-controller@c000000 {
 264                 compatible = "arm,gic-v3";
 265                 #interrupt-cells = <3>;
 266                 interrupt-parent = <&gic>;
 267                 interrupt-controller;
 268                 reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 269                       <0 0x0c080000 0 0x200000>; /* GICR */
 270
 271                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 272         };
 273
 274         uart0: serial@11002000 {
 275                 compatible = "mediatek,mt6577-uart";
 276                 reg = <0 0x11002000 0 0x400>;
 277                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 279                         <&infracfg CLK_INFRA_UART0_CK>;
 280                 clock-names = "baud", "bus";
 281                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 282                                   <&infracfg CLK_INFRA_UART0_SEL>;
 283                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 284                                          <&topckgen CLK_TOP_UART_SEL>;
 285                 pinctrl-0 = <&uart0_pins>;
 286                 pinctrl-names = "default";
 287                 status = "disabled";
 288         };
 289
 290         uart1: serial@11003000 {
 291                 compatible = "mediatek,mt6577-uart";
 292                 reg = <0 0x11003000 0 0x400>;
 293                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 295                         <&infracfg CLK_INFRA_UART1_CK>;
 296                 clock-names = "baud", "bus";
 297                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 298                                   <&infracfg CLK_INFRA_UART1_SEL>;
 299                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 300                                          <&topckgen CLK_TOP_UART_SEL>;
 301                 status = "disabled";
 302         };
 303
 304         uart2: serial@11004000 {
 305                 compatible = "mediatek,mt6577-uart";
 306                 reg = <0 0x11004000 0 0x400>;
 307                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 308                 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 309                         <&infracfg CLK_INFRA_UART2_CK>;
 310                 clock-names = "baud", "bus";
 311                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 312                                   <&infracfg CLK_INFRA_UART2_SEL>;
 313                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 314                                          <&topckgen CLK_TOP_UART_SEL>;
 315                 status = "disabled";
 316         };
 317
 318         i2c0: i2c@11007000 {
 319                 compatible = "mediatek,mt7981-i2c";
 320                 reg = <0 0x11007000 0 0x1000>,
 321                       <0 0x10217080 0 0x80>;
 322                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 323                 clock-div = <1>;
 324                 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
 325                          <&infracfg CLK_INFRA_AP_DMA_CK>,
 326                          <&infracfg CLK_INFRA_I2C_MCK_CK>,
 327                          <&infracfg CLK_INFRA_I2C_PCK_CK>;
 328                 clock-names = "main", "dma", "arb", "pmic";
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 status = "disabled";
 332         };
 333
 334         pcie: pcie@11280000 {
 335                 compatible = "mediatek,mt7981-pcie",
 336                              "mediatek,mt7986-pcie";
 337                 device_type = "pci";
 338                 reg = <0 0x11280000 0 0x4000>;
 339                 reg-names = "pcie-mac";
 340                 #address-cells = <3>;
 341                 #size-cells = <2>;
 342                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 343                 bus-range = <0x00 0xff>;
 344                 ranges = <0x82000000 0 0x20000000
 345                           0x0 0x20000000 0 0x10000000>;
 346                 status = "disabled";
 347
 348                 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
 349                          <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
 350                          <&infracfg CLK_INFRA_IPCIER_CK>,
 351                          <&infracfg CLK_INFRA_IPCIEB_CK>;
 352
 353                 phys = <&u3port0 PHY_TYPE_PCIE>;
 354                 phy-names = "pcie-phy";
 355
 356                 #interrupt-cells = <1>;
 357                 interrupt-map-mask = <0 0 0 7>;
 358                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
 359                                 <0 0 0 2 &pcie_intc 1>,
 360                                 <0 0 0 3 &pcie_intc 2>,
 361                                 <0 0 0 4 &pcie_intc 3>;
 362                 pcie_intc: interrupt-controller {
 363                         interrupt-controller;
 364                         #address-cells = <0>;
 365                         #interrupt-cells = <1>;
 366                 };
 367         };
 368
 369         crypto: crypto@10320000 {
 370                 compatible = "inside-secure,safexcel-eip97";
 371                 reg = <0 0x10320000 0 0x40000>;
 372                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 373                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 374                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 375                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 376                 interrupt-names = "ring0", "ring1", "ring2", "ring3";
 377                 clocks = <&topckgen CLK_TOP_EIP97B>;
 378                 clock-names = "top_eip97_ck";
 379                 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
 380                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
 381         };
 382
 383         pio: pinctrl@11d00000 {
 384                 compatible = "mediatek,mt7981-pinctrl";
 385                 reg = <0 0x11d00000 0 0x1000>,
 386                       <0 0x11c00000 0 0x1000>,
 387                       <0 0x11c10000 0 0x1000>,
 388                       <0 0x11d20000 0 0x1000>,
 389                       <0 0x11e00000 0 0x1000>,
 390                       <0 0x11e20000 0 0x1000>,
 391                       <0 0x11f00000 0 0x1000>,
 392                       <0 0x11f10000 0 0x1000>,
 393                       <0 0x1000b000 0 0x1000>;
 394                 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
 395                             "iocfg_rb", "iocfg_lb", "iocfg_bl",
 396                             "iocfg_tm", "iocfg_tl", "eint";
 397                 gpio-controller;
 398                 #gpio-cells = <2>;
 399                 gpio-ranges = <&pio 0 0 56>;
 400                 interrupt-controller;
 401                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 402                 interrupt-parent = <&gic>;
 403                 #interrupt-cells = <2>;
 404
 405                 mdio_pins: mdc-mdio-pins {
 406                         mux {
 407                                 function = "eth";
 408                                 groups = "smi_mdc_mdio";
 409                         };
 410                 };
 411
 412                 uart0_pins: uart0-pins {
 413                         mux {
 414                                 function = "uart";
 415                                 groups = "uart0";
 416                         };
 417                 };
 418
 419                 wifi_dbdc_pins: wifi-dbdc-pins {
 420                         mux {
 421                                 function = "eth";
 422                                 groups = "wf0_mode1";
 423                         };
 424                         conf {
 425                                 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
 426                                        "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
 427                                        "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
 428                                        "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
 429                                        "WF_CBA_RESETB", "WF_DIG_RESETB";
 430                                 drive-strength = <4>;
 431                         };
 432                 };
 433
 434                 gbe_led0_pins: gbe-led0-pins {
 435                         mux {
 436                                 function = "led";
 437                                 groups = "gbe_led0";
 438                         };
 439                 };
 440
 441                 gbe_led1_pins: gbe-led1-pins {
 442                         mux {
 443                                 function = "led";
 444                                 groups = "gbe_led1";
 445                         };
 446                 };
 447         };
 448
 449         ethsys: syscon@15000000 {
 450                 #address-cells = <1>;
 451                 #size-cells = <1>;
 452                 compatible = "mediatek,mt7981-ethsys",
 453                              "syscon";
 454                 reg = <0 0x15000000 0 0x1000>;
 455                 #clock-cells = <1>;
 456                 #reset-cells = <1>;
 457         };
 458
 459         wed: wed@15010000 {
 460                 compatible = "mediatek,mt7981-wed",
 461                              "mediatek,mt7986-wed",
 462                              "syscon";
 463                 reg = <0 0x15010000 0 0x1000>;
 464                 interrupt-parent = <&gic>;
 465                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 466                 memory-region = <&wo_emi0>, <&wo_data>;
 467                 memory-region-names = "wo-emi", "wo-data";
 468                 mediatek,wo-ccif = <&wo_ccif0>;
 469                 mediatek,wo-ilm = <&wo_ilm0>;
 470                 mediatek,wo-dlm = <&wo_dlm0>;
 471                 mediatek,wo-cpuboot = <&wo_cpuboot>;
 472         };
 473
 474         eth: ethernet@15100000 {
 475                 compatible = "mediatek,mt7981-eth";
 476                 reg = <0 0x15100000 0 0x80000>;
 477                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 478                                 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 479                                 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 480                                 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 481                 clocks = <&ethsys CLK_ETH_FE_EN>,
 482                         <&ethsys CLK_ETH_GP2_EN>,
 483                         <&ethsys CLK_ETH_GP1_EN>,
 484                         <&ethsys CLK_ETH_WOCPU0_EN>,
 485                         <&sgmiisys0 CLK_SGM0_TX_EN>,
 486                         <&sgmiisys0 CLK_SGM0_RX_EN>,
 487                         <&sgmiisys0 CLK_SGM0_CK0_EN>,
 488                         <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
 489                         <&sgmiisys1 CLK_SGM1_TX_EN>,
 490                         <&sgmiisys1 CLK_SGM1_RX_EN>,
 491                         <&sgmiisys1 CLK_SGM1_CK1_EN>,
 492                         <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
 493                         <&topckgen CLK_TOP_SGM_REG>,
 494                         <&topckgen CLK_TOP_NETSYS_SEL>,
 495                         <&topckgen CLK_TOP_NETSYS_500M_SEL>;
 496                 clock-names = "fe", "gp2", "gp1", "wocpu0",
 497                                         "sgmii_tx250m", "sgmii_rx250m",
 498                                         "sgmii_cdr_ref", "sgmii_cdr_fb",
 499                                         "sgmii2_tx250m", "sgmii2_rx250m",
 500                                         "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 501                                         "sgmii_ck", "netsys0", "netsys1";
 502                 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
 503                                   <&topckgen CLK_TOP_SGM_325M_SEL>;
 504                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
 505                                          <&topckgen CLK_TOP_CB_SGM_325M>;
 506                 mediatek,ethsys = <&ethsys>;
 507                 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 508                 mediatek,infracfg = <&topmisc>;
 509                 mediatek,wed = <&wed>;
 510                 #reset-cells = <1>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 status = "disabled";
 514
 515                 mdio_bus: mdio-bus {
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518
 519                         int_gbe_phy: ethernet-phy@0 {
 520                                 reg = <0>;
 521                                 compatible = "ethernet-phy-ieee802.3-c22";
 522                                 phy-mode = "gmii";
 523                                 phy-is-integrated;
 524                                 nvmem-cells = <&phy_calibration>;
 525                                 nvmem-cell-names = "phy-cal-data";
 526
 527                                 leds {
 528                                         #address-cells = <1>;
 529                                         #size-cells = <0>;
 530
 531                                         int_gbe_phy_led0: int-gbe-phy-led0@0 {
 532                                                 reg = <0>;
 533                                                 function = LED_FUNCTION_LAN;
 534                                                 status = "disabled";
 535                                         };
 536
 537                                         int_gbe_phy_led1: int-gbe-phy-led1@1 {
 538                                                 reg = <1>;
 539                                                 function = LED_FUNCTION_LAN;
 540                                                 status = "disabled";
 541                                         };
 542                                 };
 543                         };
 544                 };
 545         };
 546
 547         wo_dlm0: syscon@151e8000 {
 548                 compatible = "mediatek,mt7986-wo-dlm", "syscon";
 549                 reg = <0 0x151e8000 0 0x2000>;
 550         };
 551
 552         wo_ilm0: syscon@151e0000 {
 553                 compatible = "mediatek,mt7986-wo-ilm", "syscon";
 554                 reg = <0 0x151e0000 0 0x8000>;
 555         };
 556
 557         wo_cpuboot: syscon@15194000 {
 558                 compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
 559                 reg = <0 0x15194000 0 0x1000>;
 560         };
 561
 562         wo_ccif0: syscon@151a5000 {
 563                 compatible = "mediatek,mt7986-wo-ccif", "syscon";
 564                 reg = <0 0x151a5000 0 0x1000>;
 565                 interrupt-parent = <&gic>;
 566                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 567         };
 568
 569         sgmiisys0: syscon@10060000 {
 570                 compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
 571                 reg = <0 0x10060000 0 0x1000>;
 572                 mediatek,pnswap;
 573                 #clock-cells = <1>;
 574         };
 575
 576         sgmiisys1: syscon@10070000 {
 577                 compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
 578                 reg = <0 0x10070000 0 0x1000>;
 579                 #clock-cells = <1>;
 580         };
 581
 582         topmisc: topmisc@11d10000 {
 583                 compatible = "mediatek,mt7981-topmisc", "syscon";
 584                 reg = <0 0x11d10000 0 0x10000>;
 585                 #clock-cells = <1>;
 586         };
 587
 588         snand: snfi@11005000 {
 589                 compatible = "mediatek,mt7986-snand";
 590                 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
 591                 reg-names = "nfi", "ecc";
 592                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
 594                          <&infracfg CLK_INFRA_NFI1_CK>,
 595                          <&infracfg CLK_INFRA_NFI_HCK_CK>;
 596                 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 597                 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
 598                                   <&topckgen CLK_TOP_NFI1X_SEL>;
 599                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
 600                                          <&topckgen CLK_TOP_CB_M_D8>;
 601                 #address-cells = <1>;
 602                 #size-cells = <0>;
 603                 status = "disabled";
 604         };
 605
 606         mmc0: mmc@11230000 {
 607                 compatible = "mediatek,mt7986-mmc",
 608                                         "mediatek,mt7981-mmc";
 609                 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
 610                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 611                 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
 612                          <&infracfg CLK_INFRA_MSDC_HCK_CK>,
 613                          <&infracfg CLK_INFRA_MSDC_66M_CK>,
 614                          <&infracfg CLK_INFRA_MSDC_133M_CK>;
 615                 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
 616                                   <&topckgen CLK_TOP_EMMC_400M_SEL>;
 617                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
 618                                          <&topckgen CLK_TOP_CB_NET2_D2>;
 619                 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
 620                 status = "disabled";
 621         };
 622
 623         wed_pcie: wed_pcie@10003000 {
 624                 compatible = "mediatek,wed_pcie";
 625                 reg = <0 0x10003000 0 0x10>;
 626         };
 627
 628         spi0: spi@1100a000 {
 629                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 630                 #address-cells = <1>;
 631                 #size-cells = <0>;
 632                 reg = <0 0x1100a000 0 0x100>;
 633                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 635                          <&topckgen CLK_TOP_SPI_SEL>,
 636                          <&infracfg CLK_INFRA_SPI0_CK>,
 637                          <&infracfg CLK_INFRA_SPI0_HCK_CK>;
 638
 639                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 640                 status = "disabled";
 641         };
 642
 643         spi1: spi@1100b000 {
 644                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 reg = <0 0x1100b000 0 0x100>;
 648                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 650                          <&topckgen CLK_TOP_SPIM_MST_SEL>,
 651                          <&infracfg CLK_INFRA_SPI1_CK>,
 652                          <&infracfg CLK_INFRA_SPI1_HCK_CK>;
 653                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 654                 status = "disabled";
 655         };
 656
 657         spi2: spi@11009000 {
 658                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 659                 #address-cells = <1>;
 660                 #size-cells = <0>;
 661                 reg = <0 0x11009000 0 0x100>;
 662                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 663                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 664                          <&topckgen CLK_TOP_SPI_SEL>,
 665                          <&infracfg CLK_INFRA_SPI2_CK>,
 666                          <&infracfg CLK_INFRA_SPI2_HCK_CK>;
 667                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 668                 status = "disabled";
 669         };
 670
 671         consys: consys@10000000 {
 672                 compatible = "mediatek,mt7981-consys";
 673                 reg = <0 0x10000000 0 0x8600000>;
 674                 memory-region = <&wmcpu_emi>;
 675         };
 676
 677         xhci: usb@11200000 {
 678                 compatible = "mediatek,mt7986-xhci",
 679                              "mediatek,mtk-xhci";
 680                 reg = <0 0x11200000 0 0x2e00>,
 681                       <0 0x11203e00 0 0x0100>;
 682                 reg-names = "mac", "ippc";
 683                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 684                 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
 685                          <&infracfg CLK_INFRA_IUSB_CK>,
 686                          <&infracfg CLK_INFRA_IUSB_133_CK>,
 687                          <&infracfg CLK_INFRA_IUSB_66M_CK>,
 688                          <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
 689                 clock-names = "sys_ck",
 690                               "ref_ck",
 691                               "mcu_ck",
 692                               "dma_ck",
 693                               "xhci_ck";
 694                 phys = <&u2port0 PHY_TYPE_USB2>,
 695                        <&u3port0 PHY_TYPE_USB3>;
 696                 vusb33-supply = <&reg_3p3v>;
 697                 status = "disabled";
 698         };
 699
 700         usb_phy: usb-phy@11e10000 {
 701                 compatible = "mediatek,mt7981",
 702                              "mediatek,generic-tphy-v2";
 703                 #address-cells = <1>;
 704                 #size-cells = <1>;
 705                 ranges = <0 0 0x11e10000 0x1700>;
 706                 status = "disabled";
 707
 708                 u2port0: usb-phy@0 {
 709                         reg = <0x0 0x700>;
 710                         clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
 711                         clock-names = "ref";
 712                         #phy-cells = <1>;
 713                 };
 714
 715                 u3port0: usb-phy@700 {
 716                         reg = <0x700 0x900>;
 717                         clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
 718                         clock-names = "ref";
 719                         #phy-cells = <1>;
 720                         mediatek,syscon-type = <&topmisc 0x218 0>;
 721                         status = "okay";
 722                 };
 723         };
 724
 725         reg_3p3v: regulator-3p3v {
 726                 compatible = "regulator-fixed";
 727                 regulator-name = "fixed-3.3V";
 728                 regulator-min-microvolt = <3300000>;
 729                 regulator-max-microvolt = <3300000>;
 730                 regulator-boot-on;
 731                 regulator-always-on;
 732         };
 733
 734         efuse: efuse@11f20000 {
 735                 compatible = "mediatek,mt7981-efuse",
 736                              "mediatek,efuse";
 737                 reg = <0 0x11f20000 0 0x1000>;
 738                 #address-cells = <1>;
 739                 #size-cells = <1>;
 740                 status = "okay";
 741
 742                 thermal_calibration: thermal-calib@274 {
 743                         reg = <0x274 0xc>;
 744                 };
 745
 746                 phy_calibration: phy-calib@8dc {
 747                         reg = <0x8dc 0x10>;
 748                 };
 749
 750                 comb_rx_imp_p0: usb3-rx-imp@8c8 {
 751                         reg = <0x8c8 1>;
 752                         bits = <0 5>;
 753                 };
 754
 755                 comb_tx_imp_p0: usb3-tx-imp@8c8 {
 756                         reg = <0x8c8 2>;
 757                         bits = <5 5>;
 758                 };
 759
 760                 comb_intr_p0: usb3-intr@8c9 {
 761                         reg = <0x8c9 1>;
 762                         bits = <2 6>;
 763                 };
 764         };
 765
 766         afe: audio-controller@11210000 {
 767                 compatible = "mediatek,mt79xx-audio";
 768                 reg = <0 0x11210000 0 0x9000>;
 769                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 770                 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
 771                          <&infracfg CLK_INFRA_AUD_26M_CK>,
 772                          <&infracfg CLK_INFRA_AUD_L_CK>,
 773                          <&infracfg CLK_INFRA_AUD_AUD_CK>,
 774                          <&infracfg CLK_INFRA_AUD_EG2_CK>,
 775                          <&topckgen CLK_TOP_AUD_SEL>;
 776                 clock-names = "aud_bus_ck",
 777                               "aud_26m_ck",
 778                               "aud_l_ck",
 779                               "aud_aud_ck",
 780                               "aud_eg2_ck",
 781                               "aud_sel";
 782                 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
 783                                   <&topckgen CLK_TOP_A1SYS_SEL>,
 784                                   <&topckgen CLK_TOP_AUD_L_SEL>,
 785                                   <&topckgen CLK_TOP_A_TUNER_SEL>;
 786                 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
 787                                          <&topckgen CLK_TOP_APLL2_D4>,
 788                                          <&topckgen CLK_TOP_CB_APLL2_196M>,
 789                                          <&topckgen CLK_TOP_APLL2_D4>;
 790                 status = "disabled";
 791         };
 792
 793         ice: ice_debug {
 794                 compatible = "mediatek,mt7981-ice_debug",
 795                            "mediatek,mt2701-ice_debug";
 796                 clocks = <&infracfg CLK_INFRA_DBG_CK>;
 797                 clock-names = "ice_dbg";
 798         };
 799
 800         wifi: wifi@18000000 {
 801                 compatible = "mediatek,mt7981-wmac";
 802                 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
 803                 reset-names = "consys";
 804                 pinctrl-0 = <&wifi_dbdc_pins>;
 805                 pinctrl-names = "dbdc";
 806                 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
 807                          <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
 808                 clock-names = "mcu", "ap2conn";
 809                 reg = <0 0x18000000 0 0x1000000>,
 810                       <0 0x10003000 0 0x1000>,
 811                       <0 0x11d10000 0 0x1000>;
 812                 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 813                              <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 814                              <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 815                              <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 816                 memory-region = <&wmcpu_emi>;
 817                 status = "disabled";
 818         };
 819 };